1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams, FakeIntPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import xiangshan.backend.datapath.WakeUpConfig 47import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 48 49import scala.math.min 50 51case object XSTileKey extends Field[Seq[XSCoreParameters]] 52 53case object XSCoreParamsKey extends Field[XSCoreParameters] 54 55case class XSCoreParameters 56( 57 HasPrefetch: Boolean = false, 58 HartId: Int = 0, 59 XLEN: Int = 64, 60 VLEN: Int = 128, 61 ELEN: Int = 64, 62 HasMExtension: Boolean = true, 63 HasCExtension: Boolean = true, 64 HasDiv: Boolean = true, 65 HasICache: Boolean = true, 66 HasDCache: Boolean = true, 67 AddrBits: Int = 64, 68 VAddrBits: Int = 39, 69 HasFPU: Boolean = true, 70 HasVPU: Boolean = true, 71 HasCustomCSRCacheOp: Boolean = true, 72 FetchWidth: Int = 8, 73 AsidLength: Int = 16, 74 EnableBPU: Boolean = true, 75 EnableBPD: Boolean = true, 76 EnableRAS: Boolean = true, 77 EnableLB: Boolean = false, 78 EnableLoop: Boolean = true, 79 EnableSC: Boolean = true, 80 EnbaleTlbDebug: Boolean = false, 81 EnableClockGate: Boolean = true, 82 EnableJal: Boolean = false, 83 EnableFauFTB: Boolean = true, 84 UbtbGHRLength: Int = 4, 85 // HistoryLength: Int = 512, 86 EnableGHistDiff: Boolean = true, 87 EnableCommitGHistDiff: Boolean = true, 88 UbtbSize: Int = 256, 89 FtbSize: Int = 2048, 90 RasSize: Int = 16, 91 RasSpecSize: Int = 32, 92 RasCtrSize: Int = 3, 93 CacheLineSize: Int = 512, 94 FtbWays: Int = 4, 95 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 96 // Sets Hist Tag 97 // Seq(( 2048, 2, 8), 98 // ( 2048, 9, 8), 99 // ( 2048, 13, 8), 100 // ( 2048, 20, 8), 101 // ( 2048, 26, 8), 102 // ( 2048, 44, 8), 103 // ( 2048, 73, 8), 104 // ( 2048, 256, 8)), 105 Seq(( 4096, 8, 8), 106 ( 4096, 13, 8), 107 ( 4096, 32, 8), 108 ( 4096, 119, 8)), 109 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 110 // Sets Hist Tag 111 Seq(( 256, 4, 9), 112 ( 256, 8, 9), 113 ( 512, 13, 9), 114 ( 512, 16, 9), 115 ( 512, 32, 9)), 116 SCNRows: Int = 512, 117 SCNTables: Int = 4, 118 SCCtrBits: Int = 6, 119 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 120 numBr: Int = 2, 121 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 122 ((resp_in: BranchPredictionResp, p: Parameters) => { 123 val ftb = Module(new FTB()(p)) 124 val ubtb =Module(new FauFTB()(p)) 125 // val bim = Module(new BIM()(p)) 126 val tage = Module(new Tage_SC()(p)) 127 val ras = Module(new RAS()(p)) 128 val ittage = Module(new ITTage()(p)) 129 val preds = Seq(ubtb, tage, ftb, ittage, ras) 130 preds.map(_.io := DontCare) 131 132 // ubtb.io.resp_in(0) := resp_in 133 // bim.io.resp_in(0) := ubtb.io.resp 134 // btb.io.resp_in(0) := bim.io.resp 135 // tage.io.resp_in(0) := btb.io.resp 136 // loop.io.resp_in(0) := tage.io.resp 137 ubtb.io.in.bits.resp_in(0) := resp_in 138 tage.io.in.bits.resp_in(0) := ubtb.io.out 139 ftb.io.in.bits.resp_in(0) := tage.io.out 140 ittage.io.in.bits.resp_in(0) := ftb.io.out 141 ras.io.in.bits.resp_in(0) := ittage.io.out 142 143 (preds, ras.io.out) 144 }), 145 ICacheECCForceError: Boolean = false, 146 IBufSize: Int = 48, 147 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 148 DecodeWidth: Int = 6, 149 RenameWidth: Int = 6, 150 CommitWidth: Int = 6, 151 MaxUopSize: Int = 65, 152 EnableRenameSnapshot: Boolean = true, 153 RenameSnapshotNum: Int = 4, 154 FtqSize: Int = 64, 155 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 156 IntLogicRegs: Int = 32, 157 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 158 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 159 VCONFIG_IDX: Int = 32, 160 NRPhyRegs: Int = 192, 161 VirtualLoadQueueSize: Int = 72, 162 LoadQueueRARSize: Int = 72, 163 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 164 RollbackGroupSize: Int = 8, 165 LoadQueueReplaySize: Int = 72, 166 LoadUncacheBufferSize: Int = 20, 167 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 168 StoreQueueSize: Int = 64, 169 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 170 StoreQueueForwardWithMask: Boolean = true, 171 VlsQueueSize: Int = 8, 172 RobSize: Int = 160, 173 RabSize: Int = 256, 174 VTypeBufferSize: Int = 64, // used to reorder vtype 175 IssueQueueSize: Int = 24, 176 IssueQueueCompEntrySize: Int = 16, 177 dpParams: DispatchParameters = DispatchParameters( 178 IntDqSize = 16, 179 FpDqSize = 16, 180 LsDqSize = 18, 181 IntDqDeqWidth = 8, 182 FpDqDeqWidth = 6, 183 LsDqDeqWidth = 6, 184 ), 185 intPreg: PregParams = IntPregParams( 186 numEntries = 224, 187 numRead = None, 188 numWrite = None, 189 ), 190 vfPreg: VfPregParams = VfPregParams( 191 numEntries = 192, 192 numRead = None, 193 numWrite = None, 194 ), 195 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 196 LoadPipelineWidth: Int = 3, 197 StorePipelineWidth: Int = 2, 198 VecLoadPipelineWidth: Int = 2, 199 VecStorePipelineWidth: Int = 2, 200 VecMemSrcInWidth: Int = 2, 201 VecMemInstWbWidth: Int = 1, 202 VecMemDispatchWidth: Int = 1, 203 StoreBufferSize: Int = 16, 204 StoreBufferThreshold: Int = 7, 205 EnsbufferWidth: Int = 2, 206 // ============ VLSU ============ 207 UsQueueSize: Int = 8, 208 VlFlowSize: Int = 32, 209 VlUopSize: Int = 32, 210 VsFlowL1Size: Int = 128, 211 VsFlowL2Size: Int = 32, 212 VsFlow128L2Size: Int = 8, 213 VsUopSize: Int = 32, 214 // ============================== 215 UncacheBufferSize: Int = 4, 216 EnableLoadToLoadForward: Boolean = false, 217 EnableFastForward: Boolean = true, 218 EnableLdVioCheckAfterReset: Boolean = true, 219 EnableSoftPrefetchAfterReset: Boolean = true, 220 EnableCacheErrorAfterReset: Boolean = true, 221 EnableAccurateLoadError: Boolean = true, 222 EnableUncacheWriteOutstanding: Boolean = false, 223 EnableStorePrefetchAtIssue: Boolean = false, 224 EnableStorePrefetchAtCommit: Boolean = false, 225 EnableAtCommitMissTrigger: Boolean = true, 226 EnableStorePrefetchSMS: Boolean = false, 227 EnableStorePrefetchSPB: Boolean = false, 228 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 229 ReSelectLen: Int = 7, // load replay queue replay select counter len 230 iwpuParameters: WPUParameters = WPUParameters( 231 enWPU = false, 232 algoName = "mmru", 233 isICache = true, 234 ), 235 dwpuParameters: WPUParameters = WPUParameters( 236 enWPU = false, 237 algoName = "mmru", 238 enCfPred = false, 239 isICache = false, 240 ), 241 itlbParameters: TLBParameters = TLBParameters( 242 name = "itlb", 243 fetchi = true, 244 useDmode = false, 245 NWays = 48, 246 ), 247 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 248 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 249 ldtlbParameters: TLBParameters = TLBParameters( 250 name = "ldtlb", 251 NWays = 48, 252 outReplace = false, 253 partialStaticPMP = true, 254 outsideRecvFlush = true, 255 saveLevel = true 256 ), 257 sttlbParameters: TLBParameters = TLBParameters( 258 name = "sttlb", 259 NWays = 48, 260 outReplace = false, 261 partialStaticPMP = true, 262 outsideRecvFlush = true, 263 saveLevel = true 264 ), 265 hytlbParameters: TLBParameters = TLBParameters( 266 name = "hytlb", 267 NWays = 48, 268 outReplace = false, 269 partialStaticPMP = true, 270 outsideRecvFlush = true, 271 saveLevel = true 272 ), 273 pftlbParameters: TLBParameters = TLBParameters( 274 name = "pftlb", 275 NWays = 48, 276 outReplace = false, 277 partialStaticPMP = true, 278 outsideRecvFlush = true, 279 saveLevel = true 280 ), 281 refillBothTlb: Boolean = false, 282 btlbParameters: TLBParameters = TLBParameters( 283 name = "btlb", 284 NWays = 48, 285 ), 286 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 287 NumPerfCounters: Int = 16, 288 icacheParameters: ICacheParameters = ICacheParameters( 289 tagECC = Some("parity"), 290 dataECC = Some("parity"), 291 replacer = Some("setplru"), 292 nMissEntries = 2, 293 nProbeEntries = 2, 294 nPrefetchEntries = 12, 295 nPrefBufferEntries = 32, 296 ), 297 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 298 tagECC = Some("secded"), 299 dataECC = Some("secded"), 300 replacer = Some("setplru"), 301 nMissEntries = 16, 302 nProbeEntries = 8, 303 nReleaseEntries = 18, 304 nMaxPrefetchEntry = 6, 305 )), 306 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 307 name = "l2", 308 ways = 8, 309 sets = 1024, // default 512KB L2 310 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 311 )), 312 L2NBanks: Int = 1, 313 usePTWRepeater: Boolean = false, 314 softTLB: Boolean = false, // dpi-c l1tlb debug only 315 softPTW: Boolean = false, // dpi-c l2tlb debug only 316 softPTWDelay: Int = 1 317){ 318 def vlWidth = log2Up(VLEN) + 1 319 320 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 321 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 322 323 val intSchdParams = { 324 implicit val schdType: SchedulerType = IntScheduler() 325 SchdBlockParams(Seq( 326 IssueBlockParams(Seq( 327 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 328 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(7, 1))), true, 2), 329 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 330 IssueBlockParams(Seq( 331 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 332 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 2, 1)), Seq(Seq(IntRD(9, 0)), Seq(IntRD(5, 1))), true, 2), 333 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 334 IssueBlockParams(Seq( 335 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 336 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, CsrCfg, FenceCfg, I2vCfg), Seq(IntWB(port = 3, 1), VfWB(4, 0)), Seq(Seq(IntRD(10, 0)), Seq(IntRD(3, 1)))), 337 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 338 IssueBlockParams(Seq( 339 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 340 ExeUnitParams("BJU3", Seq(DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(11, 0)), Seq(IntRD(1, 1)))), 341 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 342 ), 343 numPregs = intPreg.numEntries, 344 numDeqOutside = 0, 345 schdType = schdType, 346 rfDataWidth = intPreg.dataCfg.dataWidth, 347 numUopIn = dpParams.IntDqDeqWidth, 348 ) 349 } 350 val vfSchdParams = { 351 implicit val schdType: SchedulerType = VfScheduler() 352 SchdBlockParams(Seq( 353 IssueBlockParams(Seq( 354 ExeUnitParams("VFEX0", Seq(VfaluCfg, VfmaCfg, VialuCfg, VimacCfg), Seq(VfWB(port = 5, 0), IntWB(port = 0, 1)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 355 ExeUnitParams("VFEX1", Seq(VipuCfg, VppuCfg, VfcvtCfg, F2vCfg, VSetRvfWvfCfg), Seq(VfWB(port = 6, 1), IntWB(port = 1, 2)), Seq(Seq(VfRD(5, 1)), Seq(VfRD(6, 1)), Seq(VfRD(7, 1)), Seq(VfRD(8, 1)), Seq(VfRD(9, 1)))), 356 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 357 IssueBlockParams(Seq( 358 ExeUnitParams("VFEX2", Seq(VfaluCfg, VfmaCfg, VialuCfg), Seq(VfWB(port = 6, 0), IntWB(port = 1, 1)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 359 ExeUnitParams("VFEX3", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 5, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(VfRD(3, 1)), Seq(VfRD(4, 1)))), 360 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 361 ), 362 numPregs = vfPreg.numEntries, 363 numDeqOutside = 0, 364 schdType = schdType, 365 rfDataWidth = vfPreg.dataCfg.dataWidth, 366 numUopIn = dpParams.FpDqDeqWidth, 367 ) 368 } 369 370 val memSchdParams = { 371 implicit val schdType: SchedulerType = MemScheduler() 372 val rfDataWidth = 64 373 374 SchdBlockParams(Seq( 375 IssueBlockParams(Seq( 376 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(15, 0)))), 377 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 378 IssueBlockParams(Seq( 379 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(13, 1)))), 380 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 381 IssueBlockParams(Seq( 382 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), VfWB(0, 0)), Seq(Seq(IntRD(12, 0))), true, 2), 383 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 384 IssueBlockParams(Seq( 385 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(1, 0)), Seq(Seq(IntRD(13, 0))), true, 2), 386 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 387 IssueBlockParams(Seq( 388 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(2, 0)), Seq(Seq(IntRD(14, 0))), true, 2), 389 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 390 IssueBlockParams(Seq( 391 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg), Seq(VfWB(3, 0)), Seq(Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(VfRD(12, 0)), Seq(VfRD(13, 0)), Seq(VfRD(14, 0)))), 392 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 393 IssueBlockParams(Seq( 394 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(12, 1), VfRD(12, Int.MaxValue)))), 395 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 396 IssueBlockParams(Seq( 397 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(14, 1), VfRD(13, Int.MaxValue)))), 398 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 399 ), 400 numPregs = intPreg.numEntries max vfPreg.numEntries, 401 numDeqOutside = 0, 402 schdType = schdType, 403 rfDataWidth = rfDataWidth, 404 numUopIn = dpParams.LsDqDeqWidth, 405 ) 406 } 407 408 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 409 410 def iqWakeUpParams = { 411 Seq( 412 WakeUpConfig( 413 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 414 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 415 ), 416 ).flatten 417 } 418 419 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 420 421 val backendParams: BackendParams = backend.BackendParams( 422 Map( 423 IntScheduler() -> intSchdParams, 424 VfScheduler() -> vfSchdParams, 425 MemScheduler() -> memSchdParams, 426 ), 427 Seq( 428 intPreg, 429 vfPreg, 430 fakeIntPreg 431 ), 432 iqWakeUpParams, 433 ) 434} 435 436case object DebugOptionsKey extends Field[DebugOptions] 437 438case class DebugOptions 439( 440 FPGAPlatform: Boolean = false, 441 EnableDifftest: Boolean = false, 442 AlwaysBasicDiff: Boolean = true, 443 EnableDebug: Boolean = false, 444 EnablePerfDebug: Boolean = true, 445 UseDRAMSim: Boolean = false, 446 EnableConstantin: Boolean = false, 447 EnableChiselDB: Boolean = false, 448 AlwaysBasicDB: Boolean = true, 449 EnableTopDown: Boolean = false, 450 EnableRollingDB: Boolean = false 451) 452 453trait HasXSParameter { 454 455 implicit val p: Parameters 456 457 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 458 459 val coreParams = p(XSCoreParamsKey) 460 val env = p(DebugOptionsKey) 461 462 val XLEN = coreParams.XLEN 463 val VLEN = coreParams.VLEN 464 val ELEN = coreParams.ELEN 465 val minFLen = 32 466 val fLen = 64 467 def xLen = XLEN 468 469 val HasMExtension = coreParams.HasMExtension 470 val HasCExtension = coreParams.HasCExtension 471 val HasDiv = coreParams.HasDiv 472 val HasIcache = coreParams.HasICache 473 val HasDcache = coreParams.HasDCache 474 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 475 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 476 val AsidLength = coreParams.AsidLength 477 val ReSelectLen = coreParams.ReSelectLen 478 val AddrBytes = AddrBits / 8 // unused 479 val DataBits = XLEN 480 val DataBytes = DataBits / 8 481 val VDataBytes = VLEN / 8 482 val HasFPU = coreParams.HasFPU 483 val HasVPU = coreParams.HasVPU 484 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 485 val FetchWidth = coreParams.FetchWidth 486 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 487 val EnableBPU = coreParams.EnableBPU 488 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 489 val EnableRAS = coreParams.EnableRAS 490 val EnableLB = coreParams.EnableLB 491 val EnableLoop = coreParams.EnableLoop 492 val EnableSC = coreParams.EnableSC 493 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 494 val HistoryLength = coreParams.HistoryLength 495 val EnableGHistDiff = coreParams.EnableGHistDiff 496 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 497 val EnableClockGate = coreParams.EnableClockGate 498 val UbtbGHRLength = coreParams.UbtbGHRLength 499 val UbtbSize = coreParams.UbtbSize 500 val EnableFauFTB = coreParams.EnableFauFTB 501 val FtbSize = coreParams.FtbSize 502 val FtbWays = coreParams.FtbWays 503 val RasSize = coreParams.RasSize 504 val RasSpecSize = coreParams.RasSpecSize 505 val RasCtrSize = coreParams.RasCtrSize 506 507 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 508 coreParams.branchPredictor(resp_in, p) 509 } 510 val numBr = coreParams.numBr 511 val TageTableInfos = coreParams.TageTableInfos 512 val TageBanks = coreParams.numBr 513 val SCNRows = coreParams.SCNRows 514 val SCCtrBits = coreParams.SCCtrBits 515 val SCHistLens = coreParams.SCHistLens 516 val SCNTables = coreParams.SCNTables 517 518 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 519 case ((n, cb), h) => (n, cb, h) 520 } 521 val ITTageTableInfos = coreParams.ITTageTableInfos 522 type FoldedHistoryInfo = Tuple2[Int, Int] 523 val foldedGHistInfos = 524 (TageTableInfos.map{ case (nRows, h, t) => 525 if (h > 0) 526 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 527 else 528 Set[FoldedHistoryInfo]() 529 }.reduce(_++_).toSet ++ 530 SCTableInfos.map{ case (nRows, _, h) => 531 if (h > 0) 532 Set((h, min(log2Ceil(nRows/TageBanks), h))) 533 else 534 Set[FoldedHistoryInfo]() 535 }.reduce(_++_).toSet ++ 536 ITTageTableInfos.map{ case (nRows, h, t) => 537 if (h > 0) 538 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 539 else 540 Set[FoldedHistoryInfo]() 541 }.reduce(_++_) ++ 542 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 543 ).toList 544 545 546 547 val CacheLineSize = coreParams.CacheLineSize 548 val CacheLineHalfWord = CacheLineSize / 16 549 val ExtHistoryLength = HistoryLength + 64 550 val ICacheECCForceError = coreParams.ICacheECCForceError 551 val IBufSize = coreParams.IBufSize 552 val IBufNBank = coreParams.IBufNBank 553 val backendParams: BackendParams = coreParams.backendParams 554 val DecodeWidth = coreParams.DecodeWidth 555 val RenameWidth = coreParams.RenameWidth 556 val CommitWidth = coreParams.CommitWidth 557 val MaxUopSize = coreParams.MaxUopSize 558 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 559 val RenameSnapshotNum = coreParams.RenameSnapshotNum 560 val FtqSize = coreParams.FtqSize 561 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 562 val IntLogicRegs = coreParams.IntLogicRegs 563 val FpLogicRegs = coreParams.FpLogicRegs 564 val VecLogicRegs = coreParams.VecLogicRegs 565 val VCONFIG_IDX = coreParams.VCONFIG_IDX 566 val IntPhyRegs = coreParams.intPreg.numEntries 567 val VfPhyRegs = coreParams.vfPreg.numEntries 568 val MaxPhyPregs = IntPhyRegs max VfPhyRegs 569 val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 570 val RobSize = coreParams.RobSize 571 val RabSize = coreParams.RabSize 572 val VTypeBufferSize = coreParams.VTypeBufferSize 573 val IntRefCounterWidth = log2Ceil(RobSize) 574 val LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 575 val LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 576 val LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 577 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 578 val LoadQueueRARSize = coreParams.LoadQueueRARSize 579 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 580 val RollbackGroupSize = coreParams.RollbackGroupSize 581 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 582 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 583 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 584 val StoreQueueSize = coreParams.StoreQueueSize 585 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 586 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 587 val VlsQueueSize = coreParams.VlsQueueSize 588 val dpParams = coreParams.dpParams 589 590 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 591 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 592 593 val NumRedirect = backendParams.numRedirect 594 val BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 595 val FtqRedirectAheadNum = NumRedirect 596 val LoadPipelineWidth = coreParams.LoadPipelineWidth 597 val StorePipelineWidth = coreParams.StorePipelineWidth 598 val VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 599 val VecStorePipelineWidth = coreParams.VecStorePipelineWidth 600 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 601 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 602 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 603 val StoreBufferSize = coreParams.StoreBufferSize 604 val StoreBufferThreshold = coreParams.StoreBufferThreshold 605 val EnsbufferWidth = coreParams.EnsbufferWidth 606 val UsQueueSize = coreParams.UsQueueSize 607 val VlFlowSize = coreParams.VlFlowSize 608 val VlUopSize = coreParams.VlUopSize 609 val VsFlowL1Size = coreParams.VsFlowL1Size 610 val VsFlowL2Size = coreParams.VsFlowL2Size 611 val VsFlow128L2Size = coreParams.VsFlow128L2Size 612 val VsUopSize = coreParams.VsUopSize 613 val UncacheBufferSize = coreParams.UncacheBufferSize 614 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 615 val EnableFastForward = coreParams.EnableFastForward 616 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 617 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 618 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 619 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 620 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 621 val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 622 val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 623 val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 624 val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 625 val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 626 val asidLen = coreParams.MMUAsidLen 627 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 628 val refillBothTlb = coreParams.refillBothTlb 629 val iwpuParam = coreParams.iwpuParameters 630 val dwpuParam = coreParams.dwpuParameters 631 val itlbParams = coreParams.itlbParameters 632 val ldtlbParams = coreParams.ldtlbParameters 633 val sttlbParams = coreParams.sttlbParameters 634 val hytlbParams = coreParams.hytlbParameters 635 val pftlbParams = coreParams.pftlbParameters 636 val btlbParams = coreParams.btlbParameters 637 val l2tlbParams = coreParams.l2tlbParameters 638 val NumPerfCounters = coreParams.NumPerfCounters 639 640 val instBytes = if (HasCExtension) 2 else 4 641 val instOffsetBits = log2Ceil(instBytes) 642 643 val icacheParameters = coreParams.icacheParameters 644 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 645 646 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 647 // for constrained LR/SC loop 648 val LRSCCycles = 64 649 // for lr storm 650 val LRSCBackOff = 8 651 652 // cache hierarchy configurations 653 val l1BusDataWidth = 256 654 655 // load violation predict 656 val ResetTimeMax2Pow = 20 //1078576 657 val ResetTimeMin2Pow = 10 //1024 658 // wait table parameters 659 val WaitTableSize = 1024 660 val MemPredPCWidth = log2Up(WaitTableSize) 661 val LWTUse2BitCounter = true 662 // store set parameters 663 val SSITSize = WaitTableSize 664 val LFSTSize = 32 665 val SSIDWidth = log2Up(LFSTSize) 666 val LFSTWidth = 4 667 val StoreSetEnable = true // LWT will be disabled if SS is enabled 668 val LFSTEnable = true 669 670 val PCntIncrStep: Int = 6 671 val numPCntHc: Int = 25 672 val numPCntPtw: Int = 19 673 674 val numCSRPCntFrontend = 8 675 val numCSRPCntCtrl = 8 676 val numCSRPCntLsu = 8 677 val numCSRPCntHc = 5 678 val printEventCoding = true 679 680 // Parameters for Sdtrig extension 681 protected val TriggerNum = 4 682 protected val TriggerChainMaxLength = 2 683} 684