1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import freechips.rocketchip.tile.MaxHartIdBits 31import system.SoCParamsKey 32import huancun._ 33import huancun.debug._ 34import xiangshan.cache.wpu.WPUParameters 35import coupledL2._ 36import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 37 38import scala.math.min 39 40case object XSTileKey extends Field[Seq[XSCoreParameters]] 41 42case object XSCoreParamsKey extends Field[XSCoreParameters] 43 44case class XSCoreParameters 45( 46 HasPrefetch: Boolean = false, 47 HartId: Int = 0, 48 XLEN: Int = 64, 49 VLEN: Int = 128, 50 HasMExtension: Boolean = true, 51 HasCExtension: Boolean = true, 52 HasDiv: Boolean = true, 53 HasICache: Boolean = true, 54 HasDCache: Boolean = true, 55 AddrBits: Int = 64, 56 VAddrBits: Int = 39, 57 HasFPU: Boolean = true, 58 HasCustomCSRCacheOp: Boolean = true, 59 FetchWidth: Int = 8, 60 AsidLength: Int = 16, 61 EnableBPU: Boolean = true, 62 EnableBPD: Boolean = true, 63 EnableRAS: Boolean = true, 64 EnableLB: Boolean = false, 65 EnableLoop: Boolean = true, 66 EnableSC: Boolean = true, 67 EnbaleTlbDebug: Boolean = false, 68 EnableJal: Boolean = false, 69 EnableFauFTB: Boolean = true, 70 UbtbGHRLength: Int = 4, 71 // HistoryLength: Int = 512, 72 EnableGHistDiff: Boolean = true, 73 EnableCommitGHistDiff: Boolean = true, 74 UbtbSize: Int = 256, 75 FtbSize: Int = 2048, 76 RasSize: Int = 16, 77 RasSpecSize: Int = 32, 78 RasCtrSize: Int = 3, 79 CacheLineSize: Int = 512, 80 FtbWays: Int = 4, 81 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 82 // Sets Hist Tag 83 // Seq(( 2048, 2, 8), 84 // ( 2048, 9, 8), 85 // ( 2048, 13, 8), 86 // ( 2048, 20, 8), 87 // ( 2048, 26, 8), 88 // ( 2048, 44, 8), 89 // ( 2048, 73, 8), 90 // ( 2048, 256, 8)), 91 Seq(( 4096, 8, 8), 92 ( 4096, 13, 8), 93 ( 4096, 32, 8), 94 ( 4096, 119, 8)), 95 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 96 // Sets Hist Tag 97 Seq(( 256, 4, 9), 98 ( 256, 8, 9), 99 ( 512, 13, 9), 100 ( 512, 16, 9), 101 ( 512, 32, 9)), 102 SCNRows: Int = 512, 103 SCNTables: Int = 4, 104 SCCtrBits: Int = 6, 105 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 106 numBr: Int = 2, 107 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 108 ((resp_in: BranchPredictionResp, p: Parameters) => { 109 val ftb = Module(new FTB()(p)) 110 val ubtb =Module(new FauFTB()(p)) 111 // val bim = Module(new BIM()(p)) 112 val tage = Module(new Tage_SC()(p)) 113 val ras = Module(new RAS()(p)) 114 val ittage = Module(new ITTage()(p)) 115 val preds = Seq(ubtb, tage, ftb, ittage, ras) 116 preds.map(_.io := DontCare) 117 118 // ubtb.io.resp_in(0) := resp_in 119 // bim.io.resp_in(0) := ubtb.io.resp 120 // btb.io.resp_in(0) := bim.io.resp 121 // tage.io.resp_in(0) := btb.io.resp 122 // loop.io.resp_in(0) := tage.io.resp 123 ubtb.io.in.bits.resp_in(0) := resp_in 124 tage.io.in.bits.resp_in(0) := ubtb.io.out 125 ftb.io.in.bits.resp_in(0) := tage.io.out 126 ittage.io.in.bits.resp_in(0) := ftb.io.out 127 ras.io.in.bits.resp_in(0) := ittage.io.out 128 129 (preds, ras.io.out) 130 }), 131 ICacheECCForceError: Boolean = false, 132 IBufSize: Int = 48, 133 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 134 DecodeWidth: Int = 6, 135 RenameWidth: Int = 6, 136 CommitWidth: Int = 6, 137 EnableRenameSnapshot: Boolean = true, 138 RenameSnapshotNum: Int = 4, 139 FtqSize: Int = 64, 140 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 141 IssQueSize: Int = 16, 142 NRPhyRegs: Int = 192, 143 VirtualLoadQueueSize: Int = 80, 144 LoadQueueRARSize: Int = 80, 145 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 146 RollbackGroupSize: Int = 8, 147 LoadQueueReplaySize: Int = 72, 148 LoadUncacheBufferSize: Int = 20, 149 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 150 StoreQueueSize: Int = 64, 151 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 152 StoreQueueForwardWithMask: Boolean = true, 153 VlsQueueSize: Int = 8, 154 RobSize: Int = 256, 155 dpParams: DispatchParameters = DispatchParameters( 156 IntDqSize = 16, 157 FpDqSize = 16, 158 LsDqSize = 16, 159 IntDqDeqWidth = 4, 160 FpDqDeqWidth = 4, 161 LsDqDeqWidth = 4 162 ), 163 exuParameters: ExuParameters = ExuParameters( 164 JmpCnt = 1, 165 AluCnt = 4, 166 MulCnt = 0, 167 MduCnt = 2, 168 FmacCnt = 4, 169 FmiscCnt = 2, 170 FmiscDivSqrtCnt = 0, 171 LduCnt = 2, 172 StuCnt = 2 173 ), 174 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 175 LoadPipelineWidth: Int = 2, 176 StorePipelineWidth: Int = 2, 177 VecMemSrcInWidth: Int = 2, 178 VecMemInstWbWidth: Int = 1, 179 VecMemDispatchWidth: Int = 1, 180 StoreBufferSize: Int = 16, 181 StoreBufferThreshold: Int = 7, 182 EnsbufferWidth: Int = 2, 183 UncacheBufferSize: Int = 4, 184 EnableLoadToLoadForward: Boolean = false, 185 EnableFastForward: Boolean = true, 186 EnableLdVioCheckAfterReset: Boolean = true, 187 EnableSoftPrefetchAfterReset: Boolean = true, 188 EnableCacheErrorAfterReset: Boolean = true, 189 EnableAccurateLoadError: Boolean = true, 190 EnableUncacheWriteOutstanding: Boolean = false, 191 EnableStorePrefetchAtIssue: Boolean = false, 192 EnableStorePrefetchAtCommit: Boolean = false, 193 EnableAtCommitMissTrigger: Boolean = true, 194 EnableStorePrefetchSMS: Boolean = false, 195 EnableStorePrefetchSPB: Boolean = false, 196 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 197 ReSelectLen: Int = 7, // load replay queue replay select counter len 198 iwpuParameters: WPUParameters = WPUParameters( 199 enWPU = false, 200 algoName = "mmru", 201 isICache = true, 202 ), 203 dwpuParameters: WPUParameters = WPUParameters( 204 enWPU = false, 205 algoName = "mmru", 206 enCfPred = false, 207 isICache = false, 208 ), 209 itlbParameters: TLBParameters = TLBParameters( 210 name = "itlb", 211 fetchi = true, 212 useDmode = false, 213 NWays = 48, 214 ), 215 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 216 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 217 ldtlbParameters: TLBParameters = TLBParameters( 218 name = "ldtlb", 219 NWays = 48, 220 outReplace = false, 221 partialStaticPMP = true, 222 outsideRecvFlush = true, 223 saveLevel = true 224 ), 225 sttlbParameters: TLBParameters = TLBParameters( 226 name = "sttlb", 227 NWays = 48, 228 outReplace = false, 229 partialStaticPMP = true, 230 outsideRecvFlush = true, 231 saveLevel = true 232 ), 233 pftlbParameters: TLBParameters = TLBParameters( 234 name = "pftlb", 235 NWays = 48, 236 outReplace = false, 237 partialStaticPMP = true, 238 outsideRecvFlush = true, 239 saveLevel = true 240 ), 241 refillBothTlb: Boolean = false, 242 btlbParameters: TLBParameters = TLBParameters( 243 name = "btlb", 244 NWays = 48, 245 ), 246 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 247 NumPerfCounters: Int = 16, 248 icacheParameters: ICacheParameters = ICacheParameters( 249 tagECC = Some("parity"), 250 dataECC = Some("parity"), 251 replacer = Some("setplru"), 252 nMissEntries = 2, 253 nProbeEntries = 2, 254 nPrefetchEntries = 12, 255 nPrefBufferEntries = 32, 256 ), 257 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 258 tagECC = Some("secded"), 259 dataECC = Some("secded"), 260 replacer = Some("setplru"), 261 nMissEntries = 16, 262 nProbeEntries = 8, 263 nReleaseEntries = 18, 264 nMaxPrefetchEntry = 6, 265 )), 266 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 267 name = "l2", 268 ways = 8, 269 sets = 1024, // default 512KB L2 270 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 271 )), 272 L2NBanks: Int = 1, 273 usePTWRepeater: Boolean = false, 274 softTLB: Boolean = false, // dpi-c l1tlb debug only 275 softPTW: Boolean = false, // dpi-c l2tlb debug only 276 softPTWDelay: Int = 1 277){ 278 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 279 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 280 281 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 282 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 283 284 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 285 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 286 287 val fpExuConfigs = 288 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 289 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 290 291 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 292} 293 294case object DebugOptionsKey extends Field[DebugOptions] 295 296case class DebugOptions 297( 298 FPGAPlatform: Boolean = false, 299 EnableDifftest: Boolean = false, 300 AlwaysBasicDiff: Boolean = true, 301 EnableDebug: Boolean = false, 302 EnablePerfDebug: Boolean = true, 303 UseDRAMSim: Boolean = false, 304 EnableConstantin: Boolean = false, 305 EnableChiselDB: Boolean = false, 306 AlwaysBasicDB: Boolean = true, 307 EnableRollingDB: Boolean = false 308) 309 310trait HasXSParameter { 311 312 implicit val p: Parameters 313 314 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 315 316 val coreParams = p(XSCoreParamsKey) 317 val env = p(DebugOptionsKey) 318 319 val XLEN = coreParams.XLEN 320 val VLEN = coreParams.VLEN 321 val minFLen = 32 322 val fLen = 64 323 val hartIdLen = p(MaxHartIdBits) 324 def xLen = XLEN 325 326 val HasMExtension = coreParams.HasMExtension 327 val HasCExtension = coreParams.HasCExtension 328 val HasDiv = coreParams.HasDiv 329 val HasIcache = coreParams.HasICache 330 val HasDcache = coreParams.HasDCache 331 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 332 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 333 val AsidLength = coreParams.AsidLength 334 val ReSelectLen = coreParams.ReSelectLen 335 val AddrBytes = AddrBits / 8 // unused 336 val DataBits = XLEN 337 val DataBytes = DataBits / 8 338 val VDataBytes = VLEN / 8 339 val HasFPU = coreParams.HasFPU 340 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 341 val FetchWidth = coreParams.FetchWidth 342 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 343 val EnableBPU = coreParams.EnableBPU 344 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 345 val EnableRAS = coreParams.EnableRAS 346 val EnableLB = coreParams.EnableLB 347 val EnableLoop = coreParams.EnableLoop 348 val EnableSC = coreParams.EnableSC 349 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 350 val HistoryLength = coreParams.HistoryLength 351 val EnableGHistDiff = coreParams.EnableGHistDiff 352 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 353 val UbtbGHRLength = coreParams.UbtbGHRLength 354 val UbtbSize = coreParams.UbtbSize 355 val EnableFauFTB = coreParams.EnableFauFTB 356 val FtbSize = coreParams.FtbSize 357 val FtbWays = coreParams.FtbWays 358 val RasSize = coreParams.RasSize 359 val RasSpecSize = coreParams.RasSpecSize 360 val RasCtrSize = coreParams.RasCtrSize 361 362 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 363 coreParams.branchPredictor(resp_in, p) 364 } 365 val numBr = coreParams.numBr 366 val TageTableInfos = coreParams.TageTableInfos 367 val TageBanks = coreParams.numBr 368 val SCNRows = coreParams.SCNRows 369 val SCCtrBits = coreParams.SCCtrBits 370 val SCHistLens = coreParams.SCHistLens 371 val SCNTables = coreParams.SCNTables 372 373 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 374 case ((n, cb), h) => (n, cb, h) 375 } 376 val ITTageTableInfos = coreParams.ITTageTableInfos 377 type FoldedHistoryInfo = Tuple2[Int, Int] 378 val foldedGHistInfos = 379 (TageTableInfos.map{ case (nRows, h, t) => 380 if (h > 0) 381 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 382 else 383 Set[FoldedHistoryInfo]() 384 }.reduce(_++_).toSet ++ 385 SCTableInfos.map{ case (nRows, _, h) => 386 if (h > 0) 387 Set((h, min(log2Ceil(nRows/TageBanks), h))) 388 else 389 Set[FoldedHistoryInfo]() 390 }.reduce(_++_).toSet ++ 391 ITTageTableInfos.map{ case (nRows, h, t) => 392 if (h > 0) 393 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 394 else 395 Set[FoldedHistoryInfo]() 396 }.reduce(_++_) ++ 397 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 398 ).toList 399 400 401 402 val CacheLineSize = coreParams.CacheLineSize 403 val CacheLineHalfWord = CacheLineSize / 16 404 val ExtHistoryLength = HistoryLength + 64 405 val ICacheECCForceError = coreParams.ICacheECCForceError 406 val IBufSize = coreParams.IBufSize 407 val IBufNBank = coreParams.IBufNBank 408 val DecodeWidth = coreParams.DecodeWidth 409 val RenameWidth = coreParams.RenameWidth 410 val CommitWidth = coreParams.CommitWidth 411 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 412 val RenameSnapshotNum = coreParams.RenameSnapshotNum 413 val FtqSize = coreParams.FtqSize 414 val IssQueSize = coreParams.IssQueSize 415 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 416 val NRPhyRegs = coreParams.NRPhyRegs 417 val PhyRegIdxWidth = log2Up(NRPhyRegs) 418 val RobSize = coreParams.RobSize 419 val IntRefCounterWidth = log2Ceil(RobSize) 420 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 421 val LoadQueueRARSize = coreParams.LoadQueueRARSize 422 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 423 val RollbackGroupSize = coreParams.RollbackGroupSize 424 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 425 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 426 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 427 val StoreQueueSize = coreParams.StoreQueueSize 428 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 429 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 430 val VlsQueueSize = coreParams.VlsQueueSize 431 val dpParams = coreParams.dpParams 432 val exuParameters = coreParams.exuParameters 433 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 434 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 435 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 436 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 437 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 438 val NumRedirect = exuParameters.JmpCnt + exuParameters.AluCnt 439 val BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 440 val FtqRedirectAheadNum = exuParameters.AluCnt 441 val LoadPipelineWidth = coreParams.LoadPipelineWidth 442 val StorePipelineWidth = coreParams.StorePipelineWidth 443 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 444 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 445 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 446 val StoreBufferSize = coreParams.StoreBufferSize 447 val StoreBufferThreshold = coreParams.StoreBufferThreshold 448 val EnsbufferWidth = coreParams.EnsbufferWidth 449 val UncacheBufferSize = coreParams.UncacheBufferSize 450 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 451 val EnableFastForward = coreParams.EnableFastForward 452 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 453 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 454 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 455 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 456 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 457 val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 458 val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 459 val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 460 val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 461 val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 462 require(LoadPipelineWidth == StorePipelineWidth, "LoadPipelineWidth must be equal StorePipelineWidth!") 463 require(LoadPipelineWidth == exuParameters.LduCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 464 require(StorePipelineWidth == exuParameters.StuCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 465 val Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 466 val asidLen = coreParams.MMUAsidLen 467 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 468 val refillBothTlb = coreParams.refillBothTlb 469 val iwpuParam = coreParams.iwpuParameters 470 val dwpuParam = coreParams.dwpuParameters 471 val itlbParams = coreParams.itlbParameters 472 val ldtlbParams = coreParams.ldtlbParameters 473 val sttlbParams = coreParams.sttlbParameters 474 val pftlbParams = coreParams.pftlbParameters 475 val btlbParams = coreParams.btlbParameters 476 val l2tlbParams = coreParams.l2tlbParameters 477 val NumPerfCounters = coreParams.NumPerfCounters 478 479 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 480 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 481 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 482 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 483 484 val instBytes = if (HasCExtension) 2 else 4 485 val instOffsetBits = log2Ceil(instBytes) 486 487 val icacheParameters = coreParams.icacheParameters 488 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 489 490 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 491 // for constrained LR/SC loop 492 val LRSCCycles = 64 493 // for lr storm 494 val LRSCBackOff = 8 495 496 // cache hierarchy configurations 497 val l1BusDataWidth = 256 498 499 // load violation predict 500 val ResetTimeMax2Pow = 20 //1078576 501 val ResetTimeMin2Pow = 10 //1024 502 // wait table parameters 503 val WaitTableSize = 1024 504 val MemPredPCWidth = log2Up(WaitTableSize) 505 val LWTUse2BitCounter = true 506 // store set parameters 507 val SSITSize = WaitTableSize 508 val LFSTSize = 32 509 val SSIDWidth = log2Up(LFSTSize) 510 val LFSTWidth = 4 511 val StoreSetEnable = true // LWT will be disabled if SS is enabled 512 val LFSTEnable = false 513 val loadExuConfigs = coreParams.loadExuConfigs 514 val storeExuConfigs = coreParams.storeExuConfigs 515 516 val intExuConfigs = coreParams.intExuConfigs 517 518 val fpExuConfigs = coreParams.fpExuConfigs 519 520 val exuConfigs = coreParams.exuConfigs 521 522 val PCntIncrStep: Int = 6 523 val numPCntHc: Int = 25 524 val numPCntPtw: Int = 19 525 526 val numCSRPCntFrontend = 8 527 val numCSRPCntCtrl = 8 528 val numCSRPCntLsu = 8 529 val numCSRPCntHc = 5 530 val printEventCoding = true 531} 532