| /linux-6.14.4/drivers/soc/fsl/qe/ |
| D | ucc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * QE UCC API Set - UCC specific routines implementations.
33 if (ucc_num > UCC_MAX_NUM - 1) in ucc_set_qe_mux_mii_mng()
34 return -EINVAL; in ucc_set_qe_mux_mii_mng()
37 qe_clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG, in ucc_set_qe_mux_mii_mng()
50 * 'ucc_num' is the UCC number, from 0 - 7.
62 case 0: guemr = &qe_immr->ucc1.slow.guemr; in ucc_set_type()
64 case 1: guemr = &qe_immr->ucc2.slow.guemr; in ucc_set_type()
66 case 2: guemr = &qe_immr->ucc3.slow.guemr; in ucc_set_type()
68 case 3: guemr = &qe_immr->ucc4.slow.guemr; in ucc_set_type()
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| /linux-6.14.4/Documentation/devicetree/bindings/mmc/ |
| D | samsung,exynos-dw-mshc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Jaehoon Chung <[email protected]>
13 - Krzysztof Kozlowski <[email protected]>
18 - enum:
19 - axis,artpec8-dw-mshc
20 - samsung,exynos4210-dw-mshc
21 - samsung,exynos4412-dw-mshc
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| /linux-6.14.4/Documentation/devicetree/bindings/net/ |
| D | ti,dp83822.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Davis <[email protected]>
14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
16 data over standard, twisted-pair cables or to connect to an external,
17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
24 - $ref: ethernet-phy.yaml#
30 ti,link-loss-low:
33 DP83822 PHY in Fiber mode only.
[all …]
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| D | micrel.txt | 7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
9 Configure the LED mode with single value. The list of PHYs and the
21 See the respective PHY datasheet for the mode values.
23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
30 non-standard, inverted function of this configuration bit.
31 Specifically, a clock reference ("rmii-ref" below) is always needed to
32 actually select a mode.
[all …]
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| /linux-6.14.4/Documentation/timers/ |
| D | no_hz.rst | 2 NO_HZ: Reducing Scheduling-Clock Ticks
7 reduce the number of scheduling-clock interrupts, thereby improving energy
9 some types of computationally intensive high-performance computing (HPC)
10 applications and for real-time applications.
12 There are three main ways of managing scheduling-clock interrupts
13 (also known as "scheduling-clock ticks" or simply "ticks"):
15 1. Never omit scheduling-clock ticks (CONFIG_HZ_PERIODIC=y or
16 CONFIG_NO_HZ=n for older kernels). You normally will -not-
19 2. Omit scheduling-clock ticks on idle CPUs (CONFIG_NO_HZ_IDLE=y or
23 3. Omit scheduling-clock ticks on CPUs that are either idle or that
[all …]
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| /linux-6.14.4/drivers/gpu/drm/gma500/ |
| D | psb_intel_display.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
48 /* The single-channel range is 25-112Mhz, and dual-channel
49 * is 80-224Mhz. Prefer single channel as much as possible.
68 static void psb_intel_clock(int refclk, struct gma_clock_t *clock) in psb_intel_clock() argument
70 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); in psb_intel_clock()
71 clock->p = clock->p1 * clock->p2; in psb_intel_clock()
72 clock->vco = refclk * clock->m / (clock->n + 2); in psb_intel_clock()
73 clock->dot = clock->vco / clock->p; in psb_intel_clock()
78 * or -1 if the panel fitter is not present or not in use
[all …]
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| D | cdv_intel_display.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
57 /* The single-channel range is 25-112Mhz, and dual-channel
58 * is 80-224Mhz. Prefer single channel as much as possible.
118 ret__ = -ETIMEDOUT; \
197 * mode set.
209 * DPLL reference clock is on in the DPLL control register, but before
214 struct gma_clock_t *clock, bool is_lvds, u32 ddi_select) in cdv_dpll_set_clock_cdv() argument
217 int pipe = gma_crtc->pipe; in cdv_dpll_set_clock_cdv()
244 * refclka mean use clock from same PLL in cdv_dpll_set_clock_cdv()
[all …]
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| /linux-6.14.4/drivers/clk/zynqmp/ |
| D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Xilinx
9 #include <linux/clk-provider.h>
11 #include "clk-zynqmp.h"
14 * struct zynqmp_pll - PLL clock
15 * @hw: Handle between common and hardware-specific interfaces
16 * @clk_id: PLL clock ID
44 * zynqmp_pll_get_mode() - Get mode of PLL
45 * @hw: Handle between common and hardware-specific interfaces
47 * Return: Mode of PLL
[all …]
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| /linux-6.14.4/drivers/gpu/drm/amd/amdgpu/ |
| D | atombios_crtc.c | 2 * Copyright 2007-8 Advanced Micro Devices, Inc.
31 #include "atom-bits.h"
39 struct drm_display_mode *mode, in amdgpu_atombios_crtc_overscan_setup() argument
42 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_overscan_setup()
51 args.ucCRTC = amdgpu_crtc->crtc_id; in amdgpu_atombios_crtc_overscan_setup()
53 switch (amdgpu_crtc->rmx_type) { in amdgpu_atombios_crtc_overscan_setup()
55 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
56 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
57 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
58 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
[all …]
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| /linux-6.14.4/sound/pci/echoaudio/ |
| D | layla24_dsp.c | 3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA.
25 Translation from C++ and adaptation for use in ALSA-Driver
32 static int set_input_clock(struct echoaudio *chip, u16 clock);
34 static int set_digital_mode(struct echoaudio *chip, u8 mode);
44 return -ENODEV; in init_hw()
48 dev_err(chip->card->dev, in init_hw()
49 "init_hw - could not initialize DSP comm page\n"); in init_hw()
53 chip->device_id = device_id; in init_hw()
[all …]
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| D | mona_dsp.c | 3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
33 static int set_input_clock(struct echoaudio *chip, u16 clock);
35 static int set_digital_mode(struct echoaudio *chip, u8 mode);
45 return -ENODEV; in init_hw()
49 dev_err(chip->card->dev, in init_hw()
50 "init_hw - could not initialize DSP comm page\n"); in init_hw()
54 chip->device_id = device_id; in init_hw()
[all …]
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| D | gina24_dsp.c | 3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
33 static int set_input_clock(struct echoaudio *chip, u16 clock);
35 static int set_digital_mode(struct echoaudio *chip, u8 mode);
45 return -ENODEV; in init_hw()
49 dev_err(chip->card->dev, in init_hw()
50 "init_hw - could not initialize DSP comm page\n"); in init_hw()
54 chip->device_id = device_id; in init_hw()
[all …]
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| D | echoaudio_3g.c | 3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
41 return -EIO; in check_asic_status()
43 chip->comm_page->ext_box_status = cpu_to_le32(E3G_ASIC_NOT_LOADED); in check_asic_status()
44 chip->asic_loaded = false; in check_asic_status()
49 chip->dsp_code = NULL; in check_asic_status()
50 return -EIO; in check_asic_status()
53 box_status = le32_to_cpu(chip->comm_page->ext_box_status); in check_asic_status()
[all …]
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| /linux-6.14.4/arch/arm/boot/dts/nvidia/ |
| D | tegra124-apalis-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
7 #include <dt-bindings/clock/tegra124-car.h>
10 clock@60006000 {
11 emc-timings-1 {
12 nvidia,ram-code = <1>;
14 timing-12750000 {
15 clock-frequency = <12750000>;
16 nvidia,parent-clock-frequency = <408000000>;
18 clock-names = "emc-parent";
[all …]
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| D | tegra124-jetson-tk1-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra124-car.h>
6 clock@60006000 {
7 emc-timings-3 {
8 nvidia,ram-code = <3>;
10 timing-12750000 {
11 clock-frequency = <12750000>;
12 nvidia,parent-clock-frequency = <408000000>;
14 clock-names = "emc-parent";
17 timing-20400000 {
[all …]
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| D | tegra124-nyan-blaze-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra124-car.h>
6 clock@60006000 {
7 emc-timings-1 {
8 nvidia,ram-code = <1>;
10 timing-12750000 {
11 clock-frequency = <12750000>;
12 nvidia,parent-clock-frequency = <408000000>;
14 clock-names = "emc-parent";
17 timing-20400000 {
[all …]
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| D | tegra30-asus-tf700t.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
20 remote-endpoint = <&bridge_input>;
21 bus-width = <24>;
36 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
44 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
52 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
60 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
68 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
[all …]
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| D | tegra30-asus-tf300t.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
12 tf300t-init-hog {
13 gpio-hog;
15 output-low;
27 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
35 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
43 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/sound/ |
| D | fsl,ssi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <[email protected]>
13 Notes on fsl,playback-dma and fsl,capture-dma
14 On SOCs that have an SSI, specific DMA channels are hard-wired for playback
18 DMA controller to use, but the channels themselves are hard-wired. The
22 "fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
23 "fsl,ssi-dma-channel". The SOC-specific compatible string (e.g.
24 "fsl,mpc8610-dma-channel") can remain. If these nodes are left as
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/clock/ |
| D | silabs,si5351.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/silabs,si5351.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Silicon Labs Si5351A/B/C programmable I2C clock generators
10 The Silicon Labs Si5351A/B/C are programmable I2C clock generators with up to
11 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3
12 output clocks are accessible. The internal structure of the clock generators
16 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
19 - Alvin Šipraga <alsi@bang-olufsen.dk>
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/mfd/ |
| D | omap-usb-host.txt | 5 - compatible: should be "ti,usbhs-host"
6 - reg: should contain one register range i.e. start and length
7 - ti,hwmods: must contain "usb_host_hs"
11 - num-ports: number of USB ports. Usually this is automatically detected
15 - portN-mode: String specifying the port mode for port N, where N can be
16 from 1 to 3. If the port mode is not specified, that port is treated
18 "ehci-phy",
19 "ehci-tll",
20 "ehci-hsic",
21 "ohci-phy-6pin-datse0",
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| /linux-6.14.4/drivers/video/fbdev/ |
| D | valkyriefb.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 * Vmode-switching changes and vmode 15/17 modifications created 29 August
13 * Ported to 68k Macintosh by David Huggins-Daines <[email protected]>
20 * pmc-valkyrie.h: Console support for PowerMac "control" display adaptor.
23 * pmc-valkyrie.c: Console support for PowerMac "control" display adaptor.
28 * pmc-control.h: Console support for PowerMac "control" display adaptor.
31 * pmc-control.c: Console support for PowerMac "control" display adaptor.
39 /* Valkyrie registers are word-aligned on m68k */
65 struct vpreg mode; member
78 * Dot clock rate is
[all …]
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| /linux-6.14.4/drivers/hid/intel-thc-hid/intel-quicki2c/ |
| D | quicki2c-dev.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/hid-over-i2c.h>
43 * change to low power LTR mode.
62 * struct quicki2c_subip_acpi_parameter - QuickI2C ACPI DSD parameters
65 * @addressing_mode: I2C device slave address mode, 7bit or 10bit
77 * struct quicki2c_subip_acpi_config - QuickI2C ACPI DSD parameters
78 * @SMHX: Standard Mode (100 kbit/s) Serial Clock Line HIGH Period
79 * @SMLX: Standard Mode (100 kbit/s) Serial Clock Line LOW Period
80 * @SMTD: Standard Mode (100 kbit/s) Serial Data Line Transmit Hold Period
81 * @SMRD: Standard Mode (100 kbit/s) Serial Data Receive Hold Period
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| /linux-6.14.4/arch/arm/boot/dts/sigmastar/ |
| D | mstar-infinity3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include "mstar-infinity.dtsi"
10 opp-1008000000 {
11 opp-hz = /bits/ 64 <1008000000>;
12 opp-microvolt = <1000000>;
13 clock-latency-ns = <300000>;
17 opp-108000000 {
18 opp-hz = /bits/ 64 <1080000000>;
19 opp-microvolt = <1000000>;
20 clock-latency-ns = <300000>;
[all …]
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| /linux-6.14.4/Documentation/networking/ |
| D | generic-hdlc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
14 - Normal (routed) and Ethernet-bridged (Ethernet device emulation)
16 - ARP support (no InARP support in the kernel - there is an
17 experimental InARP user-space daemon available on:
20 2. raw HDLC - either IP (IPv4) interface or Ethernet device emulation
25 Generic HDLC is a protocol driver only - it needs a low-level driver
28 Ethernet device emulation (using HDLC or Frame-Relay PVC) is compatible
40 gcc -O2 -Wall -o sethdlc sethdlc.c
44 Use sethdlc to set physical interface, clock rate, HDLC mode used,
48 sethdlc hdlc0 clock int rate 128000
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