3    Copyright Echo Digital Audio Corporation (c) 1998 - 2004
20    Foundation, Inc., 59 Temple Place - Suite 330, Boston,
21    MA  02111-1307, USA.
25  Translation from C++ and adaptation for use in ALSA-Driver
32 static int set_input_clock(struct echoaudio *chip, u16 clock);
34 static int set_digital_mode(struct echoaudio *chip, u8 mode);
44 		return -ENODEV;  in init_hw()
48 		dev_err(chip->card->dev,  in init_hw()
49 			"init_hw - could not initialize DSP comm page\n");  in init_hw()
53 	chip->device_id = device_id;  in init_hw()
54 	chip->subdevice_id = subdevice_id;  in init_hw()
55 	chip->bad_board = true;  in init_hw()
56 	chip->has_midi = true;  in init_hw()
57 	chip->dsp_code_to_load = FW_LAYLA24_DSP;  in init_hw()
58 	chip->input_clock_types =  in init_hw()
61 	chip->digital_modes =  in init_hw()
69 	chip->bad_board = false;  in init_hw()
82 	chip->digital_mode = DIGITAL_MODE_SPDIF_RCA;  in set_mixer_defaults()
83 	chip->professional_spdif = false;  in set_mixer_defaults()
84 	chip->digital_in_automute = true;  in set_mixer_defaults()
94 	/* Map the DSP clock detect bits to the generic driver clock detect bits */  in detect_input_clocks()
95 	clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);  in detect_input_clocks()
119 	if (chip->asic_loaded)  in load_asic()
132 	chip->asic_code = FW_LAYLA24_2S_ASIC;  in load_asic()
149 	/* Set up the control register if the load succeeded -  in load_asic()
150 	   48 kHz, internal clock, S/PDIF RCA mode */  in load_asic()
162 	u32 control_reg, clock, base_rate;  in set_sample_rate()  local
165 		       chip->digital_mode == DIGITAL_MODE_ADAT))  in set_sample_rate()
166 		return -EINVAL;  in set_sample_rate()
168 	/* Only set the clock for internal mode. */  in set_sample_rate()
169 	if (chip->input_clock != ECHO_CLOCK_INTERNAL) {  in set_sample_rate()
170 		dev_warn(chip->card->dev,  in set_sample_rate()
171 			 "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");  in set_sample_rate()
173 		chip->comm_page->sample_rate = cpu_to_le32(rate);  in set_sample_rate()
174 		chip->sample_rate = rate;  in set_sample_rate()
179 	control_reg = le32_to_cpu(chip->comm_page->control_register);  in set_sample_rate()
182 	clock = 0;  in set_sample_rate()
186 		clock = GML_96KHZ;  in set_sample_rate()
189 		clock = GML_88KHZ;  in set_sample_rate()
192 		clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1;  in set_sample_rate()
195 		clock = GML_44KHZ;  in set_sample_rate()
196 		/* Professional mode */  in set_sample_rate()
198 			clock |= GML_SPDIF_SAMPLE_RATE0;  in set_sample_rate()
201 		clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 |  in set_sample_rate()
205 		clock = GML_22KHZ;  in set_sample_rate()
208 		clock = GML_16KHZ;  in set_sample_rate()
211 		clock = GML_11KHZ;  in set_sample_rate()
214 		clock = GML_8KHZ;  in set_sample_rate()
217 		/* If this is a non-standard rate, then the driver needs to  in set_sample_rate()
218 		use Layla24's special "continuous frequency" mode */  in set_sample_rate()
219 		clock = LAYLA24_CONTINUOUS_CLOCK;  in set_sample_rate()
231 			return -EIO;  in set_sample_rate()
233 		chip->comm_page->sample_rate =  in set_sample_rate()
234 			cpu_to_le32(LAYLA24_MAGIC_NUMBER / base_rate - 2);  in set_sample_rate()
240 	control_reg |= clock;  in set_sample_rate()
242 	chip->comm_page->sample_rate = cpu_to_le32(rate);	/* ignored by the DSP ? */  in set_sample_rate()
243 	chip->sample_rate = rate;  in set_sample_rate()
244 	dev_dbg(chip->card->dev,  in set_sample_rate()
245 		"set_sample_rate: %d clock %d\n", rate, control_reg);  in set_sample_rate()
252 static int set_input_clock(struct echoaudio *chip, u16 clock)  in set_input_clock()  argument
256 	/* Mask off the clock select bits */  in set_input_clock()
257 	control_reg = le32_to_cpu(chip->comm_page->control_register) &  in set_input_clock()
259 	clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);  in set_input_clock()
261 	/* Pick the new clock */  in set_input_clock()
262 	switch (clock) {  in set_input_clock()
264 		chip->input_clock = ECHO_CLOCK_INTERNAL;  in set_input_clock()
265 		return set_sample_rate(chip, chip->sample_rate);  in set_input_clock()
267 		if (chip->digital_mode == DIGITAL_MODE_ADAT)  in set_input_clock()
268 			return -EAGAIN;  in set_input_clock()
281 		if (chip->digital_mode != DIGITAL_MODE_ADAT)  in set_input_clock()
282 			return -EAGAIN;  in set_input_clock()
287 		dev_err(chip->card->dev,  in set_input_clock()
288 			"Input clock 0x%x not supported for Layla24\n", clock);  in set_input_clock()
289 		return -EINVAL;  in set_input_clock()
292 	chip->input_clock = clock;  in set_input_clock()
298 /* Depending on what digital mode you want, Layla24 needs different ASICs
299 loaded.  This function checks the ASIC needed for the new mode and sees
306 	if (asic != chip->asic_code) {  in switch_asic()
307 		monitors = kmemdup(chip->comm_page->monitors,  in switch_asic()
310 			return -ENOMEM;  in switch_asic()
312 		memset(chip->comm_page->monitors, ECHOGAIN_MUTED,  in switch_asic()
318 			memcpy(chip->comm_page->monitors, monitors,  in switch_asic()
321 			return -EIO;  in switch_asic()
323 		chip->asic_code = asic;  in switch_asic()
324 		memcpy(chip->comm_page->monitors, monitors, MONITOR_ARRAY_SIZE);  in switch_asic()
333 static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)  in dsp_set_digital_mode()  argument
339 	/* Set clock to "internal" if it's not compatible with the new mode */  in dsp_set_digital_mode()
341 	switch (mode) {  in dsp_set_digital_mode()
344 		if (chip->input_clock == ECHO_CLOCK_ADAT)  in dsp_set_digital_mode()
349 		if (chip->input_clock == ECHO_CLOCK_SPDIF)  in dsp_set_digital_mode()
354 		dev_err(chip->card->dev,  in dsp_set_digital_mode()
355 			"Digital mode not supported: %d\n", mode);  in dsp_set_digital_mode()
356 		return -EINVAL;  in dsp_set_digital_mode()
360 		chip->sample_rate = 48000;  in dsp_set_digital_mode()
361 		spin_lock_irq(&chip->lock);  in dsp_set_digital_mode()
363 		spin_unlock_irq(&chip->lock);  in dsp_set_digital_mode()
368 		return -EIO;  in dsp_set_digital_mode()
370 	spin_lock_irq(&chip->lock);  in dsp_set_digital_mode()
373 	control_reg = le32_to_cpu(chip->comm_page->control_register);  in dsp_set_digital_mode()
376 	switch (mode) {  in dsp_set_digital_mode()
390 	spin_unlock_irq(&chip->lock);  in dsp_set_digital_mode()
393 	chip->digital_mode = mode;  in dsp_set_digital_mode()
395 	dev_dbg(chip->card->dev, "set_digital_mode to %d\n", mode);  in dsp_set_digital_mode()