Lines Matching +full:clock +full:- +full:mode
3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
41 return -EIO; in check_asic_status()
43 chip->comm_page->ext_box_status = cpu_to_le32(E3G_ASIC_NOT_LOADED); in check_asic_status()
44 chip->asic_loaded = false; in check_asic_status()
49 chip->dsp_code = NULL; in check_asic_status()
50 return -EIO; in check_asic_status()
53 box_status = le32_to_cpu(chip->comm_page->ext_box_status); in check_asic_status()
54 dev_dbg(chip->card->dev, "box_status=%x\n", box_status); in check_asic_status()
56 return -ENODEV; in check_asic_status()
58 chip->asic_loaded = true; in check_asic_status()
66 return le32_to_cpu(chip->comm_page->e3g_frq_register); in get_frq_reg()
79 return -EIO; in write_control_reg()
81 dev_dbg(chip->card->dev, in write_control_reg()
87 if (ctl_reg != chip->comm_page->control_register || in write_control_reg()
88 frq_reg != chip->comm_page->e3g_frq_register || force) { in write_control_reg()
89 chip->comm_page->e3g_frq_register = frq_reg; in write_control_reg()
90 chip->comm_page->control_register = ctl_reg; in write_control_reg()
95 dev_dbg(chip->card->dev, "WriteControlReg: not written, no change\n"); in write_control_reg()
101 /* Set the digital mode - currently for Gina24, Layla24, Mona, 3G */
102 static int set_digital_mode(struct echoaudio *chip, u8 mode) in set_digital_mode() argument
107 /* All audio channels must be closed before changing the digital mode */ in set_digital_mode()
108 if (snd_BUG_ON(chip->pipe_alloc_mask)) in set_digital_mode()
109 return -EAGAIN; in set_digital_mode()
111 if (snd_BUG_ON(!(chip->digital_modes & (1 << mode)))) in set_digital_mode()
112 return -EINVAL; in set_digital_mode()
114 previous_mode = chip->digital_mode; in set_digital_mode()
115 err = dsp_set_digital_mode(chip, mode); in set_digital_mode()
117 /* If we successfully changed the digital mode from or to ADAT, in set_digital_mode()
120 if (err >= 0 && previous_mode != mode && in set_digital_mode()
121 (previous_mode == DIGITAL_MODE_ADAT || mode == DIGITAL_MODE_ADAT)) { in set_digital_mode()
122 spin_lock_irq(&chip->lock); in set_digital_mode()
126 chip->monitor_gain[o][i]); in set_digital_mode()
130 set_input_gain(chip, i, chip->input_gain[i]); in set_digital_mode()
135 set_output_gain(chip, o, chip->output_gain[o]); in set_digital_mode()
137 spin_unlock_irq(&chip->lock); in set_digital_mode()
154 if (chip->professional_spdif) in set_spdif_bits()
162 if (chip->professional_spdif) in set_spdif_bits()
165 if (chip->non_audio_spdif) in set_spdif_bits()
181 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_professional_spdif()
182 chip->professional_spdif = prof; in set_professional_spdif()
183 control_reg = set_spdif_bits(chip, control_reg, chip->sample_rate); in set_professional_spdif()
191 disconnects clock inputs. You should use this information to determine which
197 /* Map the DSP clock detect bits to the generic driver clock in detect_input_clocks()
199 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks); in detect_input_clocks()
206 switch(chip->digital_mode) { in detect_input_clocks()
227 if (chip->asic_loaded) in load_asic()
237 chip->asic_code = FW_3G_ASIC; in load_asic()
244 /* Set up the control register if the load succeeded - in load_asic()
245 * 48 kHz, internal clock, S/PDIF RCA mode */ in load_asic()
260 u32 control_reg, clock, base_rate, frq_reg; in set_sample_rate() local
262 /* Only set the clock for internal mode. */ in set_sample_rate()
263 if (chip->input_clock != ECHO_CLOCK_INTERNAL) { in set_sample_rate()
264 dev_warn(chip->card->dev, in set_sample_rate()
265 "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n"); in set_sample_rate()
267 chip->comm_page->sample_rate = cpu_to_le32(rate); in set_sample_rate()
268 chip->sample_rate = rate; in set_sample_rate()
269 set_input_clock(chip, chip->input_clock); in set_sample_rate()
274 chip->digital_mode == DIGITAL_MODE_ADAT)) in set_sample_rate()
275 return -EINVAL; in set_sample_rate()
277 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_sample_rate()
282 clock = E3G_96KHZ; in set_sample_rate()
285 clock = E3G_88KHZ; in set_sample_rate()
288 clock = E3G_48KHZ; in set_sample_rate()
291 clock = E3G_44KHZ; in set_sample_rate()
294 clock = E3G_32KHZ; in set_sample_rate()
297 clock = E3G_CONTINUOUS_CLOCK; in set_sample_rate()
299 clock |= E3G_DOUBLE_SPEED_MODE; in set_sample_rate()
303 control_reg |= clock; in set_sample_rate()
312 frq_reg = E3G_MAGIC_NUMBER / base_rate - 2; in set_sample_rate()
316 chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP */ in set_sample_rate()
317 chip->sample_rate = rate; in set_sample_rate()
318 dev_dbg(chip->card->dev, in set_sample_rate()
319 "SetSampleRate: %d clock %x\n", rate, control_reg); in set_sample_rate()
321 /* Tell the DSP about it - DSP reads both control reg & freq reg */ in set_sample_rate()
327 /* Set the sample clock source to internal, S/PDIF, ADAT */
328 static int set_input_clock(struct echoaudio *chip, u16 clock) in set_input_clock() argument
333 /* Mask off the clock select bits */ in set_input_clock()
334 control_reg = le32_to_cpu(chip->comm_page->control_register) & in set_input_clock()
336 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks); in set_input_clock()
338 switch (clock) { in set_input_clock()
340 chip->input_clock = ECHO_CLOCK_INTERNAL; in set_input_clock()
341 return set_sample_rate(chip, chip->sample_rate); in set_input_clock()
343 if (chip->digital_mode == DIGITAL_MODE_ADAT) in set_input_clock()
344 return -EAGAIN; in set_input_clock()
352 if (chip->digital_mode != DIGITAL_MODE_ADAT) in set_input_clock()
353 return -EAGAIN; in set_input_clock()
365 dev_err(chip->card->dev, in set_input_clock()
366 "Input clock 0x%x not supported for Echo3G\n", clock); in set_input_clock()
367 return -EINVAL; in set_input_clock()
370 chip->input_clock = clock; in set_input_clock()
376 static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode) in dsp_set_digital_mode() argument
381 /* Set clock to "internal" if it's not compatible with the new mode */ in dsp_set_digital_mode()
383 switch (mode) { in dsp_set_digital_mode()
386 if (chip->input_clock == ECHO_CLOCK_ADAT) in dsp_set_digital_mode()
390 if (chip->input_clock == ECHO_CLOCK_SPDIF) in dsp_set_digital_mode()
394 dev_err(chip->card->dev, in dsp_set_digital_mode()
395 "Digital mode not supported: %d\n", mode); in dsp_set_digital_mode()
396 return -EINVAL; in dsp_set_digital_mode()
399 spin_lock_irq(&chip->lock); in dsp_set_digital_mode()
402 chip->sample_rate = 48000; in dsp_set_digital_mode()
406 /* Clear the current digital mode */ in dsp_set_digital_mode()
407 control_reg = le32_to_cpu(chip->comm_page->control_register); in dsp_set_digital_mode()
411 switch (mode) { in dsp_set_digital_mode()
425 spin_unlock_irq(&chip->lock); in dsp_set_digital_mode()
428 chip->digital_mode = mode; in dsp_set_digital_mode()
430 dev_dbg(chip->card->dev, "set_digital_mode(%d)\n", chip->digital_mode); in dsp_set_digital_mode()