Lines Matching +full:clock +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
57 /* The single-channel range is 25-112Mhz, and dual-channel
58 * is 80-224Mhz. Prefer single channel as much as possible.
118 ret__ = -ETIMEDOUT; \
197 * mode set.
209 * DPLL reference clock is on in the DPLL control register, but before
214 struct gma_clock_t *clock, bool is_lvds, u32 ddi_select) in cdv_dpll_set_clock_cdv() argument
217 int pipe = gma_crtc->pipe; in cdv_dpll_set_clock_cdv()
244 * refclka mean use clock from same PLL in cdv_dpll_set_clock_cdv()
246 * if DPLLA sets 01 and DPLLB sets 01, they use clock from their pll in cdv_dpll_set_clock_cdv()
272 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
288 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
290 if (clock->vco < 2250000) { in cdv_dpll_set_clock_cdv()
293 } else if (clock->vco < 2750000) { in cdv_dpll_set_clock_cdv()
296 } else if (clock->vco < 3300000) { in cdv_dpll_set_clock_cdv()
312 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER); in cdv_dpll_set_clock_cdv()
313 switch (clock->p2) { in cdv_dpll_set_clock_cdv()
327 DRM_ERROR("Bad P2 clock: %d\n", clock->p2); in cdv_dpll_set_clock_cdv()
328 return -EINVAL; in cdv_dpll_set_clock_cdv()
370 * Now only single-channel LVDS is supported on CDV. If it is in cdv_intel_limit()
371 * incorrect, please add the dual-channel LVDS. in cdv_intel_limit()
393 static void cdv_intel_clock(int refclk, struct gma_clock_t *clock) in cdv_intel_clock() argument
395 clock->m = clock->m2 + 2; in cdv_intel_clock()
396 clock->p = clock->p1 * clock->p2; in cdv_intel_clock()
397 clock->vco = (refclk * clock->m) / clock->n; in cdv_intel_clock()
398 clock->dot = clock->vco / clock->p; in cdv_intel_clock()
407 struct gma_clock_t clock; in cdv_intel_find_dp_pll() local
409 memset(&clock, 0, sizeof(clock)); in cdv_intel_find_dp_pll()
414 clock.p1 = 2; in cdv_intel_find_dp_pll()
415 clock.p2 = 10; in cdv_intel_find_dp_pll()
416 clock.n = 1; in cdv_intel_find_dp_pll()
417 clock.m1 = 0; in cdv_intel_find_dp_pll()
418 clock.m2 = 118; in cdv_intel_find_dp_pll()
420 clock.p1 = 1; in cdv_intel_find_dp_pll()
421 clock.p2 = 10; in cdv_intel_find_dp_pll()
422 clock.n = 1; in cdv_intel_find_dp_pll()
423 clock.m1 = 0; in cdv_intel_find_dp_pll()
424 clock.m2 = 98; in cdv_intel_find_dp_pll()
430 clock.p1 = 2; in cdv_intel_find_dp_pll()
431 clock.p2 = 10; in cdv_intel_find_dp_pll()
432 clock.n = 5; in cdv_intel_find_dp_pll()
433 clock.m1 = 0; in cdv_intel_find_dp_pll()
434 clock.m2 = 160; in cdv_intel_find_dp_pll()
436 clock.p1 = 1; in cdv_intel_find_dp_pll()
437 clock.p2 = 10; in cdv_intel_find_dp_pll()
438 clock.n = 5; in cdv_intel_find_dp_pll()
439 clock.m1 = 0; in cdv_intel_find_dp_pll()
440 clock.m2 = 133; in cdv_intel_find_dp_pll()
448 gma_crtc->clock_funcs->clock(refclk, &clock); in cdv_intel_find_dp_pll()
449 memcpy(best_clock, &clock, sizeof(struct gma_clock_t)); in cdv_intel_find_dp_pll()
462 crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in cdv_intel_pipe_enabled()
465 if (crtc->primary->fb == NULL || !gma_crtc->active) in cdv_intel_pipe_enabled()
474 /* Disable self-refresh before adjust WM */ in cdv_disable_sr()
483 REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/); in cdv_disable_sr()
519 if (gma_crtc->pipe == 1 && in cdv_update_wm()
534 /* enable self-refresh for single pipe active */ in cdv_update_wm()
551 dev_priv->ops->disable_sr(dev); in cdv_update_wm()
557 * or -1 if the panel fitter is not present or not in use
567 return -1; in cdv_intel_panel_fitter_pipe()
572 struct drm_display_mode *mode, in cdv_intel_crtc_mode_set() argument
577 struct drm_device *dev = crtc->dev; in cdv_intel_crtc_mode_set()
580 int pipe = gma_crtc->pipe; in cdv_intel_crtc_mode_set()
581 const struct psb_offset *map = &dev_priv->regmap[pipe]; in cdv_intel_crtc_mode_set()
583 struct gma_clock_t clock; in cdv_intel_crtc_mode_set() local
599 if (!connector->encoder in cdv_intel_crtc_mode_set()
600 || connector->encoder->crtc != crtc) in cdv_intel_crtc_mode_set()
603 ddi_select = gma_encoder->ddi_select; in cdv_intel_crtc_mode_set()
604 switch (gma_encoder->type) { in cdv_intel_crtc_mode_set()
627 if (dev_priv->dplla_96mhz) in cdv_intel_crtc_mode_set()
628 /* low-end sku, 96/100 mhz */ in cdv_intel_crtc_mode_set()
631 /* high-end sku, 27/100 mhz */ in cdv_intel_crtc_mode_set()
635 * Based on the spec the low-end SKU has only CRT/LVDS. So it is in cdv_intel_crtc_mode_set()
637 * On the high-end SKU, it will use the 27/100M reference clk in cdv_intel_crtc_mode_set()
638 * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise in cdv_intel_crtc_mode_set()
648 if (is_lvds && dev_priv->lvds_use_ssc) { in cdv_intel_crtc_mode_set()
649 refclk = dev_priv->lvds_ssc_freq * 1000; in cdv_intel_crtc_mode_set()
650 DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq); in cdv_intel_crtc_mode_set()
655 limit = gma_crtc->clock_funcs->limit(crtc, refclk); in cdv_intel_crtc_mode_set()
657 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, in cdv_intel_crtc_mode_set()
658 &clock); in cdv_intel_crtc_mode_set()
660 DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d", in cdv_intel_crtc_mode_set()
661 adjusted_mode->clock, clock.dot); in cdv_intel_crtc_mode_set()
668 cdv_intel_dp_set_m_n(crtc, mode, adjusted_mode); in cdv_intel_crtc_mode_set()
684 pipeconf = REG_READ(map->conf); in cdv_intel_crtc_mode_set()
688 switch (dev_priv->edp.bpp) { in cdv_intel_crtc_mode_set()
703 /* the BPC will be 6 if it is 18-bit LVDS panel */ in cdv_intel_crtc_mode_set()
722 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
723 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
725 cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds, ddi_select); in cdv_intel_crtc_mode_set()
740 /* Set the B0-B3 data pairs corresponding to in cdv_intel_crtc_mode_set()
742 * set the DPLLs for dual-channel mode or not. in cdv_intel_crtc_mode_set()
744 if (clock.p2 == 7) in cdv_intel_crtc_mode_set()
749 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) in cdv_intel_crtc_mode_set()
764 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); in cdv_intel_crtc_mode_set()
765 drm_mode_debug_printmodeline(mode); in cdv_intel_crtc_mode_set()
767 REG_WRITE(map->dpll, in cdv_intel_crtc_mode_set()
768 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); in cdv_intel_crtc_mode_set()
769 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
773 if (!(REG_READ(map->dpll) & DPLL_LOCK)) { in cdv_intel_crtc_mode_set()
774 dev_err(dev->dev, "Failed to get DPLL lock\n"); in cdv_intel_crtc_mode_set()
775 return -EBUSY; in cdv_intel_crtc_mode_set()
779 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; in cdv_intel_crtc_mode_set()
780 …REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_U… in cdv_intel_crtc_mode_set()
783 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | in cdv_intel_crtc_mode_set()
784 ((adjusted_mode->crtc_htotal - 1) << 16)); in cdv_intel_crtc_mode_set()
785 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | in cdv_intel_crtc_mode_set()
786 ((adjusted_mode->crtc_hblank_end - 1) << 16)); in cdv_intel_crtc_mode_set()
787 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | in cdv_intel_crtc_mode_set()
788 ((adjusted_mode->crtc_hsync_end - 1) << 16)); in cdv_intel_crtc_mode_set()
789 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | in cdv_intel_crtc_mode_set()
790 ((adjusted_mode->crtc_vtotal - 1) << 16)); in cdv_intel_crtc_mode_set()
791 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | in cdv_intel_crtc_mode_set()
792 ((adjusted_mode->crtc_vblank_end - 1) << 16)); in cdv_intel_crtc_mode_set()
793 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | in cdv_intel_crtc_mode_set()
794 ((adjusted_mode->crtc_vsync_end - 1) << 16)); in cdv_intel_crtc_mode_set()
798 REG_WRITE(map->size, in cdv_intel_crtc_mode_set()
799 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); in cdv_intel_crtc_mode_set()
800 REG_WRITE(map->pos, 0); in cdv_intel_crtc_mode_set()
801 REG_WRITE(map->src, in cdv_intel_crtc_mode_set()
802 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); in cdv_intel_crtc_mode_set()
803 REG_WRITE(map->conf, pipeconf); in cdv_intel_crtc_mode_set()
804 REG_READ(map->conf); in cdv_intel_crtc_mode_set()
808 REG_WRITE(map->cntr, dspcntr); in cdv_intel_crtc_mode_set()
813 crtc->helper_private; in cdv_intel_crtc_mode_set()
814 crtc_funcs->mode_set_base(crtc, x, y, old_fb); in cdv_intel_crtc_mode_set()
822 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
826 static void i8xx_clock(int refclk, struct gma_clock_t *clock) in i8xx_clock() argument
828 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); in i8xx_clock()
829 clock->p = clock->p1 * clock->p2; in i8xx_clock()
830 clock->vco = refclk * clock->m / (clock->n + 2); in i8xx_clock()
831 clock->dot = clock->vco / clock->p; in i8xx_clock()
834 /* Returns the clock of the currently programmed mode of the given pipe. */
840 int pipe = gma_crtc->pipe; in cdv_intel_crtc_clock_get()
841 const struct psb_offset *map = &dev_priv->regmap[pipe]; in cdv_intel_crtc_clock_get()
844 struct gma_clock_t clock; in cdv_intel_crtc_clock_get() local
846 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; in cdv_intel_crtc_clock_get()
849 dpll = REG_READ(map->dpll); in cdv_intel_crtc_clock_get()
851 fp = REG_READ(map->fp0); in cdv_intel_crtc_clock_get()
853 fp = REG_READ(map->fp1); in cdv_intel_crtc_clock_get()
857 dpll = p->dpll; in cdv_intel_crtc_clock_get()
859 fp = p->fp0; in cdv_intel_crtc_clock_get()
861 fp = p->fp1; in cdv_intel_crtc_clock_get()
864 (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN); in cdv_intel_crtc_clock_get()
867 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; in cdv_intel_crtc_clock_get()
868 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; in cdv_intel_crtc_clock_get()
869 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; in cdv_intel_crtc_clock_get()
872 clock.p1 = in cdv_intel_crtc_clock_get()
876 if (clock.p1 == 0) { in cdv_intel_crtc_clock_get()
877 clock.p1 = 4; in cdv_intel_crtc_clock_get()
878 dev_err(dev->dev, "PLL %d\n", dpll); in cdv_intel_crtc_clock_get()
880 clock.p2 = 14; in cdv_intel_crtc_clock_get()
885 i8xx_clock(66000, &clock); in cdv_intel_crtc_clock_get()
887 i8xx_clock(48000, &clock); in cdv_intel_crtc_clock_get()
890 clock.p1 = 2; in cdv_intel_crtc_clock_get()
892 clock.p1 = in cdv_intel_crtc_clock_get()
898 clock.p2 = 4; in cdv_intel_crtc_clock_get()
900 clock.p2 = 2; in cdv_intel_crtc_clock_get()
902 i8xx_clock(48000, &clock); in cdv_intel_crtc_clock_get()
910 return clock.dot; in cdv_intel_crtc_clock_get()
913 /** Returns the currently programmed mode of the given pipe. */
918 int pipe = gma_crtc->pipe; in cdv_intel_crtc_mode_get()
920 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; in cdv_intel_crtc_mode_get()
921 const struct psb_offset *map = &dev_priv->regmap[pipe]; in cdv_intel_crtc_mode_get()
922 struct drm_display_mode *mode; in cdv_intel_crtc_mode_get() local
929 htot = REG_READ(map->htotal); in cdv_intel_crtc_mode_get()
930 hsync = REG_READ(map->hsync); in cdv_intel_crtc_mode_get()
931 vtot = REG_READ(map->vtotal); in cdv_intel_crtc_mode_get()
932 vsync = REG_READ(map->vsync); in cdv_intel_crtc_mode_get()
935 htot = p->htotal; in cdv_intel_crtc_mode_get()
936 hsync = p->hsync; in cdv_intel_crtc_mode_get()
937 vtot = p->vtotal; in cdv_intel_crtc_mode_get()
938 vsync = p->vsync; in cdv_intel_crtc_mode_get()
941 mode = kzalloc(sizeof(*mode), GFP_KERNEL); in cdv_intel_crtc_mode_get()
942 if (!mode) in cdv_intel_crtc_mode_get()
945 mode->clock = cdv_intel_crtc_clock_get(dev, crtc); in cdv_intel_crtc_mode_get()
946 mode->hdisplay = (htot & 0xffff) + 1; in cdv_intel_crtc_mode_get()
947 mode->htotal = ((htot & 0xffff0000) >> 16) + 1; in cdv_intel_crtc_mode_get()
948 mode->hsync_start = (hsync & 0xffff) + 1; in cdv_intel_crtc_mode_get()
949 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; in cdv_intel_crtc_mode_get()
950 mode->vdisplay = (vtot & 0xffff) + 1; in cdv_intel_crtc_mode_get()
951 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; in cdv_intel_crtc_mode_get()
952 mode->vsync_start = (vsync & 0xffff) + 1; in cdv_intel_crtc_mode_get()
953 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; in cdv_intel_crtc_mode_get()
955 drm_mode_set_name(mode); in cdv_intel_crtc_mode_get()
956 drm_mode_set_crtcinfo(mode, 0); in cdv_intel_crtc_mode_get()
958 return mode; in cdv_intel_crtc_mode_get()
971 .clock = cdv_intel_clock,