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/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r536225/include/llvm/Target/
DTarget.td1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
24 // A string representing subtarget features that turn on this HW mode.
25 // For example, "+feat1,-feat2" will indicate that the mode is active
32 // A list of predicates that turn on this HW mode.
36 // A special mode recognized by tablegen. This mode is considered active
37 // when no other mode is active. For targets that do not use specific hw
38 // modes, this is the only mode.
51 // dependent on a HW mode. This class inherits from ValueType itself,
62 // dependent on a HW mode. This class inherits from PtrValueType itself,
79 // The register size/alignment information, parameterized by a HW mode.
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/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r522817/include/llvm/Target/
DTarget.td1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
24 // A string representing subtarget features that turn on this HW mode.
25 // For example, "+feat1,-feat2" will indicate that the mode is active
32 // A list of predicates that turn on this HW mode.
36 // A special mode recognized by tablegen. This mode is considered active
37 // when no other mode is active. For targets that do not use specific hw
38 // modes, this is the only mode.
51 // dependent on a HW mode. This class inherits from ValueType itself,
62 // dependent on a HW mode. This class inherits from PtrValueType itself,
79 // The register size/alignment information, parameterized by a HW mode.
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/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567/include/llvm/Target/
DTarget.td1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
24 // A string representing subtarget features that turn on this HW mode.
25 // For example, "+feat1,-feat2" will indicate that the mode is active
32 // A list of predicates that turn on this HW mode.
36 // A special mode recognized by tablegen. This mode is considered active
37 // when no other mode is active. For targets that do not use specific hw
38 // modes, this is the only mode.
51 // dependent on a HW mode. This class inherits from ValueType itself,
62 // dependent on a HW mode. This class inherits from PtrValueType itself,
79 // The register size/alignment information, parameterized by a HW mode.
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/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567b/include/llvm/Target/
DTarget.td1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
24 // A string representing subtarget features that turn on this HW mode.
25 // For example, "+feat1,-feat2" will indicate that the mode is active
32 // A list of predicates that turn on this HW mode.
36 // A special mode recognized by tablegen. This mode is considered active
37 // when no other mode is active. For targets that do not use specific hw
38 // modes, this is the only mode.
51 // dependent on a HW mode. This class inherits from ValueType itself,
62 // dependent on a HW mode. This class inherits from PtrValueType itself,
79 // The register size/alignment information, parameterized by a HW mode.
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/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/Target/
H A DTarget.td1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
22 // A string representing subtarget features that turn on this HW mode.
23 // For example, "+feat1,-feat2" will indicate that the mode is active
31 // A special mode recognized by tablegen. This mode is considered active
32 // when no other mode is active. For targets that do not use specific hw
33 // modes, this is the only mode.
46 // dependent on a HW mode. This class inherits from ValueType itself,
64 // The register size/alignment information, parameterized by a HW mode.
161 // is invalid for this mode/flavour.
224 // The register size/alignment information, parameterized by a HW mode.
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/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567/lib/cmake/llvm/
DHandleLLVMOptions.cmake90 "Define the maximum number of concurrent tablegen jobs (Ninja only).")
107 # Job pool for tablegen is set on the add_custom_command
136 # Cautiously enable the extensive hardening mode in libc++.
588 # Allow users to request PDBs in release mode. CMake offeres the
595 # /DEBUG disables linker GC and ICF, but we want those in Release mode.
655 # Enable standards conformance mode.
749 …-wd4577 # Suppress 'noexcept used with no exception handling mode specified; termination on except…
937 # Use -O1 even in debug mode, otherwise sanitizers slowdown is too large.
1164 # under clang in dynamic linking mode.
1370 check_c_compiler_flag("-fdebug-prefix-map=foo=bar" SUPPORTS_FDEBUG_PREFIX_MAP)
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/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r536225/lib/cmake/llvm/
DHandleLLVMOptions.cmake92 "Define the maximum number of concurrent tablegen jobs (Ninja only).")
109 # Job pool for tablegen is set on the add_custom_command
138 # Cautiously enable the extensive hardening mode in libc++.
590 # Allow users to request PDBs in release mode. CMake offeres the
597 # /DEBUG disables linker GC and ICF, but we want those in Release mode.
657 # Enable standards conformance mode.
751 …-wd4577 # Suppress 'noexcept used with no exception handling mode specified; termination on except…
939 # Use -O1 even in debug mode, otherwise sanitizers slowdown is too large.
1166 # under clang in dynamic linking mode.
1379 check_c_compiler_flag("-fdebug-prefix-map=foo=bar" SUPPORTS_FDEBUG_PREFIX_MAP)
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/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567b/lib/cmake/llvm/
DHandleLLVMOptions.cmake90 "Define the maximum number of concurrent tablegen jobs (Ninja only).")
107 # Job pool for tablegen is set on the add_custom_command
136 # Cautiously enable the extensive hardening mode in libc++.
588 # Allow users to request PDBs in release mode. CMake offeres the
595 # /DEBUG disables linker GC and ICF, but we want those in Release mode.
655 # Enable standards conformance mode.
749 …-wd4577 # Suppress 'noexcept used with no exception handling mode specified; termination on except…
937 # Use -O1 even in debug mode, otherwise sanitizers slowdown is too large.
1164 # under clang in dynamic linking mode.
1370 check_c_compiler_flag("-fdebug-prefix-map=foo=bar" SUPPORTS_FDEBUG_PREFIX_MAP)
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/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
H A DTarget.td1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
24 // A string representing subtarget features that turn on this HW mode.
25 // For example, "+feat1,-feat2" will indicate that the mode is active
33 // A special mode recognized by tablegen. This mode is considered active
34 // when no other mode is active. For targets that do not use specific hw
35 // modes, this is the only mode.
48 // dependent on a HW mode. This class inherits from ValueType itself,
66 // The register size/alignment information, parameterized by a HW mode.
163 // is invalid for this mode/flavour.
214 // The register size/alignment information, parameterized by a HW mode.
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/aosp_15_r20/external/llvm/lib/Target/X86/
H A DX86RegisterInfo.td1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
238 // Floating point stack registers. These don't map one-to-one to the FP
319 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
324 // 64-bit mode. The main complication is that they cannot be encoded in an
399 // mode to prevent encoding using the 0x90 NOP encoding. xchg %eax, %eax needs
H A DX86InstrFormats.td1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
124 // Class specifying the opcode map.
145 // Operand size for encodings that change based on mode.
150 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
151 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
153 // Address size for encodings that change based on mode.
249 // based on operand size of the mode?
252 // based on address size of the mode?
257 Map OpMap = OB; // Which opcode map does this inst have?
918 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
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/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86RegisterInfo.td1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
278 // Floating point stack registers. These don't map one-to-one to the FP
380 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
385 // 64-bit mode. The main complication is that they cannot be encoded in an
513 // register in 32-bit mode. The second register is always the next in
H A DX86InstrFormats.td1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
144 // Class specifying the opcode map.
166 // Operand size for encodings that change based on mode.
171 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
172 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
174 // Address size for encodings that change based on mode.
284 // based on operand size of the mode?
287 // based on address size of the mode?
292 Map OpMap = OB; // Which opcode map does this inst have?
968 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
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/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/
H A DX86RegisterInfo.td1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
283 // Floating point stack registers. These don't map one-to-one to the FP
384 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
389 // 64-bit mode. The main complication is that they cannot be encoded in an
523 // register in 32-bit mode. The second register is always the next in
H A DX86InstrFormats.td1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
152 // Class specifying the opcode map.
176 // Operand size for encodings that change based on mode.
181 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
182 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
184 // Address size for encodings that change based on mode.
310 // based on operand size of the mode?
313 // based on address size of the mode?
318 Map OpMap = OB; // Which opcode map does this inst have?
999 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
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/aosp_15_r20/external/clang/docs/
H A DInternalsManual.rst110 you to map almost any diagnostic to the output level that you want. The only
430 mentioned, the diagnostic machinery goes through some filtering to map a
444 mode. Instead of formatting and printing out the diagnostics, this
448 documentation for the ``-verify`` mode can be found in the Clang API
522 To map from this representation to a character-based representation, the "last"
599 not reading in "raw" mode) this contains a pointer to the unique hash value
731 * The lexer can operate in "raw" mode. This mode has several features that
734 This mode is used for lexing within an "``#if 0``" block, for example.
736 support the ``-C`` preprocessor mode, which passes comments through, and is
738 * The lexer can be in ``ParsingFilename`` mode, which happens when
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/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/M68k/
H A DM68kInstrArithmetic.td1 //===-- M68kInstrArithmetic.td - Integer Arith Instrs ------*- tablegen -*-===//
153 // the MODE for data register direct mode.
325 /// M - address mode switch
414 // the MODE for data register direct mode.
800 /// MxAdd and MxSub instructions that produce CCR and then pattern-map add and addc
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/
H A DARMInstrInfo.td1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
317 // For example, 'VECTOR_REG_CAST' between v8i16 and v16i8 will map the LSB of
319 // whereas 'bitconvert' will map it to the high byte in big-endian mode,
550 // Operands that are part of a memory addressing mode.
561 // Branches targeting ARM-mode must be divisible by 4 if they're a raw
567 // Branches targeting Thumb-mode must be divisible by 2 if they're a raw
587 // Target for BLX *from* ARM mode.
2143 /// mode). Used mostly in ARM and Thumb-1 modes.
2249 bits<5> mode;
2255 let Inst{17} = M; // Enabled if mode is set;
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/aosp_15_r20/external/llvm/lib/Target/ARM/
H A DARMInstrInfo.td1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
291 AssemblerPredicate<"!ModeThumb", "arm-mode">;
410 // Operands that are part of a memory addressing mode.
421 // Branches targeting ARM-mode must be divisible by 4 if they're a raw
427 // Branches targeting Thumb-mode must be divisible by 2 if they're a raw
447 // Target for BLX *from* ARM mode.
1866 /// mode). Used mostly in ARM and Thumb-1 modes.
1965 bits<5> mode;
1971 let Inst{17} = M; // Enabled if mode is set;
1975 let Inst{4-0} = mode;
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H A DARMInstrThumb2.td1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
1385 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1508 // pseudos map between the two.
1528 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1611 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
2043 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
3693 bits<5> mode;
3700 let Inst{4-0} = mode;
3705 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3706 "$imod\t$iflags, $mode">;
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/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
H A DSystemZInstrFormats.td1 //==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
41 // "pseudo" or "target". This is used to map a pseduo memory instruction to
181 // bits<4> Mn : mode value for operand n
2409 AddressingMode mode = bdaddr12only>
2410 : InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
2416 AddressingMode mode = bdaddr20only>
2417 : InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
2465 AddressingMode mode = bdxaddr12only>
2466 : InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
2468 [(operator cls:$R1, mode:$XBD2)]> {
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/aosp_15_r20/external/tensorflow/tensorflow/compiler/mlir/lite/ir/
H A Dtfl_ops.td1461 This op also supports a Soft-NMS (with Gaussian weighting) mode (c.f.
1464 To enable this Soft-NMS mode, set the `soft_nms_sigma` parameter to be
2063 // non-quantization tablegen patterns. Currently, it is used by the
2129 // per Predicate inside the trait and get tablegen to use that to emit error
2791 // non-quantization tablegen patterns. Currently, it is used by the
2820 // non-quantization tablegen patterns. Currently, it is used by the
2849 // non-quantization tablegen patterns. Currently, it is used by the
3279 // non-quantization tablegen patterns. Currently, it is used by the
3837 TFL_MirrorPaddingAttr:$mode
5059 // Used to map StatelessWhile and While op defined in TensorFlow to a common
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMInstrInfo.td1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
416 // Operands that are part of a memory addressing mode.
427 // Branches targeting ARM-mode must be divisible by 4 if they're a raw
433 // Branches targeting Thumb-mode must be divisible by 2 if they're a raw
453 // Target for BLX *from* ARM mode.
2008 /// mode). Used mostly in ARM and Thumb-1 modes.
2110 bits<5> mode;
2116 let Inst{17} = M; // Enabled if mode is set;
2120 let Inst{4-0} = mode;
2125 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
[all …]
H A DARMInstrThumb2.td1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
1564 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1697 // pseudos map between the two.
1720 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1805 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
2280 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
3921 bits<5> mode;
3928 let Inst{4-0} = mode;
3933 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3934 "$imod\t$iflags, $mode">;
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/SystemZ/
H A DSystemZInstrFormats.td1 //==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
41 // "pseudo" or "target". This is used to map a pseduo memory instruction to
181 // bits<4> Mn : mode value for operand n
2537 AddressingMode mode = bdaddr12only>
2538 : InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
2544 AddressingMode mode = bdaddr20only>
2545 : InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
2593 AddressingMode mode = bdxaddr12only>
2594 : InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
2596 [(operator cls:$R1, mode:$XBD2)]> {
[all …]

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