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/linux-6.14.4/tools/perf/Documentation/
Dperf-arm-spe.txt1 perf-arm-spe(1)
5 ----
6 perf-arm-spe - Support for Arm Statistical Profiling Extension within Perf tools
9 --------
11 'perf record' -e arm_spe//
14 -----------
16 The SPE (Statistical Profiling Extension) feature provides accurate attribution of latencies and
17 events down to individual instructions. Rather than being interrupt-driven, it picks an
32 This is chosen from a sample population, for SPE this is an IMPLEMENTATION DEFINED choice of all
33 architectural instructions or all micro-ops. Sampling happens at a programmable interval. The
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Dperf-c2c.txt1 perf-c2c(1)
5 ----
6 perf-c2c - Shared Data C2C/HITM Analyzer.
9 --------
12 'perf c2c record' [<options>] \-- [<record command options>] <command>
16 -----------
24 with thresholding feature. On AMD, the tool uses IBS op pmu (due to hardware
25 limitations, perf c2c is not supported on Zen3 cpus). On Arm64 it uses SPE to
27 required. See linkperf:perf-arm-spe[1] for a setup guide. Due to the
28 statistical nature of Arm SPE sampling, not every memory operation will be
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Dperf.txt5 ----
6 perf - Performance analysis tools for Linux
9 --------
11 'perf' [--version] [--help] [OPTIONS] COMMAND [ARGS]
14 -------
15 -h::
16 --help::
19 -v::
20 --version::
23 -vv::
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Dperf-record.txt1 perf-record(1)
5 ----
6 perf-record - Run a command and record its profile into perf.data
9 --------
11 'perf record' [-e <EVENT> | --event=EVENT] [-a] <command>
12 'perf record' [-e <EVENT> | --event=EVENT] [-a] \-- <command> [<options>]
15 -----------
17 from it, into perf.data - without displaying anything.
23 -------
27 -e::
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/linux-6.14.4/Documentation/devicetree/bindings/perf/
Dspe-pmu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/spe-pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU)
10 - Will Deacon <[email protected]>
14 performance sample data using an in-memory trace buffer.
18 const: arm,statistical-profiling-extension-v1
23 The PPI to signal SPE events. For heterogeneous systems where SPE is only
24 supported on a subset of the CPUs, please consult the arm,gic-v3 binding
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/linux-6.14.4/tools/perf/arch/arm64/util/
Darm-spe.c1 // SPDX-License-Identifier: GPL-2.0
3 * Arm Statistical Profiling Extensions (SPE) support
4 * Copyright (c) 2017-2018, Arm Ltd.
22 #include "../../../util/pmu.h"
27 #include "../../../util/arm-spe.h"
49 struct perf_cpu_map *event_cpus = evlist->core.user_requested_cpus; in arm_spe_find_cpus()
88 struct perf_pmu *pmu = NULL; in arm_spe_save_cpu_header() local
95 return -ENOMEM; in arm_spe_save_cpu_header()
100 data[ARM_SPE_CPU_NR_PARAMS] = ARM_SPE_CPU_PRIV_MAX - ARM_SPE_CPU_MIDR; in arm_spe_save_cpu_header()
103 /* Find the associate Arm SPE PMU for the CPU */ in arm_spe_save_cpu_header()
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DBuild1 perf-util-y += header.o
2 perf-util-y += machine.o
3 perf-util-y += perf_regs.o
4 perf-util-y += tsc.o
5 perf-util-y += pmu.o
6 perf-util-$(CONFIG_LIBTRACEEVENT) += kvm-stat.o
7 perf-util-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
8 perf-util-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o
10 perf-util-$(CONFIG_AUXTRACE) += ../../arm/util/pmu.o \
12 ../../arm/util/cs-etm.o \
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/linux-6.14.4/tools/perf/tests/shell/
Dtest_arm_spe.sh2 # Check Arm SPE trace data recording and synthesized samples (exclusive)
4 # Uses the 'perf record' to record trace data of Arm SPE events;
5 # then verify if any SPE event samples are generated by SPE with
8 # SPDX-License-Identifier: GPL-2.0
12 perf list pmu | grep -E -q 'arm_spe_[0-9]+//' && return 0
25 rm -f ${perfdata}
26 rm -f ${perfdata}.old
46 # from arm-spe.c/arm_spe_synth_events()
47 …events="(ld1-miss|ld1-access|llc-miss|lld-access|tlb-miss|tlb-access|branch-miss|remote-access|mem…
50 …# dd 3048 [002] 1 l1d-access: ffffaa64999c __GI___libc_write+0x3c (/lib/aarch64-…
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Dtest_arm_spe_fork.sh2 # Check Arm SPE doesn't hang when there are forks
4 # SPDX-License-Identifier: GPL-2.0
8 perf list pmu | grep -E -q 'arm_spe_[0-9]+//' && return 0
14 TEST_PROGRAM="perf test -w sqrtloop 10"
21 rm -f ${PERF_RECORD_LOG}
22 rm -f ${PERF_DATA}
28 perf record -o ${PERF_DATA} -e arm_spe/period=65536/ -vvv -- $TEST_PROGRAM > ${PERF_RECORD_LOG} 2>&…
31 # Check if perf hangs by checking the perf-record logs.
33 log0=$(wc -l $PERF_RECORD_LOG)
36 log1=$(wc -l $PERF_RECORD_LOG)
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/linux-6.14.4/arch/arm64/kvm/hyp/nvhe/
Dswitch.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 - ARM Ltd
8 #include <hyp/sysreg-sr.h>
10 #include <linux/arm-smccc.h>
26 #include <asm/debug-monitors.h>
31 /* Non-VHE specific context */
99 ___activate_traps(vcpu, vcpu->arch.hcr_el2); in __activate_traps()
106 struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; in __activate_traps()
145 write_sysreg(this_cpu_ptr(&kvm_init_params)->hcr_el2, hcr_el2); in __deactivate_traps()
151 /* Save VGICv3 state on non-VHE systems */
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/linux-6.14.4/tools/perf/arch/arm/util/
Dpmu.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/coresight-pmu.h>
12 #include "arm-spe.h"
13 #include "hisi-ptt.h"
15 #include "../../../util/pmu.h"
16 #include "../../../util/cs-etm.h"
17 #include "../../arm64/util/mem-events.h"
19 void perf_pmu__arch_init(struct perf_pmu *pmu) in perf_pmu__arch_init() argument
24 if (!strcmp(pmu->name, CORESIGHT_ETM_PMU_NAME)) { in perf_pmu__arch_init()
26 pmu->auxtrace = true; in perf_pmu__arch_init()
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Dauxtrace.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/coresight-pmu.h>
16 #include "../../../util/pmu.h"
18 #include "cs-etm.h"
19 #include "arm-spe.h"
20 #include "hisi-ptt.h"
32 *err = -ENOMEM; in find_all_arm_spe_pmus()
40 *err = -ENOMEM; in find_all_arm_spe_pmus()
48 arm_spe_pmus[*nr_spes]->type, in find_all_arm_spe_pmus()
49 arm_spe_pmus[*nr_spes]->name); in find_all_arm_spe_pmus()
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/linux-6.14.4/tools/perf/util/
Darm-spe.c1 // SPDX-License-Identifier: GPL-2.0
3 * Arm Statistical Profiling Extensions (SPE) support
4 * Copyright (c) 2017-2018, Arm Ltd.
28 #include "thread-stack.h"
31 #include "util/synthetic-events.h"
33 #include "arm-spe.h"
34 #include "arm-spe-decoder/arm-spe-decoder.h"
35 #include "arm-spe-decoder/arm-spe-pkt-decoder.h"
90 struct arm_spe *spe; member
120 static void arm_spe_dump(struct arm_spe *spe __maybe_unused, in arm_spe_dump()
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Darm-spe.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Arm Statistical Profiling Extensions (SPE) support
4 * Copyright (c) 2017-2018, Arm Ltd.
30 /* PMU type shared by CPUs */
46 /* Associated PMU type */
DBuild4 perf-util-y += arm64-frame-pointer-unwind-support.o
5 perf-util-y += addr_location.o
6 perf-util-y += annotate.o
7 perf-util-y += block-info.o
8 perf-util-y += block-range.o
9 perf-util-y += build-id.o
10 perf-util-y += cacheline.o
11 perf-util-y += config.o
12 perf-util-y += copyfile.o
13 perf-util-y += ctype.o
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/linux-6.14.4/drivers/perf/
Darm_pmu_acpi.c1 // SPDX-License-Identifier: GPL-2.0-only
29 gsi = gicc->performance_interrupt; in arm_pmu_acpi_register_irq()
32 * Per the ACPI spec, the MADT cannot describe a PMU that doesn't in arm_pmu_acpi_register_irq()
41 if (gicc->flags & ACPI_MADT_PERFORMANCE_IRQ_MODE) in arm_pmu_acpi_register_irq()
67 gsi = gicc->performance_interrupt; in arm_pmu_acpi_unregister_irq()
83 if (pdev->num_resources != 1) in arm_acpi_register_pmu_device()
84 return -ENXIO; in arm_acpi_register_pmu_device()
86 if (pdev->resource[0].flags != IORESOURCE_IRQ) in arm_acpi_register_pmu_device()
87 return -ENXIO; in arm_acpi_register_pmu_device()
97 if (gicc->header.length < len) in arm_acpi_register_pmu_device()
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Darm_spe_pmu.c1 // SPDX-License-Identifier: GPL-2.0-only
53 if (IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR) && !perf_allow_kernel(&event->attr)) in set_spe_event_has_cx()
54 event->hw.flags |= SPE_PMU_HW_FLAGS_CX; in set_spe_event_has_cx()
59 return !!(event->hw.flags & SPE_PMU_HW_FLAGS_CX); in get_spe_event_has_cx()
71 struct pmu pmu; member
97 #define to_spe_pmu(p) (container_of(p, struct arm_spe_pmu, pmu))
99 /* Convert a free-running index from perf into an SPE buffer offset */
100 #define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT))
128 return !!(spe_pmu->features & arm_spe_pmu_feat_caps[cap]); in arm_spe_pmu_cap_get()
132 return spe_pmu->counter_sz; in arm_spe_pmu_cap_get()
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/linux-6.14.4/arch/powerpc/platforms/
DKconfig.cputype1 # SPDX-License-Identifier: GPL-2.0
7 bool "64-bit kernel"
10 This option selects whether a 32-bit or a 64-bit kernel
272 default "-mtune=power10" if $(cc-option,-mtune=power10)
273 default "-mtune=power9" if $(cc-option,-mtune=power9)
274 default "-mtune=power8" if $(cc-option,-mtune=power8)
351 This option enables kernel support for larger than 32-bit physical
356 is platform-dependent.
372 any affect on a non-altivec cpu (it does, however add code to the
388 VSX (P7 and above), but does not have any affect on a non-VSX
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/linux-6.14.4/arch/powerpc/include/asm/
Dcell-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * on-chip system devices (memory controller, IO controller, etc...)
19 #include <asm/cell-pmu.h>
43 u8 spe[8]; member
50 u32 spe; member
61 u8 pad_0x0010_0x00a8 [0x00a8 - 0x0010]; /* 0x0010 */
65 u8 pad_0x00b0_0x0100 [0x0100 - 0x00b0]; /* 0x00b0 */
73 u8 pad_0x0128_0x0400 [0x0400 - 0x0128]; /* 0x0128 */
83 u8 pad_0x0480_0x0800 [0x0800 - 0x0480]; /* 0x0480 */
111 u8 pad_0x0898_0x0c00 [0x0c00 - 0x0898]; /* 0x0898 */
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/linux-6.14.4/include/linux/perf/
Darm_pmu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/include/asm/pmu.h
20 * The Armv7 and Armv8.8 or less CPU PMU supports up to 32 event counters.
21 * The Armv8.9/9.4 CPU PMU supports up to 33 event counters.
29 * ARM PMU hw_event flags
44 [0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
47 [0 ... C(MAX) - 1] = { \
48 [0 ... C(OP_MAX) - 1] = { \
49 [0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \
53 /* The events for a given PMU register set. */
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/linux-6.14.4/arch/arm64/include/asm/
Del2_setup.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012,2013 - ARM Ltd
11 #error Assembly-only header
17 #include <linux/irqchip/arm-gic-v3.h>
23 * Compliant CPUs advertise their VHE-onlyness with
76 * Allow Non-secure EL1 and EL0 to access physical timer and counter.
99 b.eq .Lskip_pmu_\@ // Skip if no PMU present or IMP_DEF
103 csel x2, xzr, x0, eq // all PMU counters from EL1
107 cbz x0, .Lskip_spe_\@ // Skip if SPE not present
109 mrs_s x0, SYS_PMBIDR_EL1 // If SPE available at EL2,
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/linux-6.14.4/arch/arm64/boot/dts/arm/
Dfoundation-v8.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Foundation-v8A";
16 compatible = "arm,foundation-aarch64", "arm,vexpress";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 stdout-path = "serial0:115200n8";
33 #address-cells = <2>;
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Dfvp-base-revc.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
18 #include "rtsm_ve-motherboard-rs2.dtsi"
22 compatible = "arm,fvp-base-revc", "arm,vexpress";
23 interrupt-parent = <&gic>;
24 #address-cells = <2>;
25 #size-cells = <2>;
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/linux-6.14.4/drivers/ps3/
Dps3-lpm.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <asm/cell-pmu.h>
66 * struct ps3_lpm_shadow_regs - Performance monitor shadow registers.
73 * The logical performance monitor provides a write-only interface to
91 * struct ps3_lpm_priv - Private lpm device data.
137 * lpm_priv - Static instance of the lpm data.
148 BUG_ON(!lpm_priv || !lpm_priv->sbd); in sbd_core()
149 return &lpm_priv->sbd->core; in sbd_core()
153 * use_start_stop_bookmark - Enable the PPU bookmark trace.
192 * ps3_read_phys_ctr - Read physical counter registers.
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/linux-6.14.4/drivers/dma/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
80 depends on 440SPe || 440SP
112 tristate "Analog Devices AXI-DMAC DMA support"
118 Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
154 tristate "SA-11x0 DMA support"
159 Support the DMA engine found on Intel StrongARM SA-1100 and
160 SA-1110 SoCs. This DMA engine can only be used with on-chip
220 This module can be found on Freescale Vybrid and LS-1 SoCs.
263 Enable support for the IMG multi-threaded DMA controller (MDC).
283 tristate "Intel integrated DMA 64-bit support"
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