Lines Matching +full:spe +full:- +full:pmu
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/include/asm/pmu.h
20 * The Armv7 and Armv8.8 or less CPU PMU supports up to 32 event counters.
21 * The Armv8.9/9.4 CPU PMU supports up to 33 event counters.
29 * ARM PMU hw_event flags
44 [0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
47 [0 ... C(MAX) - 1] = { \
48 [0 ... C(OP_MAX) - 1] = { \
49 [0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \
53 /* The events for a given PMU register set. */
56 * The events that are active on the PMU for the given index.
84 struct pmu pmu; member
88 irqreturn_t (*handle_irq)(struct arm_pmu *pmu);
104 bool secure_access; /* 32-bit ARM only */
113 /* the attr_groups array must be NULL-terminated */
122 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
169 void kvm_host_pmu_init(struct arm_pmu *pmu);
178 void armpmu_free(struct arm_pmu *pmu);
179 int armpmu_register(struct arm_pmu *pmu);
183 #define ARMV8_PMU_PDEV_NAME "armv8-pmu"
187 #define ARMV8_SPE_PDEV_NAME "arm,spe-v1"
192 (lo) == (hi) ? #cfg ":" #lo "\n" : #cfg ":" #lo "-" #hi
204 ((((attr)->cfg) >> lo) & GENMASK_ULL(hi - lo, 0))