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/linux-6.14.4/Documentation/devicetree/bindings/interconnect/
Dqcom,sm8550-rpmh.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,sm8550-rpmh.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM8550
10 - Abel Vesa <[email protected]>
11 - Neil Armstrong <[email protected]>
21 See also:: include/dt-bindings/interconnect/qcom,sm8550-rpmh.h
26 - qcom,sm8550-aggre1-noc
27 - qcom,sm8550-aggre2-noc
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/linux-6.14.4/Documentation/devicetree/bindings/pci/
Dqcom,pcie-sm8550.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8550 PCI Express Root Complex
10 - Bjorn Andersson <[email protected]>
11 - Manivannan Sadhasivam <[email protected]>
14 Qualcomm SM8550 SoC (and compatible) PCIe root complex controller is based on
15 the Synopsys DesignWare PCIe IP.
20 - const: qcom,pcie-sm8550
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/linux-6.14.4/Documentation/devicetree/bindings/phy/
Dqcom,sc8280xp-qmp-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
10 - Vinod Koul <[email protected]>
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,qcs615-qmp-gen3x1-pcie-phy
20 - qcom,sa8775p-qmp-gen4x2-pcie-phy
21 - qcom,sa8775p-qmp-gen4x4-pcie-phy
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Dqcom,sc8280xp-qmp-ufs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <[email protected]>
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - items:
20 - enum:
21 - qcom,qcs615-qmp-ufs-phy
22 - const: qcom,sm6115-qmp-ufs-phy
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Dqcom,sc8280xp-qmp-usb43dp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP)
10 - Vinod Koul <[email protected]>
14 controllers on Qualcomm chipsets, such as, PCIe, UFS and USB.
19 - qcom,sar2130p-qmp-usb3-dp-phy
20 - qcom,sc7180-qmp-usb3-dp-phy
21 - qcom,sc7280-qmp-usb3-dp-phy
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/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dqcom,sm8550-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SM8550
10 - Bjorn Andersson <[email protected]>
14 domains on SM8550
16 See also:: include/dt-bindings/clock/qcom,sm8550-gcc.h
20 const: qcom,sm8550-gcc
24 - description: Board XO source
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/linux-6.14.4/drivers/clk/qcom/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
48 USB, UFS, SD/eMMC, PCIe, etc.
170 i2c, USB, SD/eMMC, SATA, PCIe, etc.
342 i2c, USB, SD/eMMC, SATA, PCIe, etc.
393 i2c, USB, SD/eMMC, SATA, PCIe, etc.
411 i2c, USB, SD/eMMC, SATA, PCIe, etc.
427 i2c, USB, UFS, SD/eMMC, PCIe, etc.
435 i2c, USB, UFS, SD/eMMC, PCIe, etc.
452 i2c, USB, UFS, SD/eMMC, PCIe, etc.
494 devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc.
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/linux-6.14.4/arch/arm64/boot/dts/qcom/
Dsm8550.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
8 #include <dt-bindings/clock/qcom,sm8550-camcc.h>
9 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
10 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
11 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
12 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
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Dsar2130p.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sar2130p-gcc.h>
8 #include <dt-bindings/clock/qcom,sar2130p-gpucc.h>
9 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/interconnect/qcom,icc.h>
12 #include <dt-bindings/interconnect/qcom,sar2130p-rpmh.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/mailbox/qcom-ipcc.h>
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Dsm8650.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8650-camcc.h>
8 #include <dt-bindings/clock/qcom,sm8650-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm8650-gcc.h>
10 #include <dt-bindings/clock/qcom,sm8650-gpucc.h>
11 #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
12 #include <dt-bindings/clock/qcom,sm8650-videocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
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Dx1e80100.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
8 #include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
9 #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
10 #include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
11 #include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
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Dsdx75.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,sdx75.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/power/qcom,rpmhpd.h>
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/linux-6.14.4/drivers/interconnect/qcom/
Dsm8550.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/interconnect-provider.h>
16 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
18 #include "bcm-voter.h"
19 #include "icc-common.h"
20 #include "icc-rpmh.h"
21 #include "sm8550.h"
1614 { .compatible = "qcom,sm8550-aggre1-noc",
1616 { .compatible = "qcom,sm8550-aggre2-noc",
1618 { .compatible = "qcom,sm8550-clk-virt",
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/linux-6.14.4/Documentation/driver-api/
Dinterconnect.rst1 .. SPDX-License-Identifier: GPL-2.0
8 ------------
20 on an SoC that can be multi-tiered.
22 Below is a simplified diagram of a real-world SoC interconnect bus topology.
26 +----------------+ +----------------+
27 | HW Accelerator |--->| M NoC |<---------------+
28 +----------------+ +----------------+ |
29 | | +------------+
30 +-----+ +-------------+ V +------+ | |
31 | DDR | | +--------+ | PCIe | | |
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/linux-6.14.4/drivers/pci/controller/dwc/
Dpcie-qcom.c1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm PCIe root complex driver
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
28 #include <linux/phy/pcie.h>
37 #include "pcie-designware.h"
38 #include "pcie-qcom-common.h"
244 int (*get_resources)(struct qcom_pcie *pcie);
245 int (*init)(struct qcom_pcie *pcie);
246 int (*post_init)(struct qcom_pcie *pcie);
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/linux-6.14.4/drivers/phy/qualcomm/
Dphy-qcom-qmp-pcie.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
17 #include <linux/phy/pcie.h>
25 #include <dt-bindings/phy/phy-qcom-qmp.h>
27 #include "phy-qcom-qmp-common.h"
29 #include "phy-qcom-qmp.h"
30 #include "phy-qcom-qmp-pcs-misc-v3.h"
31 #include "phy-qcom-qmp-pcs-pcie-v4.h"
32 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
33 #include "phy-qcom-qmp-pcs-pcie-v5.h"
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/linux-6.14.4/drivers/net/ipa/
Dipa_main.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2024 Linaro Ltd.
51 * currently supported. Despite that, some resources--including routing
52 * tables and filter tables--are defined in this driver because they must
58 * well-defined communication layer between the AP subsystem and the IPA
101 * ipa_setup() - Set up IPA hardware
115 struct device *dev = ipa->dev; in ipa_setup()
118 ret = gsi_setup(&ipa->gsi); in ipa_setup()
127 command_endpoint = ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX]; in ipa_setup()
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