1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sar2130p-gcc.h> 8#include <dt-bindings/clock/qcom,sar2130p-gpucc.h> 9#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/interconnect/qcom,icc.h> 12#include <dt-bindings/interconnect/qcom,sar2130p-rpmh.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/mailbox/qcom-ipcc.h> 15#include <dt-bindings/phy/phy-qcom-qmp.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/power/qcom,rpmhpd.h> 18#include <dt-bindings/soc/qcom,gpr.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/thermal/thermal.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 chosen { }; 29 30 clocks { 31 xo_board: xo-board { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <19200000>; 35 }; 36 37 sleep_clk: sleep-clk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <32764>; 41 }; 42 }; 43 44 cpus { 45 #address-cells = <2>; 46 #size-cells = <0>; 47 48 cpu0: cpu@0 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a55"; 51 reg = <0x0 0x0>; 52 clocks = <&cpufreq_hw 0>; 53 enable-method = "psci"; 54 next-level-cache = <&l2_0>; 55 qcom,freq-domain = <&cpufreq_hw 0>; 56 power-domains = <&cpu_pd0>; 57 power-domain-names = "psci"; 58 #cooling-cells = <2>; 59 60 l2_0: l2-cache { 61 compatible = "cache"; 62 cache-level = <2>; 63 cache-unified; 64 next-level-cache = <&l3_0>; 65 66 l3_0: l3-cache { 67 compatible = "cache"; 68 cache-level = <3>; 69 cache-unified; 70 }; 71 }; 72 }; 73 74 cpu1: cpu@100 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a55"; 77 reg = <0x0 0x100>; 78 clocks = <&cpufreq_hw 0>; 79 enable-method = "psci"; 80 next-level-cache = <&l2_100>; 81 qcom,freq-domain = <&cpufreq_hw 0>; 82 power-domains = <&cpu_pd1>; 83 power-domain-names = "psci"; 84 #cooling-cells = <2>; 85 86 l2_100: l2-cache { 87 compatible = "cache"; 88 cache-level = <2>; 89 cache-unified; 90 next-level-cache = <&l3_0>; 91 }; 92 }; 93 94 cpu2: cpu@200 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a55"; 97 reg = <0x0 0x200>; 98 clocks = <&cpufreq_hw 0>; 99 enable-method = "psci"; 100 next-level-cache = <&l2_200>; 101 qcom,freq-domain = <&cpufreq_hw 0>; 102 power-domains = <&cpu_pd2>; 103 power-domain-names = "psci"; 104 #cooling-cells = <2>; 105 106 l2_200: l2-cache { 107 compatible = "cache"; 108 cache-level = <2>; 109 cache-unified; 110 next-level-cache = <&l3_0>; 111 }; 112 }; 113 114 cpu3: cpu@300 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a55"; 117 reg = <0x0 0x300>; 118 clocks = <&cpufreq_hw 0>; 119 enable-method = "psci"; 120 next-level-cache = <&l2_300>; 121 qcom,freq-domain = <&cpufreq_hw 0>; 122 power-domains = <&cpu_pd3>; 123 power-domain-names = "psci"; 124 #cooling-cells = <2>; 125 126 l2_300: l2-cache { 127 compatible = "cache"; 128 cache-level = <2>; 129 cache-unified; 130 next-level-cache = <&l3_0>; 131 }; 132 }; 133 134 cpu-map { 135 cluster0 { 136 core0 { 137 cpu = <&cpu0>; 138 }; 139 140 core1 { 141 cpu = <&cpu1>; 142 }; 143 144 core2 { 145 cpu = <&cpu2>; 146 }; 147 148 core3 { 149 cpu = <&cpu3>; 150 }; 151 }; 152 }; 153 154 idle-states { 155 entry-method = "psci"; 156 157 cpu_sleep_0: cpu-sleep-0-0 { 158 compatible = "arm,idle-state"; 159 idle-state-name = "silver-power-collapse"; 160 arm,psci-suspend-param = <0x40000003>; 161 entry-latency-us = <549>; 162 exit-latency-us = <901>; 163 min-residency-us = <1774>; 164 local-timer-stop; 165 }; 166 167 cpu_sleep_1: cpu-sleep-0-1 { 168 compatible = "arm,idle-state"; 169 idle-state-name = "silver-rail-power-collapse"; 170 arm,psci-suspend-param = <0x40000004>; 171 entry-latency-us = <702>; 172 exit-latency-us = <915>; 173 min-residency-us = <4001>; 174 local-timer-stop; 175 }; 176 }; 177 178 domain-idle-states { 179 cluster_sleep_0: cluster-sleep-0 { 180 compatible = "domain-idle-state"; 181 arm,psci-suspend-param = <0x41000044>; 182 entry-latency-us = <2752>; 183 exit-latency-us = <3048>; 184 min-residency-us = <6118>; 185 }; 186 187 cluster_sleep_1: cluster-sleep-1 { 188 compatible = "domain-idle-state"; 189 arm,psci-suspend-param = <0x41002344>; 190 entry-latency-us = <3263>; 191 exit-latency-us = <4562>; 192 min-residency-us = <8467>; 193 }; 194 195 cluster_sleep_2: cluster-sleep-2 { 196 compatible = "domain-idle-state"; 197 arm,psci-suspend-param = <0x4100c344>; 198 entry-latency-us = <3638>; 199 exit-latency-us = <6562>; 200 min-residency-us = <9862>; 201 }; 202 }; 203 }; 204 205 firmware { 206 scm: scm { 207 compatible = "qcom,scm-sar2130p", "qcom,scm"; 208 qcom,dload-mode = <&tcsr_mutex 0x13000>; 209 interconnects = <&system_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 210 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 211 }; 212 }; 213 214 clk_virt: interconnect-0 { 215 compatible = "qcom,sar2130p-clk-virt"; 216 #interconnect-cells = <2>; 217 qcom,bcm-voters = <&apps_bcm_voter>; 218 }; 219 220 mc_virt: interconnect-1 { 221 compatible = "qcom,sar2130p-mc-virt"; 222 #interconnect-cells = <2>; 223 qcom,bcm-voters = <&apps_bcm_voter>; 224 }; 225 226 memory@80000000 { 227 device_type = "memory"; 228 /* We expect the bootloader to fill in the size */ 229 reg = <0x0 0x80000000 0x0 0x0>; 230 }; 231 232 pmu { 233 compatible = "arm,armv8-pmuv3"; 234 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 235 }; 236 237 psci { 238 compatible = "arm,psci-1.0"; 239 method = "smc"; 240 241 cpu_pd0: power-domain-cpu0 { 242 #power-domain-cells = <0>; 243 power-domains = <&cluster_pd>; 244 domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>; 245 }; 246 247 cpu_pd1: power-domain-cpu1 { 248 #power-domain-cells = <0>; 249 power-domains = <&cluster_pd>; 250 domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>; 251 }; 252 253 cpu_pd2: power-domain-cpu2 { 254 #power-domain-cells = <0>; 255 power-domains = <&cluster_pd>; 256 domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>; 257 }; 258 259 cpu_pd3: power-domain-cpu3 { 260 #power-domain-cells = <0>; 261 power-domains = <&cluster_pd>; 262 domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>; 263 }; 264 265 cluster_pd: power-domain-cpu-cluster0 { 266 #power-domain-cells = <0>; 267 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>, <&cluster_sleep_2>; 268 }; 269 }; 270 271 reserved_memory: reserved-memory { 272 #address-cells = <2>; 273 #size-cells = <2>; 274 ranges; 275 276 hyp_mem: hyp@80000000 { 277 reg = <0x0 0x80000000 0x0 0x600000>; 278 no-map; 279 }; 280 281 xbl_dt_log_mem: xbl-dt-log@80600000 { 282 reg = <0x0 0x80600000 0x0 0x40000>; 283 no-map; 284 }; 285 286 xbl_ramdump_mem: xbl-ramdump@80640000 { 287 reg = <0x0 0x80640000 0x0 0x1c0000>; 288 no-map; 289 }; 290 291 aop_image_mem: aop-image@80800000 { 292 reg = <0x0 0x80800000 0x0 0x60000>; 293 no-map; 294 }; 295 296 aop_cmd_db_mem: aop-cmd-db@80860000 { 297 compatible = "qcom,cmd-db"; 298 reg = <0x0 0x80860000 0x0 0x20000>; 299 no-map; 300 }; 301 302 aop_config_mem: aop-config@80880000 { 303 reg = <0x0 0x80880000 0x0 0x20000>; 304 no-map; 305 }; 306 307 tme_crash_dump_mem: tme-crash-dump@808a0000 { 308 reg = <0x0 0x808a0000 0x0 0x40000>; 309 no-map; 310 }; 311 312 tme_log_mem: tme-log@808e0000 { 313 reg = <0x0 0x808e0000 0x0 0x4000>; 314 no-map; 315 }; 316 317 uefi_log_mem: uefi-log@808e4000 { 318 reg = <0x0 0x808e4000 0x0 0x10000>; 319 no-map; 320 }; 321 322 secdata_apss_mem: secdata-apss@808ff000 { 323 reg = <0x0 0x808ff000 0x0 0x1000>; 324 no-map; 325 }; 326 327 smem: smem@80900000 { 328 compatible = "qcom,smem"; 329 reg = <0x0 0x80900000 0x0 0x200000>; 330 hwlocks = <&tcsr_mutex 3>; 331 no-map; 332 }; 333 334 cpucp_fw_mem: cpucp-fw@80b00000 { 335 reg = <0x0 0x80b00000 0x0 0x100000>; 336 no-map; 337 }; 338 339 helios_ram_dump_mem: helios-ram-dump@80c00000 { 340 reg = <0x0 0x80c00000 0x0 0xe00000>; 341 no-map; 342 }; 343 344 camera_mem: camera@84e00000 { 345 reg = <0x0 0x84e00000 0x0 0x800000>; 346 no-map; 347 }; 348 349 video_mem: video@86f00000 { 350 reg = <0x0 0x86f00000 0x0 0x500000>; 351 no-map; 352 }; 353 354 adsp_mem: adsp@87600000 { 355 reg = <0x0 0x87600000 0x0 0x1e00000>; 356 no-map; 357 }; 358 359 cdsp_mem: cdsp@89400000 { 360 reg = <0x0 0x89400000 0x0 0xf00000>; 361 no-map; 362 }; 363 364 ipa_fw_mem: ipa-fw@8a300000 { 365 reg = <0x0 0x8a300000 0x0 0x10000>; 366 no-map; 367 }; 368 369 ipa_gsi_mem: ipa-gsi@8a3a0000 { 370 reg = <0x0 0x8a310000 0x0 0xa000>; 371 no-map; 372 }; 373 374 gpu_micro_code_mem: gpu-micro-code@8a31a000 { 375 reg = <0x0 0x8a31a000 0x0 0x2000>; 376 no-map; 377 }; 378 379 cvp_mem: cvp@8a400000 { 380 reg = <0x0 0x8a400000 0x0 0x700000>; 381 no-map; 382 }; 383 384 xbl_sc_mem: xbl-sc@a6e00000 { 385 no-map; 386 reg = <0x0 0xa6e00000 0x0 0x40000>; 387 }; 388 389 global_sync_mem: global-sync@a6f00000 { 390 no-map; 391 reg = <0x0 0xa6f00000 0x0 0x100000>; 392 }; 393 394 tz_stat_mem: tz-stat@e8800000 { 395 no-map; 396 reg = <0x0 0xe8800000 0x0 0x100000>; 397 }; 398 399 tags_mem: tags@e8900000 { 400 no-map; 401 reg = <0x0 0xe8900000 0x0 0x500000>; 402 }; 403 404 qtee_mem: qtee@e8e00000 { 405 no-map; 406 reg = <0x0 0xe8e00000 0x0 0x500000>; 407 }; 408 409 trusted_apps_mem: trusted-apps@e9300000 { 410 no-map; 411 reg = <0x0 0xe9300000 0x0 0xc00000>; 412 }; 413 }; 414 415 smp2p-adsp { 416 compatible = "qcom,smp2p"; 417 qcom,smem = <443>, <429>; 418 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 419 IPCC_MPROC_SIGNAL_SMP2P 420 IRQ_TYPE_EDGE_RISING>; 421 mboxes = <&ipcc IPCC_CLIENT_LPASS 422 IPCC_MPROC_SIGNAL_SMP2P>; 423 424 qcom,local-pid = <0>; 425 qcom,remote-pid = <2>; 426 427 smp2p_adsp_out: master-kernel { 428 qcom,entry-name = "master-kernel"; 429 #qcom,smem-state-cells = <1>; 430 }; 431 432 smp2p_adsp_in: slave-kernel { 433 qcom,entry-name = "slave-kernel"; 434 interrupt-controller; 435 #interrupt-cells = <2>; 436 }; 437 }; 438 439 smp2p-cdsp { 440 compatible = "qcom,smp2p"; 441 qcom,smem = <94>, <432>; 442 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 443 IPCC_MPROC_SIGNAL_SMP2P 444 IRQ_TYPE_EDGE_RISING>; 445 mboxes = <&ipcc IPCC_CLIENT_CDSP 446 IPCC_MPROC_SIGNAL_SMP2P>; 447 448 qcom,local-pid = <0>; 449 qcom,remote-pid = <5>; 450 451 smp2p_cdsp_out: master-kernel { 452 qcom,entry-name = "master-kernel"; 453 #qcom,smem-state-cells = <1>; 454 }; 455 456 smp2p_cdsp_in: slave-kernel { 457 qcom,entry-name = "slave-kernel"; 458 interrupt-controller; 459 #interrupt-cells = <2>; 460 }; 461 }; 462 463 soc: soc@0 { 464 compatible = "simple-bus"; 465 #address-cells = <2>; 466 #size-cells = <2>; 467 ranges = <0 0 0 0 0x10 0>; 468 dma-ranges = <0 0 0 0 0x10 0>; 469 470 gcc: clock-controller@100000 { 471 compatible = "qcom,sar2130p-gcc"; 472 reg = <0x0 0x00100000 0x0 0x1f4200>; 473 #clock-cells = <1>; 474 #reset-cells = <1>; 475 #power-domain-cells = <1>; 476 clocks = <&rpmhcc RPMH_CXO_CLK>, 477 <&sleep_clk>, 478 <&pcie0_phy>, 479 <&pcie1_phy>, 480 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 481 }; 482 483 sdhc_1: mmc@7c4000 { 484 compatible = "qcom,sar2130p-sdhci", "qcom,sdhci-msm-v5"; 485 reg = <0x0 0x007c4000 0x0 0x1000>, 486 <0x0 0x007c5000 0x0 0x1000>; 487 reg-names = "hc", "cqhci"; 488 489 iommus = <&apps_smmu 0x160 0x0>; 490 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 492 interrupt-names = "hc_irq", "pwr_irq"; 493 494 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 495 <&gcc GCC_SDCC1_APPS_CLK>, 496 <&rpmhcc RPMH_CXO_CLK>; 497 clock-names = "iface", "core", "xo"; 498 interconnects = <&system_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS 499 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 500 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 501 &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>; 502 interconnect-names = "sdhc-ddr","cpu-sdhc"; 503 power-domains = <&rpmhpd RPMHPD_CX>; 504 operating-points-v2 = <&sdhc1_opp_table>; 505 506 pinctrl-0 = <&sdc1_default>; 507 pinctrl-1 = <&sdc1_sleep>; 508 pinctrl-names = "default", "sleep"; 509 510 bus-width = <8>; 511 non-removable; 512 supports-cqe; 513 514 mmc-ddr-1_8v; 515 mmc-hs200-1_8v; 516 mmc-hs400-1_8v; 517 mmc-hs400-enhanced-strobe; 518 519 status = "disabled"; 520 521 sdhc1_opp_table: opp-table { 522 compatible = "operating-points-v2"; 523 524 opp-100000000 { 525 opp-hz = /bits/ 64 <100000000>; 526 required-opps = <&rpmhpd_opp_low_svs>; 527 opp-peak-kBps = <500000 200000>; 528 opp-avg-kBps = <104000 0>; 529 }; 530 531 opp-384000000 { 532 opp-hz = /bits/ 64 <384000000>; 533 required-opps = <&rpmhpd_opp_nom>; 534 opp-peak-kBps = <2500000 1000000>; 535 opp-avg-kBps = <400000 0>; 536 }; 537 }; 538 }; 539 540 gpi_dma0: dma-controller@900000 { 541 compatible = "qcom,sar2130p-gpi-dma", "qcom,sm6350-gpi-dma"; 542 reg = <0x0 0x00900000 0x0 0x60000>; 543 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 555 #dma-cells = <3>; 556 dma-channels = <12>; 557 dma-channel-mask = <0x7e>; 558 iommus = <&apps_smmu 0x76 0x0>; 559 560 status = "disabled"; 561 }; 562 563 qupv3_id_0: geniqup@9c0000 { 564 compatible = "qcom,geni-se-qup"; 565 reg = <0x0 0x009c0000 0x0 0x2000>; 566 clock-names = "m-ahb", "s-ahb"; 567 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 568 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 569 iommus = <&apps_smmu 0x63 0x0>; 570 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 571 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>; 572 interconnect-names = "qup-core"; 573 #address-cells = <2>; 574 #size-cells = <2>; 575 ranges; 576 577 status = "disabled"; 578 579 i2c0: i2c@980000 { 580 compatible = "qcom,geni-i2c"; 581 reg = <0x0 0x00980000 0x0 0x4000>; 582 clock-names = "se"; 583 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 584 pinctrl-0 = <&qup_i2c0_data_clk>; 585 pinctrl-names = "default"; 586 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 590 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 591 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 592 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 593 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 594 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 595 interconnect-names = "qup-core", "qup-config", "qup-memory"; 596 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 597 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 598 dma-names = "tx", "rx"; 599 600 status = "disabled"; 601 }; 602 603 spi0: spi@980000 { 604 compatible = "qcom,geni-spi"; 605 reg = <0x0 0x00980000 0x0 0x4000>; 606 clock-names = "se"; 607 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 608 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 609 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs0>; 610 pinctrl-names = "default"; 611 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 612 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 613 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 614 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 615 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 616 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 617 interconnect-names = "qup-core", "qup-config", "qup-memory"; 618 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 619 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 620 dma-names = "tx", "rx"; 621 #address-cells = <1>; 622 #size-cells = <0>; 623 624 status = "disabled"; 625 }; 626 627 i2c1: i2c@984000 { 628 compatible = "qcom,geni-i2c"; 629 reg = <0x0 0x00984000 0x0 0x4000>; 630 clock-names = "se"; 631 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 632 pinctrl-0 = <&qup_i2c1_data_clk>; 633 pinctrl-names = "default"; 634 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 635 #address-cells = <1>; 636 #size-cells = <0>; 637 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 638 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 639 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 640 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 641 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 642 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 643 interconnect-names = "qup-core", "qup-config", "qup-memory"; 644 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 645 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 646 dma-names = "tx", "rx"; 647 648 status = "disabled"; 649 }; 650 651 spi1: spi@984000 { 652 compatible = "qcom,geni-spi"; 653 reg = <0x0 0x00984000 0x0 0x4000>; 654 clock-names = "se"; 655 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 656 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 657 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 658 pinctrl-names = "default"; 659 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 660 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 661 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 662 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 663 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 664 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 665 interconnect-names = "qup-core", "qup-config", "qup-memory"; 666 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 667 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 668 dma-names = "tx", "rx"; 669 #address-cells = <1>; 670 #size-cells = <0>; 671 672 status = "disabled"; 673 }; 674 675 i2c2: i2c@988000 { 676 compatible = "qcom,geni-i2c"; 677 reg = <0x0 0x00988000 0x0 0x4000>; 678 clock-names = "se"; 679 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 680 pinctrl-0 = <&qup_i2c2_data_clk>; 681 pinctrl-names = "default"; 682 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 683 #address-cells = <1>; 684 #size-cells = <0>; 685 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 686 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 687 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 688 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 689 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 690 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 691 interconnect-names = "qup-core", "qup-config", "qup-memory"; 692 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 693 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 694 dma-names = "tx", "rx"; 695 696 status = "disabled"; 697 }; 698 699 spi2: spi@988000 { 700 compatible = "qcom,geni-spi"; 701 reg = <0x0 0x00988000 0x0 0x4000>; 702 clock-names = "se"; 703 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 704 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 705 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 706 pinctrl-names = "default"; 707 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 708 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 709 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 710 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 711 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 712 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 713 interconnect-names = "qup-core", "qup-config", "qup-memory"; 714 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 715 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 716 dma-names = "tx", "rx"; 717 #address-cells = <1>; 718 #size-cells = <0>; 719 720 status = "disabled"; 721 }; 722 723 724 i2c3: i2c@98c000 { 725 compatible = "qcom,geni-i2c"; 726 reg = <0x0 0x0098c000 0x0 0x4000>; 727 clock-names = "se"; 728 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 729 pinctrl-0 = <&qup_i2c3_data_clk>; 730 pinctrl-names = "default"; 731 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 732 #address-cells = <1>; 733 #size-cells = <0>; 734 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 735 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 736 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 737 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 738 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 739 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 740 interconnect-names = "qup-core", "qup-config", "qup-memory"; 741 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 742 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 743 dma-names = "tx", "rx"; 744 745 status = "disabled"; 746 }; 747 748 spi3: spi@98c000 { 749 compatible = "qcom,geni-spi"; 750 reg = <0x0 0x0098c000 0x0 0x4000>; 751 clock-names = "se"; 752 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 753 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 754 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs0>; 755 pinctrl-names = "default"; 756 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 757 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 758 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 759 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 760 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 761 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 762 interconnect-names = "qup-core", "qup-config", "qup-memory"; 763 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 764 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 765 dma-names = "tx", "rx"; 766 #address-cells = <1>; 767 #size-cells = <0>; 768 769 status = "disabled"; 770 }; 771 772 i2c4: i2c@990000 { 773 compatible = "qcom,geni-i2c"; 774 reg = <0x0 0x00990000 0x0 0x4000>; 775 clock-names = "se"; 776 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 777 pinctrl-0 = <&qup_i2c4_data_clk>; 778 pinctrl-names = "default"; 779 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 780 #address-cells = <1>; 781 #size-cells = <0>; 782 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 783 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 784 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 785 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 786 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 787 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 788 interconnect-names = "qup-core", "qup-config", "qup-memory"; 789 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 790 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 791 dma-names = "tx", "rx"; 792 793 status = "disabled"; 794 }; 795 796 spi4: spi@990000 { 797 compatible = "qcom,geni-spi"; 798 reg = <0x0 0x00990000 0x0 0x4000>; 799 clock-names = "se"; 800 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 801 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 802 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs0>; 803 pinctrl-names = "default"; 804 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 805 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 806 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 807 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 808 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 809 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 810 interconnect-names = "qup-core", "qup-config", "qup-memory"; 811 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 812 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 813 dma-names = "tx", "rx"; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 817 status = "disabled"; 818 }; 819 820 i2c5: i2c@994000 { 821 compatible = "qcom,geni-i2c"; 822 reg = <0x0 0x00994000 0x0 0x4000>; 823 clock-names = "se"; 824 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 825 pinctrl-0 = <&qup_i2c5_data_clk>; 826 pinctrl-names = "default"; 827 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 828 #address-cells = <1>; 829 #size-cells = <0>; 830 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 831 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 832 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 833 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 834 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 835 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 836 interconnect-names = "qup-core", "qup-config", "qup-memory"; 837 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 838 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 839 dma-names = "tx", "rx"; 840 841 status = "disabled"; 842 }; 843 844 spi5: spi@994000 { 845 compatible = "qcom,geni-spi"; 846 reg = <0x0 0x00994000 0x0 0x4000>; 847 clock-names = "se"; 848 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 849 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 850 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 851 pinctrl-names = "default"; 852 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 853 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 854 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 855 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 856 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 857 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 858 interconnect-names = "qup-core", "qup-config", "qup-memory"; 859 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 860 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 861 dma-names = "tx", "rx"; 862 #address-cells = <1>; 863 #size-cells = <0>; 864 865 status = "disabled"; 866 }; 867 }; 868 869 gpi_dma1: dma-controller@a00000 { 870 compatible = "qcom,sar2130p-gpi-dma", "qcom,sm6350-gpi-dma"; 871 #dma-cells = <3>; 872 reg = <0x0 0x00a00000 0x0 0x60000>; 873 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 885 dma-channels = <12>; 886 dma-channel-mask = <0x7e>; 887 iommus = <&apps_smmu 0x16 0x0>; 888 889 status = "disabled"; 890 }; 891 892 qupv3_id_1: geniqup@ac0000 { 893 compatible = "qcom,geni-se-qup"; 894 reg = <0x0 0x00ac0000 0x0 0x6000>; 895 clock-names = "m-ahb", "s-ahb"; 896 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 897 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 898 iommus = <&apps_smmu 0x3 0x0>; 899 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 900 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; 901 interconnect-names = "qup-core"; 902 #address-cells = <2>; 903 #size-cells = <2>; 904 ranges; 905 906 status = "disabled"; 907 908 i2c6: i2c@a80000 { 909 compatible = "qcom,geni-i2c"; 910 reg = <0x0 0x00a80000 0x0 0x4000>; 911 clock-names = "se"; 912 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 913 pinctrl-0 = <&qup_i2c6_data_clk>; 914 pinctrl-names = "default"; 915 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 919 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 920 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 921 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 922 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 923 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 924 interconnect-names = "qup-core", "qup-config", "qup-memory"; 925 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 926 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 927 dma-names = "tx", "rx"; 928 929 status = "disabled"; 930 }; 931 932 spi6: spi@a80000 { 933 compatible = "qcom,geni-spi"; 934 reg = <0x0 0x00a80000 0x0 0x4000>; 935 clock-names = "se"; 936 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 937 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 938 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 939 pinctrl-names = "default"; 940 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 941 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 942 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 943 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 944 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 945 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 946 interconnect-names = "qup-core", "qup-config", "qup-memory"; 947 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 948 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 949 dma-names = "tx", "rx"; 950 #address-cells = <1>; 951 #size-cells = <0>; 952 953 status = "disabled"; 954 }; 955 956 i2c7: i2c@a84000 { 957 compatible = "qcom,geni-i2c"; 958 reg = <0x0 0x00a84000 0x0 0x4000>; 959 clock-names = "se"; 960 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 961 pinctrl-0 = <&qup_i2c7_data_clk>; 962 pinctrl-names = "default"; 963 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 964 #address-cells = <1>; 965 #size-cells = <0>; 966 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 967 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 968 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 969 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 970 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 971 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 972 interconnect-names = "qup-core", "qup-config", "qup-memory"; 973 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 974 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 975 dma-names = "tx", "rx"; 976 977 status = "disabled"; 978 }; 979 980 spi7: spi@a84000 { 981 compatible = "qcom,geni-spi"; 982 reg = <0x0 0x00a84000 0x0 0x4000>; 983 clock-names = "se"; 984 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 985 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 986 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 987 pinctrl-names = "default"; 988 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 989 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 990 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 991 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 992 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 993 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 994 interconnect-names = "qup-core", "qup-config", "qup-memory"; 995 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 996 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 997 dma-names = "tx", "rx"; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 1001 status = "disabled"; 1002 }; 1003 1004 uart7: serial@a84000 { 1005 compatible = "qcom,geni-uart"; 1006 reg = <0x0 0x00a84000 0x0 0x4000>; 1007 clock-names = "se"; 1008 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1009 pinctrl-0 = <&qup_uart7_default>; 1010 pinctrl-names = "default"; 1011 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1012 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1013 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1014 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1015 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>; 1016 interconnect-names = "qup-core", "qup-config"; 1017 1018 status = "disabled"; 1019 }; 1020 1021 i2c8: i2c@a88000 { 1022 compatible = "qcom,geni-i2c"; 1023 reg = <0x0 0x00a88000 0x0 0x4000>; 1024 clock-names = "se"; 1025 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1026 pinctrl-0 = <&qup_i2c8_data_clk>; 1027 pinctrl-names = "default"; 1028 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1032 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1033 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1034 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1035 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1036 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1037 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1038 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1039 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1040 dma-names = "tx", "rx"; 1041 1042 status = "disabled"; 1043 }; 1044 1045 spi8: spi@a88000 { 1046 compatible = "qcom,geni-spi"; 1047 reg = <0x0 0x00a88000 0x0 0x4000>; 1048 clock-names = "se"; 1049 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1050 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1051 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1052 pinctrl-names = "default"; 1053 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1054 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1055 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1056 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1057 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1058 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1059 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1060 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1061 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1062 dma-names = "tx", "rx"; 1063 #address-cells = <1>; 1064 #size-cells = <0>; 1065 1066 status = "disabled"; 1067 }; 1068 1069 i2c9: i2c@a8c000 { 1070 compatible = "qcom,geni-i2c"; 1071 reg = <0x0 0x00a8c000 0x0 0x4000>; 1072 clock-names = "se"; 1073 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1074 pinctrl-0 = <&qup_i2c9_data_clk>; 1075 pinctrl-names = "default"; 1076 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1077 #address-cells = <1>; 1078 #size-cells = <0>; 1079 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1080 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1081 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1082 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1083 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1084 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1085 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1086 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1087 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1088 dma-names = "tx", "rx"; 1089 1090 status = "disabled"; 1091 }; 1092 1093 spi9: spi@a8c000 { 1094 compatible = "qcom,geni-spi"; 1095 reg = <0x0 0x00a8c000 0x0 0x4000>; 1096 clock-names = "se"; 1097 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1098 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1099 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1100 pinctrl-names = "default"; 1101 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1102 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1103 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1104 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1105 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1106 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1107 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1108 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1109 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1110 dma-names = "tx", "rx"; 1111 #address-cells = <1>; 1112 #size-cells = <0>; 1113 1114 status = "disabled"; 1115 }; 1116 1117 i2c10: i2c@a90000 { 1118 compatible = "qcom,geni-i2c"; 1119 reg = <0x0 0x00a90000 0x0 0x4000>; 1120 clock-names = "se"; 1121 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1122 pinctrl-0 = <&qup_i2c10_data_clk>; 1123 pinctrl-names = "default"; 1124 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1125 #address-cells = <1>; 1126 #size-cells = <0>; 1127 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1128 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1129 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1130 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1131 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1132 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1133 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1134 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1135 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1136 dma-names = "tx", "rx"; 1137 1138 status = "disabled"; 1139 }; 1140 1141 spi10: spi@a90000 { 1142 compatible = "qcom,geni-spi"; 1143 reg = <0x0 0x00a90000 0x0 0x4000>; 1144 clock-names = "se"; 1145 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1146 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1147 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1148 pinctrl-names = "default"; 1149 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1150 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1151 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1152 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1153 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1154 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1155 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1156 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1157 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1158 dma-names = "tx", "rx"; 1159 #address-cells = <1>; 1160 #size-cells = <0>; 1161 1162 status = "disabled"; 1163 }; 1164 1165 i2c11: i2c@a94000 { 1166 compatible = "qcom,geni-i2c"; 1167 reg = <0x0 0x00a94000 0x0 0x4000>; 1168 clock-names = "se"; 1169 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1170 pinctrl-0 = <&qup_i2c11_data_clk>; 1171 pinctrl-names = "default"; 1172 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1176 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1177 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1178 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1179 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1180 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1181 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1182 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1183 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1184 dma-names = "tx", "rx"; 1185 1186 status = "disabled"; 1187 }; 1188 1189 spi11: spi@a94000 { 1190 compatible = "qcom,geni-spi"; 1191 reg = <0x0 0x00a94000 0x0 0x4000>; 1192 clock-names = "se"; 1193 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1194 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1195 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1196 pinctrl-names = "default"; 1197 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1198 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1199 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1200 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1201 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1202 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1203 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1204 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1205 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1206 dma-names = "tx", "rx"; 1207 #address-cells = <1>; 1208 #size-cells = <0>; 1209 1210 status = "disabled"; 1211 }; 1212 1213 uart11: serial@a94000 { 1214 compatible = "qcom,geni-debug-uart"; 1215 reg = <0x0 0x00a94000 0x0 0x4000>; 1216 clock-names = "se"; 1217 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1218 pinctrl-0 = <&qup_uart11_default>; 1219 pinctrl-names = "default"; 1220 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1221 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1222 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1223 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1224 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1225 interconnect-names = "qup-core", 1226 "qup-config"; 1227 1228 status = "disabled"; 1229 }; 1230 }; 1231 1232 config_noc: interconnect@1500000 { 1233 compatible = "qcom,sar2130p-config-noc"; 1234 reg = <0x0 0x01500000 0x0 0x10>; 1235 #interconnect-cells = <2>; 1236 qcom,bcm-voters = <&apps_bcm_voter>; 1237 }; 1238 1239 system_noc: interconnect@1680000 { 1240 compatible = "qcom,sar2130p-system-noc"; 1241 reg = <0x0 0x01680000 0x0 0x29080>; 1242 clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1243 #interconnect-cells = <2>; 1244 qcom,bcm-voters = <&apps_bcm_voter>; 1245 }; 1246 1247 pcie_noc: interconnect@16c0000 { 1248 compatible = "qcom,sar2130p-pcie-anoc"; 1249 reg = <0x0 0x016c0000 0x0 0xa080>; 1250 clocks = <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1251 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1252 #interconnect-cells = <2>; 1253 qcom,bcm-voters = <&apps_bcm_voter>; 1254 }; 1255 1256 mmss_noc: interconnect@1740000 { 1257 compatible = "qcom,sar2130p-mmss-noc"; 1258 reg = <0x0 0x01740000 0x0 0x1f100>; 1259 #interconnect-cells = <2>; 1260 qcom,bcm-voters = <&apps_bcm_voter>; 1261 }; 1262 1263 pcie0: pcie@1c00000 { 1264 device_type = "pci"; 1265 compatible = "qcom,sar2130p-pcie", "qcom,pcie-sm8550"; 1266 reg = <0x0 0x01c00000 0x0 0x3000>, 1267 <0x0 0x60000000 0x0 0xf1d>, 1268 <0x0 0x60000f20 0x0 0xa8>, 1269 <0x0 0x60001000 0x0 0x1000>, 1270 <0x0 0x60100000 0x0 0x100000>, 1271 <0x0 0x01c0c000 0x0 0x1000>; 1272 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1273 #address-cells = <3>; 1274 #size-cells = <2>; 1275 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1276 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1277 bus-range = <0x00 0xff>; 1278 1279 dma-coherent; 1280 1281 linux,pci-domain = <0>; 1282 num-lanes = <2>; 1283 1284 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1285 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1286 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1287 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1288 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1289 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1290 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1291 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1292 interrupt-names = "msi0", 1293 "msi1", 1294 "msi2", 1295 "msi3", 1296 "msi4", 1297 "msi5", 1298 "msi6", 1299 "msi7"; 1300 #interrupt-cells = <1>; 1301 interrupt-map-mask = <0 0 0 0x7>; 1302 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1303 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1304 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1305 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1306 1307 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1308 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1309 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1310 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1311 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1312 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 1313 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1314 clock-names = "aux", 1315 "cfg", 1316 "bus_master", 1317 "bus_slave", 1318 "slave_q2a", 1319 "ddrss_sf_tbu", 1320 "noc_aggr"; 1321 1322 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 1323 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1324 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1325 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; 1326 interconnect-names = "pcie-mem", "cpu-pcie"; 1327 1328 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1329 <0x100 &apps_smmu 0x1c01 0x1>; 1330 1331 resets = <&gcc GCC_PCIE_0_BCR>; 1332 reset-names = "pci"; 1333 1334 power-domains = <&gcc PCIE_0_GDSC>; 1335 1336 phys = <&pcie0_phy>; 1337 phy-names = "pciephy"; 1338 1339 status = "disabled"; 1340 1341 pcieport0: pcie@0 { 1342 device_type = "pci"; 1343 reg = <0x0 0x0 0x0 0x0 0x0>; 1344 bus-range = <0x01 0xff>; 1345 1346 #address-cells = <3>; 1347 #size-cells = <2>; 1348 ranges; 1349 }; 1350 }; 1351 1352 pcie0_phy: phy@1c06000 { 1353 compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy"; 1354 reg = <0x0 0x01c06000 0x0 0x2000>; 1355 1356 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1357 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1358 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 1359 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 1360 <&gcc GCC_PCIE_0_PIPE_CLK>; 1361 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1362 "pipe"; 1363 1364 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1365 reset-names = "phy"; 1366 1367 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1368 assigned-clock-rates = <100000000>; 1369 1370 power-domains = <&gcc PCIE_0_PHY_GDSC>; 1371 1372 #clock-cells = <0>; 1373 clock-output-names = "pcie0_pipe_clk"; 1374 1375 #phy-cells = <0>; 1376 1377 status = "disabled"; 1378 }; 1379 1380 pcie1: pcie@1c08000 { 1381 device_type = "pci"; 1382 compatible = "qcom,sar2130p-pcie", "qcom,pcie-sm8550"; 1383 reg = <0x0 0x01c08000 0x0 0x3000>, 1384 <0x0 0x40000000 0x0 0xf1d>, 1385 <0x0 0x40000f20 0x0 0xa8>, 1386 <0x0 0x40001000 0x0 0x1000>, 1387 <0x0 0x40100000 0x0 0x100000>, 1388 <0x0 0x01c0b000 0x0 0x1000>; 1389 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1390 #address-cells = <3>; 1391 #size-cells = <2>; 1392 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1393 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1394 bus-range = <0x00 0xff>; 1395 1396 dma-coherent; 1397 1398 linux,pci-domain = <1>; 1399 num-lanes = <2>; 1400 1401 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1402 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1403 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1409 interrupt-names = "msi0", 1410 "msi1", 1411 "msi2", 1412 "msi3", 1413 "msi4", 1414 "msi5", 1415 "msi6", 1416 "msi7"; 1417 #interrupt-cells = <1>; 1418 interrupt-map-mask = <0 0 0 0x7>; 1419 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1420 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1421 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1422 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1423 1424 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1425 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1426 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1427 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1428 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1429 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 1430 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1431 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>, 1432 <&gcc GCC_QMIP_PCIE_AHB_CLK>; 1433 clock-names = "aux", 1434 "cfg", 1435 "bus_master", 1436 "bus_slave", 1437 "slave_q2a", 1438 "ddrss_sf_tbu", 1439 "noc_aggr", 1440 "cnoc_sf_axi", 1441 "qmip_pcie_ahb"; 1442 1443 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1444 assigned-clock-rates = <19200000>; 1445 1446 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 1447 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1448 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1449 &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; 1450 interconnect-names = "pcie-mem", "cpu-pcie"; 1451 1452 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1453 <0x100 &apps_smmu 0x1e01 0x1>; 1454 1455 resets = <&gcc GCC_PCIE_1_BCR>, 1456 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 1457 reset-names = "pci", "link_down"; 1458 1459 power-domains = <&gcc PCIE_1_GDSC>; 1460 1461 phys = <&pcie1_phy>; 1462 phy-names = "pciephy"; 1463 1464 status = "disabled"; 1465 1466 pcie@0 { 1467 device_type = "pci"; 1468 reg = <0x0 0x0 0x0 0x0 0x0>; 1469 bus-range = <0x01 0xff>; 1470 1471 #address-cells = <3>; 1472 #size-cells = <2>; 1473 ranges; 1474 }; 1475 }; 1476 1477 pcie1_phy: phy@1c0e000 { 1478 compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy"; 1479 reg = <0x0 0x01c0e000 0x0 0x2000>; 1480 1481 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1482 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1483 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 1484 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 1485 <&gcc GCC_PCIE_1_PIPE_CLK>; 1486 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1487 "pipe"; 1488 1489 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1490 reset-names = "phy"; 1491 1492 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1493 assigned-clock-rates = <100000000>; 1494 1495 power-domains = <&gcc PCIE_1_PHY_GDSC>; 1496 1497 #clock-cells = <0>; 1498 clock-output-names = "pcie1_pipe_clk"; 1499 1500 #phy-cells = <0>; 1501 1502 status = "disabled"; 1503 }; 1504 1505 tcsr_mutex: hwlock@1f40000 { 1506 compatible = "qcom,tcsr-mutex"; 1507 reg = <0x0 0x01f40000 0x0 0x20000>; 1508 1509 #hwlock-cells = <1>; 1510 }; 1511 1512 tcsr: clock-controller@1fc0000 { 1513 compatible = "qcom,sar2130p-tcsr", "syscon"; 1514 reg = <0x0 0x01fc0000 0x0 0x30000>; 1515 clocks = <&rpmhcc RPMH_CXO_CLK>; 1516 #clock-cells = <1>; 1517 #reset-cells = <1>; 1518 }; 1519 1520 remoteproc_adsp: remoteproc@3000000 { 1521 compatible = "qcom,sar2130p-adsp-pas"; 1522 reg = <0x0 0x03000000 0x0 0x10000>; 1523 1524 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 1525 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1526 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1527 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1528 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1529 interrupt-names = "wdog", "fatal", "ready", 1530 "handover", "stop-ack"; 1531 1532 clocks = <&rpmhcc RPMH_CXO_CLK>; 1533 clock-names = "xo"; 1534 1535 power-domains = <&rpmhpd RPMHPD_LCX>, 1536 <&rpmhpd RPMHPD_LMX>; 1537 power-domain-names = "lcx", "lmx"; 1538 1539 memory-region = <&adsp_mem>; 1540 1541 qcom,qmp = <&aoss_qmp>; 1542 1543 qcom,smem-states = <&smp2p_adsp_out 0>; 1544 qcom,smem-state-names = "stop"; 1545 1546 status = "disabled"; 1547 1548 remoteproc_adsp_glink: glink-edge { 1549 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1550 IPCC_MPROC_SIGNAL_GLINK_QMP 1551 IRQ_TYPE_EDGE_RISING>; 1552 mboxes = <&ipcc IPCC_CLIENT_LPASS 1553 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1554 1555 label = "lpass"; 1556 qcom,remote-pid = <2>; 1557 1558 gpr { 1559 compatible = "qcom,gpr"; 1560 qcom,glink-channels = "adsp_apps"; 1561 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 1562 qcom,intents = <512 20>; 1563 #address-cells = <1>; 1564 #size-cells = <0>; 1565 1566 q6apm: service@1 { 1567 compatible = "qcom,q6apm"; 1568 reg = <GPR_APM_MODULE_IID>; 1569 #sound-dai-cells = <0>; 1570 qcom,protection-domain = "avs/audio", 1571 "msm/adsp/audio_pd"; 1572 1573 q6apmdai: dais { 1574 compatible = "qcom,q6apm-dais"; 1575 iommus = <&apps_smmu 0x1801 0x0>; 1576 }; 1577 1578 q6apmbedai: bedais { 1579 compatible = "qcom,q6apm-lpass-dais"; 1580 #sound-dai-cells = <1>; 1581 }; 1582 }; 1583 1584 q6prm: service@2 { 1585 compatible = "qcom,q6prm"; 1586 reg = <GPR_PRM_MODULE_IID>; 1587 qcom,protection-domain = "avs/audio", 1588 "msm/adsp/audio_pd"; 1589 1590 q6prmcc: clock-controller { 1591 compatible = "qcom,q6prm-lpass-clocks"; 1592 #clock-cells = <2>; 1593 }; 1594 }; 1595 }; 1596 1597 fastrpc { 1598 compatible = "qcom,fastrpc"; 1599 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1600 label = "adsp"; 1601 qcom,non-secure-domain; 1602 #address-cells = <1>; 1603 #size-cells = <0>; 1604 1605 compute-cb@3 { 1606 compatible = "qcom,fastrpc-compute-cb"; 1607 reg = <3>; 1608 iommus = <&apps_smmu 0x1803 0x0>; 1609 }; 1610 1611 compute-cb@4 { 1612 compatible = "qcom,fastrpc-compute-cb"; 1613 reg = <4>; 1614 iommus = <&apps_smmu 0x1804 0x0>; 1615 }; 1616 1617 compute-cb@5 { 1618 compatible = "qcom,fastrpc-compute-cb"; 1619 reg = <5>; 1620 iommus = <&apps_smmu 0x1805 0x0>; 1621 }; 1622 1623 compute-cb@6 { 1624 compatible = "qcom,fastrpc-compute-cb"; 1625 reg = <6>; 1626 iommus = <&apps_smmu 0x1806 0x0>; 1627 }; 1628 }; 1629 }; 1630 }; 1631 1632 gpu: gpu@3d00000 { 1633 compatible = "qcom,adreno-621.0", "qcom,adreno"; 1634 reg = <0x0 0x03d00000 0x0 0x40000>, 1635 <0x0 0x03d9e000 0x0 0x2000>, 1636 <0x0 0x03d61000 0x0 0x800>; 1637 reg-names = "kgsl_3d0_reg_memory", 1638 "cx_mem", 1639 "cx_dbgc"; 1640 1641 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1642 1643 iommus = <&adreno_smmu 0 0x401>; 1644 1645 operating-points-v2 = <&gpu_opp_table>; 1646 1647 qcom,gmu = <&gmu>; 1648 1649 nvmem-cells = <&gpu_speed_bin>; 1650 nvmem-cell-names = "speed_bin"; 1651 #cooling-cells = <2>; 1652 1653 status = "disabled"; 1654 1655 gpu_zap_shader: zap-shader { 1656 memory-region = <&gpu_micro_code_mem>; 1657 }; 1658 1659 gpu_opp_table: opp-table { 1660 compatible = "operating-points-v2"; 1661 1662 opp-843000000 { 1663 opp-hz = /bits/ 64 <843000000>; 1664 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1665 opp-supported-hw = <0x1>; 1666 }; 1667 1668 opp-780000000 { 1669 opp-hz = /bits/ 64 <780000000>; 1670 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1671 opp-supported-hw = <0x1>; 1672 }; 1673 1674 opp-644000000 { 1675 opp-hz = /bits/ 64 <644000000>; 1676 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1677 opp-supported-hw = <0x3>; 1678 }; 1679 1680 opp-570000000 { 1681 opp-hz = /bits/ 64 <570000000>; 1682 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1683 opp-supported-hw = <0x3>; 1684 }; 1685 1686 opp-450000000 { 1687 opp-hz = /bits/ 64 <450000000>; 1688 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1689 opp-supported-hw = <0x3>; 1690 }; 1691 1692 opp-320000000 { 1693 opp-hz = /bits/ 64 <320000000>; 1694 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1695 opp-supported-hw = <0x3>; 1696 }; 1697 1698 opp-235000000 { 1699 opp-hz = /bits/ 64 <235000000>; 1700 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 1701 opp-supported-hw = <0x3>; 1702 }; 1703 }; 1704 }; 1705 1706 gmu: gmu@3d6a000 { 1707 compatible = "qcom,adreno-gmu-621.0", "qcom,adreno-gmu"; 1708 reg = <0x0 0x03d6a000 0x0 0x35000>, 1709 <0x0 0x03de0000 0x0 0x10000>, 1710 <0x0 0x0b290000 0x0 0x10000>; 1711 reg-names = "gmu", "rscc", "gmu_pdc"; 1712 1713 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1714 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1715 interrupt-names = "hfi", "gmu"; 1716 1717 clocks = <&gpucc GPU_CC_AHB_CLK>, 1718 <&gpucc GPU_CC_CX_GMU_CLK>, 1719 <&gpucc GPU_CC_CXO_CLK>, 1720 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1721 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1722 <&gpucc GPU_CC_HUB_CX_INT_CLK>; 1723 clock-names = "ahb", 1724 "gmu", 1725 "cxo", 1726 "axi", 1727 "memnoc", 1728 "hub"; 1729 1730 power-domains = <&gpucc GPU_CX_GDSC>, 1731 <&gpucc GPU_GX_GDSC>; 1732 power-domain-names = "cx", 1733 "gx"; 1734 1735 iommus = <&adreno_smmu 5 0x400>; 1736 1737 qcom,qmp = <&aoss_qmp>; 1738 1739 operating-points-v2 = <&gmu_opp_table>; 1740 1741 gmu_opp_table: opp-table { 1742 compatible = "operating-points-v2"; 1743 1744 opp-220000000 { 1745 opp-hz = /bits/ 64 <220000000>; 1746 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1747 }; 1748 1749 opp-550000000 { 1750 opp-hz = /bits/ 64 <550000000>; 1751 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1752 }; 1753 }; 1754 }; 1755 1756 gpucc: clock-controller@3d90000 { 1757 compatible = "qcom,sar2130p-gpucc"; 1758 reg = <0x0 0x03d90000 0x0 0xa000>; 1759 1760 clocks = <&rpmhcc RPMH_CXO_CLK>, 1761 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1762 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1763 1764 #clock-cells = <1>; 1765 #reset-cells = <1>; 1766 #power-domain-cells = <1>; 1767 }; 1768 1769 adreno_smmu: iommu@3da0000 { 1770 compatible = "qcom,sar2130p-smmu-500", "qcom,adreno-smmu", 1771 "qcom,smmu-500", "arm,mmu-500"; 1772 reg = <0x0 0x03da0000 0x0 0x10000>; 1773 #iommu-cells = <2>; 1774 #global-interrupts = <1>; 1775 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 1784 1785 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1786 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1787 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1788 <&gpucc GPU_CC_AHB_CLK>; 1789 clock-names = "hlos", 1790 "bus", 1791 "iface", 1792 "ahb"; 1793 power-domains = <&gpucc GPU_CX_GDSC>; 1794 dma-coherent; 1795 }; 1796 1797 usb_1_hsphy: phy@88e3000 { 1798 compatible = "qcom,sar2130p-snps-eusb2-phy", 1799 "qcom,sm8550-snps-eusb2-phy"; 1800 reg = <0x0 0x088e3000 0x0 0x154>; 1801 #phy-cells = <0>; 1802 1803 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 1804 clock-names = "ref"; 1805 1806 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1807 1808 status = "disabled"; 1809 }; 1810 1811 usb_dp_qmpphy: phy@88e8000 { 1812 compatible = "qcom,sar2130p-qmp-usb3-dp-phy"; 1813 reg = <0x0 0x088e8000 0x0 0x3000>; 1814 1815 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1816 <&rpmhcc RPMH_CXO_CLK>, 1817 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 1818 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1819 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 1820 1821 power-domains = <&gcc USB3_PHY_GDSC>; 1822 1823 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 1824 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 1825 reset-names = "phy", "common"; 1826 1827 #clock-cells = <1>; 1828 #phy-cells = <1>; 1829 1830 orientation-switch; 1831 1832 status = "disabled"; 1833 1834 ports { 1835 #address-cells = <1>; 1836 #size-cells = <0>; 1837 1838 port@0 { 1839 reg = <0>; 1840 1841 usb_dp_qmpphy_out: endpoint { 1842 }; 1843 }; 1844 1845 port@1 { 1846 reg = <1>; 1847 1848 usb_dp_qmpphy_usb_ss_in: endpoint { 1849 remote-endpoint = <&usb_1_dwc3_ss>; 1850 }; 1851 }; 1852 1853 port@2 { 1854 reg = <2>; 1855 1856 usb_dp_qmpphy_dp_in: endpoint { 1857 }; 1858 }; 1859 }; 1860 }; 1861 1862 usb_1: usb@a6f8800 { 1863 compatible = "qcom,sar2130p-dwc3", "qcom,dwc3"; 1864 reg = <0x0 0x0a6f8800 0x0 0x400>; 1865 #address-cells = <2>; 1866 #size-cells = <2>; 1867 ranges; 1868 1869 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1870 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1871 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1872 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1873 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1874 <&tcsr TCSR_USB3_CLKREF_EN>; 1875 clock-names = "cfg_noc", 1876 "core", 1877 "iface", 1878 "sleep", 1879 "mock_utmi", 1880 "xo"; 1881 1882 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1883 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1884 assigned-clock-rates = <19200000>, <200000000>; 1885 1886 interrupts-extended = <&intc GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1887 <&intc GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1888 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1889 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1890 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 1891 interrupt-names = "pwr_event", 1892 "hs_phy_irq", 1893 "dp_hs_phy_irq", 1894 "dm_hs_phy_irq", 1895 "ss_phy_irq"; 1896 1897 power-domains = <&gcc USB30_PRIM_GDSC>; 1898 required-opps = <&rpmhpd_opp_nom>; 1899 1900 resets = <&gcc GCC_USB30_PRIM_BCR>; 1901 1902 interconnects = <&system_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 1903 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1904 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1905 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; 1906 interconnect-names = "usb-ddr", "apps-usb"; 1907 1908 status = "disabled"; 1909 1910 usb_1_dwc3: usb@a600000 { 1911 compatible = "snps,dwc3"; 1912 reg = <0x0 0x0a600000 0x0 0xcd00>; 1913 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 1914 iommus = <&apps_smmu 0x20 0x0>; 1915 phys = <&usb_1_hsphy>, 1916 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 1917 phy-names = "usb2-phy", "usb3-phy"; 1918 1919 snps,has-lpm-erratum; 1920 snps,hird-threshold = /bits/ 8 <0x0>; 1921 snps,is-utmi-l1-suspend; 1922 snps,dis-u1-entry-quirk; 1923 snps,dis-u2-entry-quirk; 1924 snps,dis_u2_susphy_quirk; 1925 snps,dis_u3_susphy_quirk; 1926 snps,parkmode-disable-ss-quirk; 1927 1928 tx-fifo-resize; 1929 dma-coherent; 1930 usb-role-switch; 1931 1932 ports { 1933 #address-cells = <1>; 1934 #size-cells = <0>; 1935 1936 port@0 { 1937 reg = <0>; 1938 1939 usb_1_dwc3_hs: endpoint { 1940 }; 1941 }; 1942 1943 port@1 { 1944 reg = <1>; 1945 1946 usb_1_dwc3_ss: endpoint { 1947 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 1948 }; 1949 }; 1950 }; 1951 }; 1952 }; 1953 1954 pdc: interrupt-controller@b220000 { 1955 compatible = "qcom,sar2130p-pdc", "qcom,pdc"; 1956 reg = <0x0 0x0b220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; 1957 qcom,pdc-ranges = <0 480 94>, 1958 <94 609 31>, 1959 <125 63 1>, 1960 <126 716 12>; 1961 #interrupt-cells = <2>; 1962 interrupt-parent = <&intc>; 1963 interrupt-controller; 1964 }; 1965 1966 aoss_qmp: power-management@c300000 { 1967 compatible = "qcom,sar2130p-aoss-qmp", "qcom,aoss-qmp"; 1968 reg = <0x0 0x0c300000 0x0 0x400>; 1969 interrupt-parent = <&ipcc>; 1970 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 1971 IRQ_TYPE_EDGE_RISING>; 1972 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 1973 1974 #clock-cells = <0>; 1975 }; 1976 1977 tsens0: thermal-sensor@c263000 { 1978 compatible = "qcom,sar2130p-tsens", "qcom,tsens-v2"; 1979 reg = <0x0 0x0c263000 0x0 0x1000>, /* TM */ 1980 <0x0 0x0c222000 0x0 0x1000>; /* SROT */ 1981 #qcom,sensors = <16>; 1982 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 1983 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1984 interrupt-names = "uplow", "critical"; 1985 #thermal-sensor-cells = <1>; 1986 }; 1987 1988 sram@c3f0000 { 1989 compatible = "qcom,rpmh-stats"; 1990 reg = <0x0 0x0c3f0000 0x0 0x400>; 1991 }; 1992 1993 arbiter@c400000 { 1994 compatible = "qcom,sar2130p-spmi-pmic-arb", 1995 "qcom,x1e80100-spmi-pmic-arb"; 1996 reg = <0x0 0x0c400000 0x0 0x3000>, 1997 <0x0 0x0c500000 0x0 0x400000>, 1998 <0x0 0x0c440000 0x0 0x80000>; 1999 reg-names = "core", "chnls", "obsrvr"; 2000 2001 qcom,ee = <0>; 2002 qcom,channel = <0>; 2003 2004 #address-cells = <2>; 2005 #size-cells = <2>; 2006 ranges; 2007 2008 spmi_bus: spmi@c42d000 { 2009 reg = <0x0 0x0c42d000 0x0 0x4000>, 2010 <0x0 0x0c4c0000 0x0 0x10000>; 2011 reg-names = "cnfg", "intr"; 2012 2013 interrupt-names = "periph_irq"; 2014 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2015 interrupt-controller; 2016 #interrupt-cells = <4>; 2017 2018 #address-cells = <2>; 2019 #size-cells = <0>; 2020 }; 2021 }; 2022 2023 ipcc: mailbox@ed18000 { 2024 compatible = "qcom,sar2130p-ipcc", "qcom,ipcc"; 2025 reg = <0x0 0x0ed18000 0x0 0x1000>; 2026 2027 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 2028 interrupt-controller; 2029 #interrupt-cells = <3>; 2030 2031 #mbox-cells = <2>; 2032 }; 2033 2034 tlmm: pinctrl@f100000 { 2035 compatible = "qcom,sar2130p-tlmm"; 2036 reg = <0x0 0x0f100000 0x0 0x300000>; 2037 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2038 gpio-controller; 2039 #gpio-cells = <2>; 2040 interrupt-controller; 2041 #interrupt-cells = <2>; 2042 gpio-ranges = <&tlmm 0 0 156>; 2043 wakeup-parent = <&pdc>; 2044 2045 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 2046 /* SDA, SCL */ 2047 pins = "gpio0", "gpio1"; 2048 function = "qup0"; 2049 drive-strength = <2>; 2050 bias-pull-up; 2051 }; 2052 2053 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 2054 /* SDA, SCL */ 2055 pins = "gpio2", "gpio3"; 2056 function = "qup1"; 2057 drive-strength = <2>; 2058 bias-pull-up; 2059 }; 2060 2061 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 2062 /* SDA, SCL */ 2063 pins = "gpio22", "gpio23"; 2064 function = "qup2"; 2065 drive-strength = <2>; 2066 bias-pull-up; 2067 }; 2068 2069 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 2070 /* SDA, SCL */ 2071 pins = "gpio16", "gpio17"; 2072 function = "qup3"; 2073 drive-strength = <2>; 2074 bias-pull-up; 2075 }; 2076 2077 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 2078 /* SDA, SCL */ 2079 pins = "gpio20", "gpio21"; 2080 function = "qup4"; 2081 drive-strength = <2>; 2082 bias-pull-up; 2083 }; 2084 2085 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 2086 /* SDA, SCL */ 2087 pins = "gpio95", "gpio96"; 2088 function = "qup5"; 2089 drive-strength = <2>; 2090 bias-pull-up; 2091 }; 2092 2093 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 2094 /* SDA, SCL */ 2095 pins = "gpio91", "gpio92"; 2096 function = "qup6"; 2097 drive-strength = <2>; 2098 bias-pull-up; 2099 }; 2100 2101 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 2102 /* SDA, SCL */ 2103 pins = "gpio8", "gpio9"; 2104 function = "qup7"; 2105 drive-strength = <2>; 2106 bias-pull-up; 2107 }; 2108 2109 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 2110 /* SDA, SCL */ 2111 pins = "gpio8", "gpio9"; 2112 function = "qup8"; 2113 drive-strength = <2>; 2114 bias-pull-up; 2115 }; 2116 2117 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 2118 /* SDA, SCL */ 2119 pins = "gpio109", "gpio110"; 2120 function = "qup9"; 2121 drive-strength = <2>; 2122 bias-pull-up; 2123 }; 2124 2125 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 2126 /* SDA, SCL */ 2127 pins = "gpio4", "gpio5"; 2128 function = "qup10"; 2129 drive-strength = <2>; 2130 bias-pull-up; 2131 }; 2132 2133 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 2134 /* SDA, SCL */ 2135 pins = "gpio28", "gpio30"; 2136 function = "qup11"; 2137 drive-strength = <2>; 2138 bias-pull-up; 2139 }; 2140 2141 qup_spi0_cs0: qup-spi0-cs0-state { 2142 pins = "gpio3"; 2143 function = "qup0"; 2144 drive-strength = <2>; 2145 bias-disable; 2146 }; 2147 2148 qup_spi0_cs1: qup-spi0-cs1-state { 2149 pins = "gpio93"; 2150 function = "qup0"; 2151 drive-strength = <2>; 2152 bias-disable; 2153 }; 2154 2155 qup_spi0_data_clk: qup-spi0-data-clk-state { 2156 /* MISO, MOSI, CLK */ 2157 pins = "gpio0", "gpio1", "gpio2"; 2158 function = "qup0"; 2159 drive-strength = <2>; 2160 bias-disable; 2161 }; 2162 2163 qup_spi1_cs: qup-spi1-cs-state { 2164 pins = "gpio62"; 2165 function = "qup1"; 2166 drive-strength = <2>; 2167 bias-disable; 2168 }; 2169 2170 qup_spi1_data_clk: qup-spi1-data-clk-state { 2171 /* MISO, MOSI, CLK */ 2172 pins = "gpio2", "gpio3", "gpio61"; 2173 function = "qup1"; 2174 drive-strength = <2>; 2175 bias-disable; 2176 }; 2177 2178 qup_spi2_cs: qup-spi2-cs-state { 2179 pins = "gpio13"; 2180 function = "qup2"; 2181 drive-strength = <2>; 2182 bias-disable; 2183 }; 2184 2185 qup_spi2_data_clk: qup-spi2-data-clk-state { 2186 /* MISO, MOSI, CLK */ 2187 pins = "gpio22", "gpio23", "gpio12"; 2188 function = "qup2"; 2189 drive-strength = <2>; 2190 bias-disable; 2191 }; 2192 2193 qup_spi3_cs0: qup-spi3-cs0-state { 2194 pins = "gpio19"; 2195 function = "qup3"; 2196 drive-strength = <2>; 2197 bias-disable; 2198 }; 2199 2200 qup_spi3_cs1: qup-spi3-cs1-state { 2201 pins = "gpio41"; 2202 function = "qup3"; 2203 drive-strength = <2>; 2204 bias-disable; 2205 }; 2206 2207 qup_spi3_data_clk: qup-spi3-data-clk-state { 2208 /* MISO, MOSI, CLK */ 2209 pins = "gpio16", "gpio17", "gpio18"; 2210 function = "qup3"; 2211 drive-strength = <2>; 2212 bias-disable; 2213 }; 2214 2215 qup_spi4_cs0: qup-spi4-cs0-state { 2216 pins = "gpio23"; 2217 function = "qup4"; 2218 drive-strength = <2>; 2219 bias-disable; 2220 }; 2221 2222 qup_spi4_cs1: qup-spi4-cs1-state { 2223 pins = "gpio94"; 2224 function = "qup4"; 2225 drive-strength = <2>; 2226 bias-disable; 2227 }; 2228 2229 qup_spi4_data_clk: qup-spi4-data-clk-state { 2230 /* MISO, MOSI, CLK */ 2231 pins = "gpio20", "gpio21", "gpio22"; 2232 function = "qup4"; 2233 drive-strength = <2>; 2234 bias-disable; 2235 }; 2236 2237 qup_spi5_cs: qup-spi5-cs-state { 2238 pins = "gpio98"; 2239 function = "qup5"; 2240 drive-strength = <2>; 2241 bias-disable; 2242 }; 2243 2244 qup_spi5_data_clk: qup-spi5-data-clk-state { 2245 /* MISO, MOSI, CLK */ 2246 pins = "gpio95", "gpio96", "gpio97"; 2247 function = "qup5"; 2248 drive-strength = <2>; 2249 bias-disable; 2250 }; 2251 2252 qup_spi6_cs: qup-spi6-cs-state { 2253 pins = "gpio63"; 2254 function = "qup6"; 2255 drive-strength = <2>; 2256 bias-disable; 2257 }; 2258 2259 qup_spi6_data_clk: qup-spi6-data-clk-state { 2260 /* MISO, MOSI, CLK */ 2261 pins = "gpio91", "gpio92", "gpio64"; 2262 function = "qup6"; 2263 drive-strength = <2>; 2264 bias-disable; 2265 }; 2266 2267 qup_spi7_cs: qup-spi7-cs-state { 2268 pins = "gpio27"; 2269 function = "qup7"; 2270 drive-strength = <2>; 2271 bias-disable; 2272 }; 2273 2274 qup_spi7_data_clk: qup-spi7-data-clk-state { 2275 /* MISO, MOSI, CLK */ 2276 pins = "gpio24", "gpio25", "gpio26"; 2277 function = "qup7"; 2278 drive-strength = <2>; 2279 bias-disable; 2280 }; 2281 2282 qup_spi8_cs: qup-spi8-cs-state { 2283 pins = "gpio11"; 2284 function = "qup8"; 2285 drive-strength = <2>; 2286 bias-disable; 2287 }; 2288 2289 qup_spi8_data_clk: qup-spi8-data-clk-state { 2290 /* MISO, MOSI, CLK */ 2291 pins = "gpio8", "gpio9", "gpio10"; 2292 function = "qup8"; 2293 drive-strength = <2>; 2294 bias-disable; 2295 }; 2296 2297 qup_spi9_cs: qup-spi9-cs-state { 2298 pins = "gpio35"; 2299 function = "qup9"; 2300 drive-strength = <2>; 2301 bias-disable; 2302 }; 2303 2304 qup_spi9_data_clk: qup-spi9-data-clk-state { 2305 /* MISO, MOSI, CLK */ 2306 pins = "gpio109", "gpio110", "gpio34"; 2307 function = "qup9"; 2308 drive-strength = <2>; 2309 bias-disable; 2310 }; 2311 2312 qup_spi10_cs: qup-spi10-cs-state { 2313 pins = "gpio7"; 2314 function = "qup10"; 2315 drive-strength = <2>; 2316 bias-disable; 2317 }; 2318 2319 qup_spi10_data_clk: qup-spi10-data-clk-state { 2320 /* MISO, MOSI, CLK */ 2321 pins = "gpio4", "gpio5", "gpio6"; 2322 function = "qup10"; 2323 drive-strength = <2>; 2324 bias-disable; 2325 }; 2326 2327 qup_spi11_cs: qup-spi11-cs-state { 2328 pins = "gpio15"; 2329 function = "qup11"; 2330 drive-strength = <2>; 2331 bias-disable; 2332 }; 2333 2334 qup_spi11_data_clk: qup-spi11-data-clk-state { 2335 /* MISO, MOSI, CLK */ 2336 pins = "gpio28", "gpio30", "gpio14"; 2337 function = "qup11"; 2338 drive-strength = <2>; 2339 bias-disable; 2340 }; 2341 2342 qup_uart7_default: qup-uart7-default-state { 2343 cts-pins { 2344 pins = "gpio24"; 2345 function = "qup7"; 2346 drive-strength = <2>; 2347 bias-disable; 2348 }; 2349 2350 rts-pins { 2351 pins = "gpio25"; 2352 function = "qup7"; 2353 drive-strength = <2>; 2354 bias-pull-down; 2355 }; 2356 2357 rx-pins { 2358 pins = "gpio27"; 2359 function = "qup7"; 2360 drive-strength = <2>; 2361 bias-pull-down; 2362 }; 2363 2364 tx-pins { 2365 pins = "gpio26"; 2366 function = "qup7"; 2367 drive-strength = <2>; 2368 bias-pull-up; 2369 }; 2370 }; 2371 2372 qup_uart11_default: qup-uart11-default-state { 2373 pins = "gpio14", "gpio15"; 2374 function = "qup11"; 2375 drive-strength = <2>; 2376 bias-disable; 2377 }; 2378 2379 sdc1_default: sdc1-default-state { 2380 clk-pins { 2381 pins = "sdc1_clk"; 2382 drive-strength = <16>; 2383 bias-disable; 2384 }; 2385 2386 cmd-pins { 2387 pins = "sdc1_cmd"; 2388 drive-strength = <10>; 2389 bias-pull-up; 2390 }; 2391 2392 data-pins { 2393 pins = "sdc1_data"; 2394 drive-strength = <10>; 2395 bias-pull-up; 2396 }; 2397 2398 rclk-pins { 2399 pins = "sdc1_rclk"; 2400 bias-pull-down; 2401 }; 2402 }; 2403 2404 sdc1_sleep: sdc1-sleep-state { 2405 clk-pins { 2406 pins = "sdc1_clk"; 2407 drive-strength = <2>; 2408 bias-disable; 2409 }; 2410 2411 cmd-pins { 2412 pins = "sdc1_cmd"; 2413 drive-strength = <2>; 2414 bias-pull-up; 2415 }; 2416 2417 data-pins { 2418 pins = "sdc1_data"; 2419 drive-strength = <2>; 2420 bias-pull-up; 2421 }; 2422 2423 rclk-pins { 2424 pins = "sdc1_rclk"; 2425 bias-pull-down; 2426 }; 2427 }; 2428 }; 2429 2430 apps_smmu: iommu@15000000 { 2431 compatible = "qcom,sar2130p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2432 reg = <0x0 0x15000000 0x0 0x100000>; 2433 #iommu-cells = <2>; 2434 #global-interrupts = <1>; 2435 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2436 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2437 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2438 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2439 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2440 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2441 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2442 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2443 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2444 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2445 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2446 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2447 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2448 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2449 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2450 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2451 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2452 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2453 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2454 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2455 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2456 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2457 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2458 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2459 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2460 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2461 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2462 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2463 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2464 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2465 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2466 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2467 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2468 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2469 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2470 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2471 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2472 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2473 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2474 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2475 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2476 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2477 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2478 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2479 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2480 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2481 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2482 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2483 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2484 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2485 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2486 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2487 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2488 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2489 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2490 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2491 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2492 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2493 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2494 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2495 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2496 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2497 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2498 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2499 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2500 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2501 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2502 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2503 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2504 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2505 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2506 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2507 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2508 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2509 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2510 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2511 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2512 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2513 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2514 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 2515 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 2516 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2517 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 2518 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 2519 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2520 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 2521 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2522 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2523 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 2524 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 2525 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 2526 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 2527 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 2528 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 2529 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 2530 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 2531 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 2532 dma-coherent; 2533 }; 2534 2535 intc: interrupt-controller@17200000 { 2536 compatible = "arm,gic-v3"; 2537 #interrupt-cells = <3>; 2538 interrupt-controller; 2539 #redistributor-regions = <1>; 2540 redistributor-stride = <0x0 0x20000>; 2541 reg = <0x0 0x17200000 0x0 0x10000>, 2542 <0x0 0x17260000 0x0 0x100000>; 2543 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2544 #address-cells = <2>; 2545 #size-cells = <2>; 2546 ranges; 2547 2548 gic_its: msi-controller@17240000 { 2549 compatible = "arm,gic-v3-its"; 2550 reg = <0x0 0x17240000 0x0 0x20000>; 2551 msi-controller; 2552 #msi-cells = <1>; 2553 }; 2554 }; 2555 2556 apps_rsc: rsc@17a00000 { 2557 label = "apps_rsc"; 2558 compatible = "qcom,rpmh-rsc"; 2559 reg = <0x0 0x17a00000 0x0 0x10000>, 2560 <0x0 0x17a10000 0x0 0x10000>, 2561 <0x0 0x17a20000 0x0 0x10000>; 2562 reg-names = "drv-0", "drv-1", "drv-2"; 2563 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2564 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2565 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2566 qcom,tcs-offset = <0xd00>; 2567 qcom,drv-id = <2>; 2568 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 2569 <WAKE_TCS 2>, <CONTROL_TCS 0>; 2570 power-domains = <&cluster_pd>; 2571 2572 apps_bcm_voter: bcm-voter { 2573 compatible = "qcom,bcm-voter"; 2574 }; 2575 2576 rpmhcc: clock-controller { 2577 compatible = "qcom,sar2130p-rpmh-clk"; 2578 #clock-cells = <1>; 2579 clock-names = "xo"; 2580 clocks = <&xo_board>; 2581 }; 2582 2583 rpmhpd: power-controller { 2584 compatible = "qcom,sar2130p-rpmhpd"; 2585 #power-domain-cells = <1>; 2586 operating-points-v2 = <&rpmhpd_opp_table>; 2587 2588 rpmhpd_opp_table: opp-table { 2589 compatible = "operating-points-v2"; 2590 2591 rpmhpd_opp_ret: opp1 { 2592 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2593 }; 2594 2595 rpmhpd_opp_min_svs: opp2 { 2596 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2597 }; 2598 2599 rpmhpd_opp_low_svs_d1: opp3 { 2600 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2601 }; 2602 2603 rpmhpd_opp_low_svs: opp4 { 2604 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2605 }; 2606 2607 rpmhpd_opp_svs: opp5 { 2608 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2609 }; 2610 2611 rpmhpd_opp_svs_l1: opp6 { 2612 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2613 }; 2614 2615 rpmhpd_opp_nom: opp7 { 2616 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2617 }; 2618 2619 rpmhpd_opp_turbo: opp8 { 2620 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2621 }; 2622 2623 rpmhpd_opp_turbo_l1: opp9 { 2624 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2625 }; 2626 }; 2627 }; 2628 }; 2629 2630 cpufreq_hw: cpufreq@17d91000 { 2631 compatible = "qcom,sar2130p-cpufreq-epss", "qcom,cpufreq-epss"; 2632 reg = <0x0 0x17d91000 0x0 0x1000>; 2633 reg-names = "freq-domain0"; 2634 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 2635 clock-names = "xo", "alternate"; 2636 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2637 interrupt-names = "dcvsh-irq-0"; 2638 #freq-domain-cells = <1>; 2639 #clock-cells = <1>; 2640 }; 2641 2642 gem_noc: interconnect@19100000 { 2643 compatible = "qcom,sar2130p-gem-noc"; 2644 reg = <0x0 0x19100000 0x0 0xa2080>; 2645 #interconnect-cells = <2>; 2646 qcom,bcm-voters = <&apps_bcm_voter>; 2647 }; 2648 2649 /* 2650 * Bootloader expects just cache-controller node instead of 2651 * the typical system-cache-controller 2652 */ 2653 llcc: cache-controller@19200000 { 2654 compatible = "qcom,sar2130p-llcc"; 2655 reg = <0x0 0x19200000 0x0 0x80000>, 2656 <0x0 0x19300000 0x0 0x80000>, 2657 <0x0 0x19a00000 0x0 0x80000>, 2658 <0x0 0x19c00000 0x0 0x80000>, 2659 <0x0 0x19af0000 0x0 0x80000>, 2660 <0x0 0x19cf0000 0x0 0x80000>; 2661 reg-names = "llcc0_base", 2662 "llcc1_base", 2663 "llcc_broadcast_base", 2664 "llcc_broadcast_and_base", 2665 "llcc_scratchpad_broadcast_base", 2666 "llcc_scratchpad_broadcast_and_base"; 2667 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 2668 }; 2669 2670 qfprom: qfprom@221c8000 { 2671 compatible = "qcom,sar2130p-qfprom", "qcom,qfprom"; 2672 reg = <0x0 0x221c8000 0x0 0x1000>; 2673 #address-cells = <1>; 2674 #size-cells = <1>; 2675 read-only; 2676 2677 gpu_speed_bin: gpu-speed-bin@119 { 2678 reg = <0x119 0x2>; 2679 bits = <5 8>; 2680 }; 2681 }; 2682 2683 nsp_noc: interconnect@320c0000 { 2684 compatible = "qcom,sar2130p-nsp-noc"; 2685 reg = <0x0 0x320c0000 0x0 0x10>; 2686 #interconnect-cells = <2>; 2687 qcom,bcm-voters = <&apps_bcm_voter>; 2688 }; 2689 2690 lpass_ag_noc: interconnect@3c40000 { 2691 compatible = "qcom,sar2130p-lpass-ag-noc"; 2692 reg = <0x0 0x3c40000 0x0 0x10>; 2693 #interconnect-cells = <1>; 2694 qcom,bcm-voters = <&apps_bcm_voter>; 2695 }; 2696 }; 2697 2698 timer { 2699 compatible = "arm,armv8-timer"; 2700 2701 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 2702 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 2703 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 2704 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 2705 }; 2706 2707 thermal-zones { 2708 aoss0-thermal { 2709 thermal-sensors = <&tsens0 0>; 2710 2711 trips { 2712 trip-point0 { 2713 temperature = <115000>; 2714 hysteresis = <5000>; 2715 type = "hot"; 2716 }; 2717 2718 aoss0-critical { 2719 temperature = <125000>; 2720 hysteresis = <0>; 2721 type = "critical"; 2722 }; 2723 2724 }; 2725 }; 2726 2727 cpu0-thermal { 2728 thermal-sensors = <&tsens0 1>; 2729 2730 trips { 2731 cpu0_alert0: trip-point0 { 2732 temperature = <110000>; 2733 hysteresis = <10000>; 2734 type = "passive"; 2735 }; 2736 2737 cpu0_alert1: trip-point1 { 2738 temperature = <115000>; 2739 hysteresis = <5000>; 2740 type = "passive"; 2741 }; 2742 2743 cpu0-critical { 2744 temperature = <125000>; 2745 hysteresis = <1000>; 2746 type = "critical"; 2747 }; 2748 }; 2749 2750 cooling-maps { 2751 map0 { 2752 trip = <&cpu0_alert0>; 2753 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2754 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2755 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2756 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2757 }; 2758 2759 map1 { 2760 trip = <&cpu0_alert1>; 2761 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2762 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2763 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2764 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2765 }; 2766 }; 2767 }; 2768 2769 cpu1-thermal { 2770 thermal-sensors = <&tsens0 2>; 2771 2772 trips { 2773 cpu1_alert0: trip-point0 { 2774 temperature = <110000>; 2775 hysteresis = <10000>; 2776 type = "passive"; 2777 }; 2778 2779 cpu1_alert1: trip-point1 { 2780 temperature = <115000>; 2781 hysteresis = <5000>; 2782 type = "passive"; 2783 }; 2784 2785 cpu1-critical { 2786 temperature = <125000>; 2787 hysteresis = <1000>; 2788 type = "critical"; 2789 }; 2790 }; 2791 2792 cooling-maps { 2793 map0 { 2794 trip = <&cpu1_alert0>; 2795 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2796 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2797 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2798 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2799 }; 2800 2801 map1 { 2802 trip = <&cpu1_alert1>; 2803 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2804 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2805 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2806 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2807 }; 2808 }; 2809 }; 2810 2811 cpu2-thermal { 2812 thermal-sensors = <&tsens0 3>; 2813 2814 trips { 2815 cpu2_alert0: trip-point0 { 2816 temperature = <110000>; 2817 hysteresis = <10000>; 2818 type = "passive"; 2819 }; 2820 2821 cpu2_alert1: trip-point1 { 2822 temperature = <115000>; 2823 hysteresis = <5000>; 2824 type = "passive"; 2825 }; 2826 2827 cpu2-critical { 2828 temperature = <125000>; 2829 hysteresis = <1000>; 2830 type = "critical"; 2831 }; 2832 }; 2833 2834 cooling-maps { 2835 map0 { 2836 trip = <&cpu2_alert0>; 2837 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2838 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2839 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2840 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2841 }; 2842 2843 map1 { 2844 trip = <&cpu2_alert1>; 2845 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2846 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2847 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2848 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2849 }; 2850 }; 2851 }; 2852 2853 cpu3-thermal { 2854 thermal-sensors = <&tsens0 4>; 2855 2856 trips { 2857 cpu3_alert0: trip-point0 { 2858 temperature = <110000>; 2859 hysteresis = <10000>; 2860 type = "passive"; 2861 }; 2862 2863 cpu3_alert1: rip-point1 { 2864 temperature = <115000>; 2865 hysteresis = <5000>; 2866 type = "passive"; 2867 }; 2868 2869 cpu3-critical { 2870 temperature = <125000>; 2871 hysteresis = <1000>; 2872 type = "critical"; 2873 }; 2874 }; 2875 2876 cooling-maps { 2877 map0 { 2878 trip = <&cpu3_alert0>; 2879 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2880 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2881 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2882 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2883 }; 2884 2885 map1 { 2886 trip = <&cpu3_alert1>; 2887 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2888 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2889 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2890 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2891 }; 2892 }; 2893 }; 2894 2895 gpuss0-thermal { 2896 polling-delay-passive = <250>; 2897 2898 thermal-sensors = <&tsens0 5>; 2899 2900 cooling-maps { 2901 map0 { 2902 trip = <&gpu0_alert0>; 2903 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2904 }; 2905 }; 2906 2907 trips { 2908 gpu0_alert0: trip-point0 { 2909 temperature = <85000>; 2910 hysteresis = <1000>; 2911 type = "passive"; 2912 }; 2913 2914 trip-point1 { 2915 temperature = <90000>; 2916 hysteresis = <1000>; 2917 type = "hot"; 2918 }; 2919 2920 trip-point2 { 2921 temperature = <115000>; 2922 hysteresis = <1000>; 2923 type = "critical"; 2924 }; 2925 }; 2926 }; 2927 2928 gpuss1-thermal { 2929 polling-delay-passive = <250>; 2930 2931 thermal-sensors = <&tsens0 6>; 2932 2933 cooling-maps { 2934 map0 { 2935 trip = <&gpu1_alert0>; 2936 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2937 }; 2938 }; 2939 2940 trips { 2941 gpu1_alert0: trip-point0 { 2942 temperature = <85000>; 2943 hysteresis = <1000>; 2944 type = "passive"; 2945 }; 2946 2947 trip-point1 { 2948 temperature = <90000>; 2949 hysteresis = <1000>; 2950 type = "hot"; 2951 }; 2952 2953 trip-point2 { 2954 temperature = <115000>; 2955 hysteresis = <1000>; 2956 type = "critical"; 2957 }; 2958 }; 2959 }; 2960 2961 nspss0-thermal { 2962 thermal-sensors = <&tsens0 7>; 2963 2964 trips { 2965 trip-point0 { 2966 temperature = <95000>; 2967 hysteresis = <5000>; 2968 type = "hot"; 2969 }; 2970 2971 trip-point1 { 2972 temperature = <115000>; 2973 hysteresis = <5000>; 2974 type = "hot"; 2975 }; 2976 2977 nspss1-critical { 2978 temperature = <125000>; 2979 hysteresis = <1000>; 2980 type = "critical"; 2981 }; 2982 }; 2983 }; 2984 2985 nspss1-thermal { 2986 thermal-sensors = <&tsens0 8>; 2987 2988 trips { 2989 trip-point0 { 2990 temperature = <95000>; 2991 hysteresis = <5000>; 2992 type = "hot"; 2993 }; 2994 2995 trip-point1 { 2996 temperature = <115000>; 2997 hysteresis = <5000>; 2998 type = "hot"; 2999 }; 3000 3001 nspss2-critical { 3002 temperature = <125000>; 3003 hysteresis = <1000>; 3004 type = "critical"; 3005 }; 3006 }; 3007 }; 3008 3009 nspss2-thermal { 3010 thermal-sensors = <&tsens0 9>; 3011 3012 trips { 3013 trip-point0 { 3014 temperature = <95000>; 3015 hysteresis = <5000>; 3016 type = "hot"; 3017 }; 3018 3019 trip-point1 { 3020 temperature = <115000>; 3021 hysteresis = <5000>; 3022 type = "hot"; 3023 }; 3024 3025 nspss2-critical { 3026 temperature = <125000>; 3027 hysteresis = <1000>; 3028 type = "critical"; 3029 }; 3030 }; 3031 }; 3032 3033 video-thermal { 3034 thermal-sensors = <&tsens0 10>; 3035 3036 trips { 3037 trip-point0 { 3038 temperature = <115000>; 3039 hysteresis = <5000>; 3040 type = "hot"; 3041 }; 3042 3043 video-critical { 3044 temperature = <125000>; 3045 hysteresis = <0>; 3046 type = "critical"; 3047 }; 3048 }; 3049 }; 3050 3051 ddr-thermal { 3052 thermal-sensors = <&tsens0 11>; 3053 3054 trips { 3055 trip-point0 { 3056 temperature = <115000>; 3057 hysteresis = <5000>; 3058 type = "hot"; 3059 }; 3060 3061 ddr-critical { 3062 temperature = <125000>; 3063 hysteresis = <0>; 3064 type = "critical"; 3065 }; 3066 }; 3067 }; 3068 3069 camera0-thermal { 3070 thermal-sensors = <&tsens0 12>; 3071 3072 trips { 3073 trip-point0 { 3074 temperature = <115000>; 3075 hysteresis = <5000>; 3076 type = "hot"; 3077 }; 3078 3079 camera0-critical { 3080 temperature = <125000>; 3081 hysteresis = <0>; 3082 type = "critical"; 3083 }; 3084 }; 3085 }; 3086 3087 camera1-thermal { 3088 thermal-sensors = <&tsens0 13>; 3089 3090 trips { 3091 trip-point0 { 3092 temperature = <115000>; 3093 hysteresis = <5000>; 3094 type = "hot"; 3095 }; 3096 3097 camera1-critical { 3098 temperature = <125000>; 3099 hysteresis = <0>; 3100 type = "critical"; 3101 }; 3102 }; 3103 }; 3104 3105 mdmss-thermal { 3106 thermal-sensors = <&tsens0 14>; 3107 3108 trips { 3109 trip-point0 { 3110 temperature = <115000>; 3111 hysteresis = <5000>; 3112 type = "hot"; 3113 }; 3114 3115 mdmss-critical { 3116 temperature = <125000>; 3117 hysteresis = <0>; 3118 type = "critical"; 3119 }; 3120 }; 3121 }; 3122 }; 3123}; 3124