1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm8450-videocc.h> 8#include <dt-bindings/clock/qcom,sm8550-camcc.h> 9#include <dt-bindings/clock/qcom,sm8550-gcc.h> 10#include <dt-bindings/clock/qcom,sm8550-gpucc.h> 11#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 12#include <dt-bindings/clock/qcom,sm8550-dispcc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/interconnect/qcom,icc.h> 18#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> 19#include <dt-bindings/mailbox/qcom-ipcc.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/power/qcom,rpmhpd.h> 22#include <dt-bindings/soc/qcom,gpr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 25#include <dt-bindings/phy/phy-qcom-qmp.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 clocks { 37 xo_board: xo-board { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 }; 41 42 sleep_clk: sleep-clk { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 }; 46 47 bi_tcxo_div2: bi-tcxo-div2-clk { 48 #clock-cells = <0>; 49 compatible = "fixed-factor-clock"; 50 clocks = <&rpmhcc RPMH_CXO_CLK>; 51 clock-mult = <1>; 52 clock-div = <2>; 53 }; 54 55 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 56 #clock-cells = <0>; 57 compatible = "fixed-factor-clock"; 58 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 59 clock-mult = <1>; 60 clock-div = <2>; 61 }; 62 }; 63 64 cpus { 65 #address-cells = <2>; 66 #size-cells = <0>; 67 68 cpu0: cpu@0 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a510"; 71 reg = <0 0>; 72 clocks = <&cpufreq_hw 0>; 73 enable-method = "psci"; 74 next-level-cache = <&l2_0>; 75 power-domains = <&cpu_pd0>; 76 power-domain-names = "psci"; 77 qcom,freq-domain = <&cpufreq_hw 0>; 78 capacity-dmips-mhz = <1024>; 79 dynamic-power-coefficient = <100>; 80 #cooling-cells = <2>; 81 l2_0: l2-cache { 82 compatible = "cache"; 83 cache-level = <2>; 84 cache-unified; 85 next-level-cache = <&l3_0>; 86 l3_0: l3-cache { 87 compatible = "cache"; 88 cache-level = <3>; 89 cache-unified; 90 }; 91 }; 92 }; 93 94 cpu1: cpu@100 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a510"; 97 reg = <0 0x100>; 98 clocks = <&cpufreq_hw 0>; 99 enable-method = "psci"; 100 next-level-cache = <&l2_100>; 101 power-domains = <&cpu_pd1>; 102 power-domain-names = "psci"; 103 qcom,freq-domain = <&cpufreq_hw 0>; 104 capacity-dmips-mhz = <1024>; 105 dynamic-power-coefficient = <100>; 106 #cooling-cells = <2>; 107 l2_100: l2-cache { 108 compatible = "cache"; 109 cache-level = <2>; 110 cache-unified; 111 next-level-cache = <&l3_0>; 112 }; 113 }; 114 115 cpu2: cpu@200 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a510"; 118 reg = <0 0x200>; 119 clocks = <&cpufreq_hw 0>; 120 enable-method = "psci"; 121 next-level-cache = <&l2_200>; 122 power-domains = <&cpu_pd2>; 123 power-domain-names = "psci"; 124 qcom,freq-domain = <&cpufreq_hw 0>; 125 capacity-dmips-mhz = <1024>; 126 dynamic-power-coefficient = <100>; 127 #cooling-cells = <2>; 128 l2_200: l2-cache { 129 compatible = "cache"; 130 cache-level = <2>; 131 cache-unified; 132 next-level-cache = <&l3_0>; 133 }; 134 }; 135 136 cpu3: cpu@300 { 137 device_type = "cpu"; 138 compatible = "arm,cortex-a715"; 139 reg = <0 0x300>; 140 clocks = <&cpufreq_hw 1>; 141 enable-method = "psci"; 142 next-level-cache = <&l2_300>; 143 power-domains = <&cpu_pd3>; 144 power-domain-names = "psci"; 145 qcom,freq-domain = <&cpufreq_hw 1>; 146 capacity-dmips-mhz = <1792>; 147 dynamic-power-coefficient = <270>; 148 #cooling-cells = <2>; 149 l2_300: l2-cache { 150 compatible = "cache"; 151 cache-level = <2>; 152 cache-unified; 153 next-level-cache = <&l3_0>; 154 }; 155 }; 156 157 cpu4: cpu@400 { 158 device_type = "cpu"; 159 compatible = "arm,cortex-a715"; 160 reg = <0 0x400>; 161 clocks = <&cpufreq_hw 1>; 162 enable-method = "psci"; 163 next-level-cache = <&l2_400>; 164 power-domains = <&cpu_pd4>; 165 power-domain-names = "psci"; 166 qcom,freq-domain = <&cpufreq_hw 1>; 167 capacity-dmips-mhz = <1792>; 168 dynamic-power-coefficient = <270>; 169 #cooling-cells = <2>; 170 l2_400: l2-cache { 171 compatible = "cache"; 172 cache-level = <2>; 173 cache-unified; 174 next-level-cache = <&l3_0>; 175 }; 176 }; 177 178 cpu5: cpu@500 { 179 device_type = "cpu"; 180 compatible = "arm,cortex-a710"; 181 reg = <0 0x500>; 182 clocks = <&cpufreq_hw 1>; 183 enable-method = "psci"; 184 next-level-cache = <&l2_500>; 185 power-domains = <&cpu_pd5>; 186 power-domain-names = "psci"; 187 qcom,freq-domain = <&cpufreq_hw 1>; 188 capacity-dmips-mhz = <1792>; 189 dynamic-power-coefficient = <270>; 190 #cooling-cells = <2>; 191 l2_500: l2-cache { 192 compatible = "cache"; 193 cache-level = <2>; 194 cache-unified; 195 next-level-cache = <&l3_0>; 196 }; 197 }; 198 199 cpu6: cpu@600 { 200 device_type = "cpu"; 201 compatible = "arm,cortex-a710"; 202 reg = <0 0x600>; 203 clocks = <&cpufreq_hw 1>; 204 enable-method = "psci"; 205 next-level-cache = <&l2_600>; 206 power-domains = <&cpu_pd6>; 207 power-domain-names = "psci"; 208 qcom,freq-domain = <&cpufreq_hw 1>; 209 capacity-dmips-mhz = <1792>; 210 dynamic-power-coefficient = <270>; 211 #cooling-cells = <2>; 212 l2_600: l2-cache { 213 compatible = "cache"; 214 cache-level = <2>; 215 cache-unified; 216 next-level-cache = <&l3_0>; 217 }; 218 }; 219 220 cpu7: cpu@700 { 221 device_type = "cpu"; 222 compatible = "arm,cortex-x3"; 223 reg = <0 0x700>; 224 clocks = <&cpufreq_hw 2>; 225 enable-method = "psci"; 226 next-level-cache = <&l2_700>; 227 power-domains = <&cpu_pd7>; 228 power-domain-names = "psci"; 229 qcom,freq-domain = <&cpufreq_hw 2>; 230 capacity-dmips-mhz = <1894>; 231 dynamic-power-coefficient = <588>; 232 #cooling-cells = <2>; 233 l2_700: l2-cache { 234 compatible = "cache"; 235 cache-level = <2>; 236 cache-unified; 237 next-level-cache = <&l3_0>; 238 }; 239 }; 240 241 cpu-map { 242 cluster0 { 243 core0 { 244 cpu = <&cpu0>; 245 }; 246 247 core1 { 248 cpu = <&cpu1>; 249 }; 250 251 core2 { 252 cpu = <&cpu2>; 253 }; 254 255 core3 { 256 cpu = <&cpu3>; 257 }; 258 259 core4 { 260 cpu = <&cpu4>; 261 }; 262 263 core5 { 264 cpu = <&cpu5>; 265 }; 266 267 core6 { 268 cpu = <&cpu6>; 269 }; 270 271 core7 { 272 cpu = <&cpu7>; 273 }; 274 }; 275 }; 276 277 idle-states { 278 entry-method = "psci"; 279 280 little_cpu_sleep_0: cpu-sleep-0-0 { 281 compatible = "arm,idle-state"; 282 idle-state-name = "silver-rail-power-collapse"; 283 arm,psci-suspend-param = <0x40000004>; 284 entry-latency-us = <550>; 285 exit-latency-us = <750>; 286 min-residency-us = <6700>; 287 local-timer-stop; 288 }; 289 290 big_cpu_sleep_0: cpu-sleep-1-0 { 291 compatible = "arm,idle-state"; 292 idle-state-name = "gold-rail-power-collapse"; 293 arm,psci-suspend-param = <0x40000004>; 294 entry-latency-us = <600>; 295 exit-latency-us = <1300>; 296 min-residency-us = <8136>; 297 local-timer-stop; 298 }; 299 300 prime_cpu_sleep_0: cpu-sleep-2-0 { 301 compatible = "arm,idle-state"; 302 idle-state-name = "goldplus-rail-power-collapse"; 303 arm,psci-suspend-param = <0x40000004>; 304 entry-latency-us = <500>; 305 exit-latency-us = <1350>; 306 min-residency-us = <7480>; 307 local-timer-stop; 308 }; 309 }; 310 311 domain-idle-states { 312 cluster_sleep_0: cluster-sleep-0 { 313 compatible = "domain-idle-state"; 314 arm,psci-suspend-param = <0x41000044>; 315 entry-latency-us = <750>; 316 exit-latency-us = <2350>; 317 min-residency-us = <9144>; 318 }; 319 320 cluster_sleep_1: cluster-sleep-1 { 321 compatible = "domain-idle-state"; 322 arm,psci-suspend-param = <0x4100c344>; 323 entry-latency-us = <2800>; 324 exit-latency-us = <4400>; 325 min-residency-us = <10150>; 326 }; 327 }; 328 }; 329 330 firmware { 331 scm: scm { 332 compatible = "qcom,scm-sm8550", "qcom,scm"; 333 qcom,dload-mode = <&tcsr 0x19000>; 334 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 335 }; 336 }; 337 338 clk_virt: interconnect-0 { 339 compatible = "qcom,sm8550-clk-virt"; 340 #interconnect-cells = <2>; 341 qcom,bcm-voters = <&apps_bcm_voter>; 342 }; 343 344 mc_virt: interconnect-1 { 345 compatible = "qcom,sm8550-mc-virt"; 346 #interconnect-cells = <2>; 347 qcom,bcm-voters = <&apps_bcm_voter>; 348 }; 349 350 memory@a0000000 { 351 device_type = "memory"; 352 /* We expect the bootloader to fill in the size */ 353 reg = <0 0xa0000000 0 0>; 354 }; 355 356 pmu-a510 { 357 compatible = "arm,cortex-a510-pmu"; 358 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 359 }; 360 361 pmu-a710 { 362 compatible = "arm,cortex-a710-pmu"; 363 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 364 }; 365 366 pmu-a715 { 367 compatible = "arm,cortex-a715-pmu"; 368 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 369 }; 370 371 pmu-x3 { 372 compatible = "arm,cortex-x3-pmu"; 373 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 374 }; 375 376 psci { 377 compatible = "arm,psci-1.0"; 378 method = "smc"; 379 380 cpu_pd0: power-domain-cpu0 { 381 #power-domain-cells = <0>; 382 power-domains = <&cluster_pd>; 383 domain-idle-states = <&little_cpu_sleep_0>; 384 }; 385 386 cpu_pd1: power-domain-cpu1 { 387 #power-domain-cells = <0>; 388 power-domains = <&cluster_pd>; 389 domain-idle-states = <&little_cpu_sleep_0>; 390 }; 391 392 cpu_pd2: power-domain-cpu2 { 393 #power-domain-cells = <0>; 394 power-domains = <&cluster_pd>; 395 domain-idle-states = <&little_cpu_sleep_0>; 396 }; 397 398 cpu_pd3: power-domain-cpu3 { 399 #power-domain-cells = <0>; 400 power-domains = <&cluster_pd>; 401 domain-idle-states = <&big_cpu_sleep_0>; 402 }; 403 404 cpu_pd4: power-domain-cpu4 { 405 #power-domain-cells = <0>; 406 power-domains = <&cluster_pd>; 407 domain-idle-states = <&big_cpu_sleep_0>; 408 }; 409 410 cpu_pd5: power-domain-cpu5 { 411 #power-domain-cells = <0>; 412 power-domains = <&cluster_pd>; 413 domain-idle-states = <&big_cpu_sleep_0>; 414 }; 415 416 cpu_pd6: power-domain-cpu6 { 417 #power-domain-cells = <0>; 418 power-domains = <&cluster_pd>; 419 domain-idle-states = <&big_cpu_sleep_0>; 420 }; 421 422 cpu_pd7: power-domain-cpu7 { 423 #power-domain-cells = <0>; 424 power-domains = <&cluster_pd>; 425 domain-idle-states = <&prime_cpu_sleep_0>; 426 }; 427 428 cluster_pd: power-domain-cluster { 429 #power-domain-cells = <0>; 430 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>; 431 }; 432 }; 433 434 reserved_memory: reserved-memory { 435 #address-cells = <2>; 436 #size-cells = <2>; 437 ranges; 438 439 hyp_mem: hyp-region@80000000 { 440 reg = <0 0x80000000 0 0xa00000>; 441 no-map; 442 }; 443 444 cpusys_vm_mem: cpusys-vm-region@80a00000 { 445 reg = <0 0x80a00000 0 0x400000>; 446 no-map; 447 }; 448 449 hyp_tags_mem: hyp-tags-region@80e00000 { 450 reg = <0 0x80e00000 0 0x3d0000>; 451 no-map; 452 }; 453 454 xbl_sc_mem: xbl-sc-region@d8100000 { 455 reg = <0 0xd8100000 0 0x40000>; 456 no-map; 457 }; 458 459 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { 460 reg = <0 0x811d0000 0 0x30000>; 461 no-map; 462 }; 463 464 /* merged xbl_dt_log, xbl_ramdump, aop_image */ 465 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { 466 reg = <0 0x81a00000 0 0x260000>; 467 no-map; 468 }; 469 470 aop_cmd_db_mem: aop-cmd-db-region@81c60000 { 471 compatible = "qcom,cmd-db"; 472 reg = <0 0x81c60000 0 0x20000>; 473 no-map; 474 }; 475 476 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ 477 aop_config_merged_mem: aop-config-merged-region@81c80000 { 478 reg = <0 0x81c80000 0 0x74000>; 479 no-map; 480 }; 481 482 /* secdata region can be reused by apps */ 483 smem: smem@81d00000 { 484 compatible = "qcom,smem"; 485 reg = <0 0x81d00000 0 0x200000>; 486 hwlocks = <&tcsr_mutex 3>; 487 no-map; 488 }; 489 490 adsp_mhi_mem: adsp-mhi-region@81f00000 { 491 reg = <0 0x81f00000 0 0x20000>; 492 no-map; 493 }; 494 495 global_sync_mem: global-sync-region@82600000 { 496 reg = <0 0x82600000 0 0x100000>; 497 no-map; 498 }; 499 500 tz_stat_mem: tz-stat-region@82700000 { 501 reg = <0 0x82700000 0 0x100000>; 502 no-map; 503 }; 504 505 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { 506 reg = <0 0x82800000 0 0x4600000>; 507 no-map; 508 }; 509 510 mpss_mem: mpss-region@8a800000 { 511 reg = <0 0x8a800000 0 0x10800000>; 512 no-map; 513 }; 514 515 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { 516 reg = <0 0x9b000000 0 0x80000>; 517 no-map; 518 }; 519 520 ipa_fw_mem: ipa-fw-region@9b080000 { 521 reg = <0 0x9b080000 0 0x10000>; 522 no-map; 523 }; 524 525 ipa_gsi_mem: ipa-gsi-region@9b090000 { 526 reg = <0 0x9b090000 0 0xa000>; 527 no-map; 528 }; 529 530 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { 531 reg = <0 0x9b09a000 0 0x2000>; 532 no-map; 533 }; 534 535 spss_region_mem: spss-region@9b100000 { 536 reg = <0 0x9b100000 0 0x180000>; 537 no-map; 538 }; 539 540 /* First part of the "SPU secure shared memory" region */ 541 spu_tz_shared_mem: spu-tz-shared-region@9b280000 { 542 reg = <0 0x9b280000 0 0x60000>; 543 no-map; 544 }; 545 546 /* Second part of the "SPU secure shared memory" region */ 547 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { 548 reg = <0 0x9b2e0000 0 0x20000>; 549 no-map; 550 }; 551 552 camera_mem: camera-region@9b300000 { 553 reg = <0 0x9b300000 0 0x800000>; 554 no-map; 555 }; 556 557 video_mem: video-region@9bb00000 { 558 reg = <0 0x9bb00000 0 0x700000>; 559 no-map; 560 }; 561 562 cvp_mem: cvp-region@9c200000 { 563 reg = <0 0x9c200000 0 0x700000>; 564 no-map; 565 }; 566 567 cdsp_mem: cdsp-region@9c900000 { 568 reg = <0 0x9c900000 0 0x2000000>; 569 no-map; 570 }; 571 572 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { 573 reg = <0 0x9e900000 0 0x80000>; 574 no-map; 575 }; 576 577 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { 578 reg = <0 0x9e980000 0 0x80000>; 579 no-map; 580 }; 581 582 adspslpi_mem: adspslpi-region@9ea00000 { 583 reg = <0 0x9ea00000 0 0x4080000>; 584 no-map; 585 }; 586 587 /* uefi region can be reused by apps */ 588 589 /* Linux kernel image is loaded at 0xa8000000 */ 590 591 rmtfs_mem: rmtfs-region@d4a80000 { 592 compatible = "qcom,rmtfs-mem"; 593 reg = <0x0 0xd4a80000 0x0 0x280000>; 594 no-map; 595 596 qcom,client-id = <1>; 597 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 598 }; 599 600 mpss_dsm_mem: mpss-dsm-region@d4d00000 { 601 reg = <0 0xd4d00000 0 0x3300000>; 602 no-map; 603 }; 604 605 tz_reserved_mem: tz-reserved-region@d8000000 { 606 reg = <0 0xd8000000 0 0x100000>; 607 no-map; 608 }; 609 610 cpucp_fw_mem: cpucp-fw-region@d8140000 { 611 reg = <0 0xd8140000 0 0x1c0000>; 612 no-map; 613 }; 614 615 qtee_mem: qtee-region@d8300000 { 616 reg = <0 0xd8300000 0 0x500000>; 617 no-map; 618 }; 619 620 ta_mem: ta-region@d8800000 { 621 reg = <0 0xd8800000 0 0x8a00000>; 622 no-map; 623 }; 624 625 tz_tags_mem: tz-tags-region@e1200000 { 626 reg = <0 0xe1200000 0 0x2740000>; 627 no-map; 628 }; 629 630 hwfence_shbuf: hwfence-shbuf-region@e6440000 { 631 reg = <0 0xe6440000 0 0x279000>; 632 no-map; 633 }; 634 635 trust_ui_vm_mem: trust-ui-vm-region@f3600000 { 636 reg = <0 0xf3600000 0 0x4aee000>; 637 no-map; 638 }; 639 640 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { 641 reg = <0 0xf80ee000 0 0x1000>; 642 no-map; 643 }; 644 645 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { 646 reg = <0 0xf80ef000 0 0x9000>; 647 no-map; 648 }; 649 650 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { 651 reg = <0 0xf80f8000 0 0x4000>; 652 no-map; 653 }; 654 655 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { 656 reg = <0 0xf80fc000 0 0x4000>; 657 no-map; 658 }; 659 660 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { 661 reg = <0 0xf8100000 0 0x100000>; 662 no-map; 663 }; 664 665 oem_vm_mem: oem-vm-region@f8400000 { 666 reg = <0 0xf8400000 0 0x4800000>; 667 no-map; 668 }; 669 670 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { 671 reg = <0 0xfcc00000 0 0x4000>; 672 no-map; 673 }; 674 675 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { 676 reg = <0 0xfcc04000 0 0x100000>; 677 no-map; 678 }; 679 680 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { 681 reg = <0 0xfce00000 0 0x2900000>; 682 no-map; 683 }; 684 685 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { 686 reg = <0 0xff700000 0 0x100000>; 687 no-map; 688 }; 689 }; 690 691 smp2p-adsp { 692 compatible = "qcom,smp2p"; 693 qcom,smem = <443>, <429>; 694 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 695 IPCC_MPROC_SIGNAL_SMP2P 696 IRQ_TYPE_EDGE_RISING>; 697 mboxes = <&ipcc IPCC_CLIENT_LPASS 698 IPCC_MPROC_SIGNAL_SMP2P>; 699 700 qcom,local-pid = <0>; 701 qcom,remote-pid = <2>; 702 703 smp2p_adsp_out: master-kernel { 704 qcom,entry-name = "master-kernel"; 705 #qcom,smem-state-cells = <1>; 706 }; 707 708 smp2p_adsp_in: slave-kernel { 709 qcom,entry-name = "slave-kernel"; 710 interrupt-controller; 711 #interrupt-cells = <2>; 712 }; 713 }; 714 715 smp2p-cdsp { 716 compatible = "qcom,smp2p"; 717 qcom,smem = <94>, <432>; 718 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 719 IPCC_MPROC_SIGNAL_SMP2P 720 IRQ_TYPE_EDGE_RISING>; 721 mboxes = <&ipcc IPCC_CLIENT_CDSP 722 IPCC_MPROC_SIGNAL_SMP2P>; 723 724 qcom,local-pid = <0>; 725 qcom,remote-pid = <5>; 726 727 smp2p_cdsp_out: master-kernel { 728 qcom,entry-name = "master-kernel"; 729 #qcom,smem-state-cells = <1>; 730 }; 731 732 smp2p_cdsp_in: slave-kernel { 733 qcom,entry-name = "slave-kernel"; 734 interrupt-controller; 735 #interrupt-cells = <2>; 736 }; 737 }; 738 739 smp2p-modem { 740 compatible = "qcom,smp2p"; 741 qcom,smem = <435>, <428>; 742 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 743 IPCC_MPROC_SIGNAL_SMP2P 744 IRQ_TYPE_EDGE_RISING>; 745 mboxes = <&ipcc IPCC_CLIENT_MPSS 746 IPCC_MPROC_SIGNAL_SMP2P>; 747 748 qcom,local-pid = <0>; 749 qcom,remote-pid = <1>; 750 751 smp2p_modem_out: master-kernel { 752 qcom,entry-name = "master-kernel"; 753 #qcom,smem-state-cells = <1>; 754 }; 755 756 smp2p_modem_in: slave-kernel { 757 qcom,entry-name = "slave-kernel"; 758 interrupt-controller; 759 #interrupt-cells = <2>; 760 }; 761 762 ipa_smp2p_out: ipa-ap-to-modem { 763 qcom,entry-name = "ipa"; 764 #qcom,smem-state-cells = <1>; 765 }; 766 767 ipa_smp2p_in: ipa-modem-to-ap { 768 qcom,entry-name = "ipa"; 769 interrupt-controller; 770 #interrupt-cells = <2>; 771 }; 772 }; 773 774 soc: soc@0 { 775 compatible = "simple-bus"; 776 ranges = <0 0 0 0 0x10 0>; 777 dma-ranges = <0 0 0 0 0x10 0>; 778 779 #address-cells = <2>; 780 #size-cells = <2>; 781 782 gcc: clock-controller@100000 { 783 compatible = "qcom,sm8550-gcc"; 784 reg = <0 0x00100000 0 0x1f4200>; 785 #clock-cells = <1>; 786 #reset-cells = <1>; 787 #power-domain-cells = <1>; 788 clocks = <&bi_tcxo_div2>, <&sleep_clk>, 789 <&pcie0_phy>, 790 <&pcie1_phy QMP_PCIE_PIPE_CLK>, 791 <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, 792 <&ufs_mem_phy 0>, 793 <&ufs_mem_phy 1>, 794 <&ufs_mem_phy 2>, 795 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 796 }; 797 798 ipcc: mailbox@408000 { 799 compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; 800 reg = <0 0x00408000 0 0x1000>; 801 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 802 interrupt-controller; 803 #interrupt-cells = <3>; 804 #mbox-cells = <2>; 805 }; 806 807 gpi_dma2: dma-controller@800000 { 808 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 809 #dma-cells = <3>; 810 reg = <0 0x00800000 0 0x60000>; 811 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 823 dma-channels = <12>; 824 dma-channel-mask = <0x3e>; 825 iommus = <&apps_smmu 0x436 0>; 826 dma-coherent; 827 status = "disabled"; 828 }; 829 830 qupv3_id_1: geniqup@8c0000 { 831 compatible = "qcom,geni-se-qup"; 832 reg = <0 0x008c0000 0 0x2000>; 833 ranges; 834 clock-names = "m-ahb", "s-ahb"; 835 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 836 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 837 iommus = <&apps_smmu 0x423 0>; 838 dma-coherent; 839 #address-cells = <2>; 840 #size-cells = <2>; 841 status = "disabled"; 842 843 i2c8: i2c@880000 { 844 compatible = "qcom,geni-i2c"; 845 reg = <0 0x00880000 0 0x4000>; 846 clock-names = "se"; 847 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 848 pinctrl-names = "default"; 849 pinctrl-0 = <&qup_i2c8_data_clk>; 850 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 851 #address-cells = <1>; 852 #size-cells = <0>; 853 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 854 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 855 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 856 interconnect-names = "qup-core", "qup-config", "qup-memory"; 857 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 858 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 859 dma-names = "tx", "rx"; 860 status = "disabled"; 861 }; 862 863 spi8: spi@880000 { 864 compatible = "qcom,geni-spi"; 865 reg = <0 0x00880000 0 0x4000>; 866 clock-names = "se"; 867 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 868 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 869 pinctrl-names = "default"; 870 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 871 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 872 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 873 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 874 interconnect-names = "qup-core", "qup-config", "qup-memory"; 875 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 876 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 877 dma-names = "tx", "rx"; 878 #address-cells = <1>; 879 #size-cells = <0>; 880 status = "disabled"; 881 }; 882 883 i2c9: i2c@884000 { 884 compatible = "qcom,geni-i2c"; 885 reg = <0 0x00884000 0 0x4000>; 886 clock-names = "se"; 887 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 888 pinctrl-names = "default"; 889 pinctrl-0 = <&qup_i2c9_data_clk>; 890 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 894 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 895 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 896 interconnect-names = "qup-core", "qup-config", "qup-memory"; 897 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 898 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 899 dma-names = "tx", "rx"; 900 status = "disabled"; 901 }; 902 903 spi9: spi@884000 { 904 compatible = "qcom,geni-spi"; 905 reg = <0 0x00884000 0 0x4000>; 906 clock-names = "se"; 907 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 908 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 909 pinctrl-names = "default"; 910 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 911 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 912 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 913 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 914 interconnect-names = "qup-core", "qup-config", "qup-memory"; 915 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 916 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 917 dma-names = "tx", "rx"; 918 #address-cells = <1>; 919 #size-cells = <0>; 920 status = "disabled"; 921 }; 922 923 i2c10: i2c@888000 { 924 compatible = "qcom,geni-i2c"; 925 reg = <0 0x00888000 0 0x4000>; 926 clock-names = "se"; 927 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 928 pinctrl-names = "default"; 929 pinctrl-0 = <&qup_i2c10_data_clk>; 930 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 931 #address-cells = <1>; 932 #size-cells = <0>; 933 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 934 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 935 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 936 interconnect-names = "qup-core", "qup-config", "qup-memory"; 937 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 938 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 939 dma-names = "tx", "rx"; 940 status = "disabled"; 941 }; 942 943 spi10: spi@888000 { 944 compatible = "qcom,geni-spi"; 945 reg = <0 0x00888000 0 0x4000>; 946 clock-names = "se"; 947 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 948 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 949 pinctrl-names = "default"; 950 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 951 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 952 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 953 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 954 interconnect-names = "qup-core", "qup-config", "qup-memory"; 955 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 956 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 957 dma-names = "tx", "rx"; 958 #address-cells = <1>; 959 #size-cells = <0>; 960 status = "disabled"; 961 }; 962 963 i2c11: i2c@88c000 { 964 compatible = "qcom,geni-i2c"; 965 reg = <0 0x0088c000 0 0x4000>; 966 clock-names = "se"; 967 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 968 pinctrl-names = "default"; 969 pinctrl-0 = <&qup_i2c11_data_clk>; 970 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 971 #address-cells = <1>; 972 #size-cells = <0>; 973 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 974 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 975 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 976 interconnect-names = "qup-core", "qup-config", "qup-memory"; 977 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 978 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 979 dma-names = "tx", "rx"; 980 status = "disabled"; 981 }; 982 983 spi11: spi@88c000 { 984 compatible = "qcom,geni-spi"; 985 reg = <0 0x0088c000 0 0x4000>; 986 clock-names = "se"; 987 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 988 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 989 pinctrl-names = "default"; 990 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 991 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 992 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 993 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 994 interconnect-names = "qup-core", "qup-config", "qup-memory"; 995 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 996 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 997 dma-names = "tx", "rx"; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 status = "disabled"; 1001 }; 1002 1003 i2c12: i2c@890000 { 1004 compatible = "qcom,geni-i2c"; 1005 reg = <0 0x00890000 0 0x4000>; 1006 clock-names = "se"; 1007 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1008 pinctrl-names = "default"; 1009 pinctrl-0 = <&qup_i2c12_data_clk>; 1010 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1014 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1015 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1016 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1017 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1018 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1019 dma-names = "tx", "rx"; 1020 status = "disabled"; 1021 }; 1022 1023 spi12: spi@890000 { 1024 compatible = "qcom,geni-spi"; 1025 reg = <0 0x00890000 0 0x4000>; 1026 clock-names = "se"; 1027 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1028 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1029 pinctrl-names = "default"; 1030 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1031 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1032 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1033 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1034 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1035 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1036 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1037 dma-names = "tx", "rx"; 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 status = "disabled"; 1041 }; 1042 1043 i2c13: i2c@894000 { 1044 compatible = "qcom,geni-i2c"; 1045 reg = <0 0x00894000 0 0x4000>; 1046 clock-names = "se"; 1047 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1048 pinctrl-names = "default"; 1049 pinctrl-0 = <&qup_i2c13_data_clk>; 1050 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1054 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1055 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1056 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1057 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1058 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1059 dma-names = "tx", "rx"; 1060 status = "disabled"; 1061 }; 1062 1063 spi13: spi@894000 { 1064 compatible = "qcom,geni-spi"; 1065 reg = <0 0x00894000 0 0x4000>; 1066 clock-names = "se"; 1067 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1068 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1069 pinctrl-names = "default"; 1070 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1071 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1072 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1073 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1074 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1075 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1076 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1077 dma-names = "tx", "rx"; 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 status = "disabled"; 1081 }; 1082 1083 uart14: serial@898000 { 1084 compatible = "qcom,geni-uart"; 1085 reg = <0 0x898000 0 0x4000>; 1086 clock-names = "se"; 1087 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1088 pinctrl-names = "default"; 1089 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; 1090 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1091 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1092 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 1093 interconnect-names = "qup-core", "qup-config"; 1094 status = "disabled"; 1095 }; 1096 1097 i2c15: i2c@89c000 { 1098 compatible = "qcom,geni-i2c"; 1099 reg = <0 0x0089c000 0 0x4000>; 1100 clock-names = "se"; 1101 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1102 pinctrl-names = "default"; 1103 pinctrl-0 = <&qup_i2c15_data_clk>; 1104 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1108 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1109 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1110 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1111 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1112 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1113 dma-names = "tx", "rx"; 1114 status = "disabled"; 1115 }; 1116 1117 spi15: spi@89c000 { 1118 compatible = "qcom,geni-spi"; 1119 reg = <0 0x0089c000 0 0x4000>; 1120 clock-names = "se"; 1121 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1122 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1123 pinctrl-names = "default"; 1124 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1125 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1126 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1127 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1128 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1129 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1130 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1131 dma-names = "tx", "rx"; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 status = "disabled"; 1135 }; 1136 }; 1137 1138 i2c_master_hub_0: geniqup@9c0000 { 1139 compatible = "qcom,geni-se-i2c-master-hub"; 1140 reg = <0x0 0x009c0000 0x0 0x2000>; 1141 clock-names = "s-ahb"; 1142 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1143 #address-cells = <2>; 1144 #size-cells = <2>; 1145 ranges; 1146 status = "disabled"; 1147 1148 i2c_hub_0: i2c@980000 { 1149 compatible = "qcom,geni-i2c-master-hub"; 1150 reg = <0x0 0x00980000 0x0 0x4000>; 1151 clock-names = "se", "core"; 1152 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1153 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1154 pinctrl-names = "default"; 1155 pinctrl-0 = <&hub_i2c0_data_clk>; 1156 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1160 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1161 interconnect-names = "qup-core", "qup-config"; 1162 status = "disabled"; 1163 }; 1164 1165 i2c_hub_1: i2c@984000 { 1166 compatible = "qcom,geni-i2c-master-hub"; 1167 reg = <0x0 0x00984000 0x0 0x4000>; 1168 clock-names = "se", "core"; 1169 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1170 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1171 pinctrl-names = "default"; 1172 pinctrl-0 = <&hub_i2c1_data_clk>; 1173 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1174 #address-cells = <1>; 1175 #size-cells = <0>; 1176 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1177 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1178 interconnect-names = "qup-core", "qup-config"; 1179 status = "disabled"; 1180 }; 1181 1182 i2c_hub_2: i2c@988000 { 1183 compatible = "qcom,geni-i2c-master-hub"; 1184 reg = <0x0 0x00988000 0x0 0x4000>; 1185 clock-names = "se", "core"; 1186 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1187 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1188 pinctrl-names = "default"; 1189 pinctrl-0 = <&hub_i2c2_data_clk>; 1190 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1191 #address-cells = <1>; 1192 #size-cells = <0>; 1193 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1194 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1195 interconnect-names = "qup-core", "qup-config"; 1196 status = "disabled"; 1197 }; 1198 1199 i2c_hub_3: i2c@98c000 { 1200 compatible = "qcom,geni-i2c-master-hub"; 1201 reg = <0x0 0x0098c000 0x0 0x4000>; 1202 clock-names = "se", "core"; 1203 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1204 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1205 pinctrl-names = "default"; 1206 pinctrl-0 = <&hub_i2c3_data_clk>; 1207 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1208 #address-cells = <1>; 1209 #size-cells = <0>; 1210 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1211 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1212 interconnect-names = "qup-core", "qup-config"; 1213 status = "disabled"; 1214 }; 1215 1216 i2c_hub_4: i2c@990000 { 1217 compatible = "qcom,geni-i2c-master-hub"; 1218 reg = <0x0 0x00990000 0x0 0x4000>; 1219 clock-names = "se", "core"; 1220 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1221 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1222 pinctrl-names = "default"; 1223 pinctrl-0 = <&hub_i2c4_data_clk>; 1224 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1225 #address-cells = <1>; 1226 #size-cells = <0>; 1227 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1228 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1229 interconnect-names = "qup-core", "qup-config"; 1230 status = "disabled"; 1231 }; 1232 1233 i2c_hub_5: i2c@994000 { 1234 compatible = "qcom,geni-i2c-master-hub"; 1235 reg = <0 0x00994000 0 0x4000>; 1236 clock-names = "se", "core"; 1237 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1238 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1239 pinctrl-names = "default"; 1240 pinctrl-0 = <&hub_i2c5_data_clk>; 1241 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1242 #address-cells = <1>; 1243 #size-cells = <0>; 1244 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1245 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1246 interconnect-names = "qup-core", "qup-config"; 1247 status = "disabled"; 1248 }; 1249 1250 i2c_hub_6: i2c@998000 { 1251 compatible = "qcom,geni-i2c-master-hub"; 1252 reg = <0 0x00998000 0 0x4000>; 1253 clock-names = "se", "core"; 1254 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1255 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1256 pinctrl-names = "default"; 1257 pinctrl-0 = <&hub_i2c6_data_clk>; 1258 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1259 #address-cells = <1>; 1260 #size-cells = <0>; 1261 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1262 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1263 interconnect-names = "qup-core", "qup-config"; 1264 status = "disabled"; 1265 }; 1266 1267 i2c_hub_7: i2c@99c000 { 1268 compatible = "qcom,geni-i2c-master-hub"; 1269 reg = <0 0x0099c000 0 0x4000>; 1270 clock-names = "se", "core"; 1271 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1272 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1273 pinctrl-names = "default"; 1274 pinctrl-0 = <&hub_i2c7_data_clk>; 1275 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1276 #address-cells = <1>; 1277 #size-cells = <0>; 1278 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1279 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1280 interconnect-names = "qup-core", "qup-config"; 1281 status = "disabled"; 1282 }; 1283 1284 i2c_hub_8: i2c@9a0000 { 1285 compatible = "qcom,geni-i2c-master-hub"; 1286 reg = <0 0x009a0000 0 0x4000>; 1287 clock-names = "se", "core"; 1288 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1289 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1290 pinctrl-names = "default"; 1291 pinctrl-0 = <&hub_i2c8_data_clk>; 1292 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1296 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1297 interconnect-names = "qup-core", "qup-config"; 1298 status = "disabled"; 1299 }; 1300 1301 i2c_hub_9: i2c@9a4000 { 1302 compatible = "qcom,geni-i2c-master-hub"; 1303 reg = <0 0x009a4000 0 0x4000>; 1304 clock-names = "se", "core"; 1305 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1306 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1307 pinctrl-names = "default"; 1308 pinctrl-0 = <&hub_i2c9_data_clk>; 1309 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1310 #address-cells = <1>; 1311 #size-cells = <0>; 1312 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1313 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1314 interconnect-names = "qup-core", "qup-config"; 1315 status = "disabled"; 1316 }; 1317 }; 1318 1319 gpi_dma1: dma-controller@a00000 { 1320 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 1321 #dma-cells = <3>; 1322 reg = <0 0x00a00000 0 0x60000>; 1323 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1324 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1325 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1326 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1327 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1328 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1329 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1330 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1331 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1332 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1333 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1334 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1335 dma-channels = <12>; 1336 dma-channel-mask = <0x1e>; 1337 iommus = <&apps_smmu 0xb6 0>; 1338 dma-coherent; 1339 status = "disabled"; 1340 }; 1341 1342 qupv3_id_0: geniqup@ac0000 { 1343 compatible = "qcom,geni-se-qup"; 1344 reg = <0 0x00ac0000 0 0x2000>; 1345 ranges; 1346 clock-names = "m-ahb", "s-ahb"; 1347 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1348 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1349 iommus = <&apps_smmu 0xa3 0>; 1350 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1351 interconnect-names = "qup-core"; 1352 dma-coherent; 1353 #address-cells = <2>; 1354 #size-cells = <2>; 1355 status = "disabled"; 1356 1357 i2c0: i2c@a80000 { 1358 compatible = "qcom,geni-i2c"; 1359 reg = <0 0x00a80000 0 0x4000>; 1360 clock-names = "se"; 1361 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1362 pinctrl-names = "default"; 1363 pinctrl-0 = <&qup_i2c0_data_clk>; 1364 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1365 #address-cells = <1>; 1366 #size-cells = <0>; 1367 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1368 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1369 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1370 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1371 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1372 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1373 dma-names = "tx", "rx"; 1374 status = "disabled"; 1375 }; 1376 1377 spi0: spi@a80000 { 1378 compatible = "qcom,geni-spi"; 1379 reg = <0 0x00a80000 0 0x4000>; 1380 clock-names = "se"; 1381 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1382 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1383 pinctrl-names = "default"; 1384 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1385 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1386 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1387 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1388 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1389 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1390 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1391 dma-names = "tx", "rx"; 1392 #address-cells = <1>; 1393 #size-cells = <0>; 1394 status = "disabled"; 1395 }; 1396 1397 i2c1: i2c@a84000 { 1398 compatible = "qcom,geni-i2c"; 1399 reg = <0 0x00a84000 0 0x4000>; 1400 clock-names = "se"; 1401 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1402 pinctrl-names = "default"; 1403 pinctrl-0 = <&qup_i2c1_data_clk>; 1404 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1405 #address-cells = <1>; 1406 #size-cells = <0>; 1407 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1408 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1409 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1410 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1411 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1412 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1413 dma-names = "tx", "rx"; 1414 status = "disabled"; 1415 }; 1416 1417 spi1: spi@a84000 { 1418 compatible = "qcom,geni-spi"; 1419 reg = <0 0x00a84000 0 0x4000>; 1420 clock-names = "se"; 1421 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1422 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1423 pinctrl-names = "default"; 1424 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1425 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1426 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1427 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1428 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1429 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1430 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1431 dma-names = "tx", "rx"; 1432 #address-cells = <1>; 1433 #size-cells = <0>; 1434 status = "disabled"; 1435 }; 1436 1437 i2c2: i2c@a88000 { 1438 compatible = "qcom,geni-i2c"; 1439 reg = <0 0x00a88000 0 0x4000>; 1440 clock-names = "se"; 1441 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1442 pinctrl-names = "default"; 1443 pinctrl-0 = <&qup_i2c2_data_clk>; 1444 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1445 #address-cells = <1>; 1446 #size-cells = <0>; 1447 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1448 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1449 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1450 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1451 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1452 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1453 dma-names = "tx", "rx"; 1454 status = "disabled"; 1455 }; 1456 1457 spi2: spi@a88000 { 1458 compatible = "qcom,geni-spi"; 1459 reg = <0 0x00a88000 0 0x4000>; 1460 clock-names = "se"; 1461 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1462 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1463 pinctrl-names = "default"; 1464 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1465 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1466 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1467 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1468 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1469 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1470 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1471 dma-names = "tx", "rx"; 1472 #address-cells = <1>; 1473 #size-cells = <0>; 1474 status = "disabled"; 1475 }; 1476 1477 i2c3: i2c@a8c000 { 1478 compatible = "qcom,geni-i2c"; 1479 reg = <0 0x00a8c000 0 0x4000>; 1480 clock-names = "se"; 1481 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1482 pinctrl-names = "default"; 1483 pinctrl-0 = <&qup_i2c3_data_clk>; 1484 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1485 #address-cells = <1>; 1486 #size-cells = <0>; 1487 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1488 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1489 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1490 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1491 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1492 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1493 dma-names = "tx", "rx"; 1494 status = "disabled"; 1495 }; 1496 1497 spi3: spi@a8c000 { 1498 compatible = "qcom,geni-spi"; 1499 reg = <0 0x00a8c000 0 0x4000>; 1500 clock-names = "se"; 1501 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1502 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1503 pinctrl-names = "default"; 1504 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1505 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1506 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1507 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1508 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1509 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1510 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1511 dma-names = "tx", "rx"; 1512 #address-cells = <1>; 1513 #size-cells = <0>; 1514 status = "disabled"; 1515 }; 1516 1517 i2c4: i2c@a90000 { 1518 compatible = "qcom,geni-i2c"; 1519 reg = <0 0x00a90000 0 0x4000>; 1520 clock-names = "se"; 1521 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1522 pinctrl-names = "default"; 1523 pinctrl-0 = <&qup_i2c4_data_clk>; 1524 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1525 #address-cells = <1>; 1526 #size-cells = <0>; 1527 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1528 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1529 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1530 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1531 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1532 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1533 dma-names = "tx", "rx"; 1534 status = "disabled"; 1535 }; 1536 1537 spi4: spi@a90000 { 1538 compatible = "qcom,geni-spi"; 1539 reg = <0 0x00a90000 0 0x4000>; 1540 clock-names = "se"; 1541 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1542 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1543 pinctrl-names = "default"; 1544 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1545 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1546 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1547 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1548 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1549 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1550 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1551 dma-names = "tx", "rx"; 1552 #address-cells = <1>; 1553 #size-cells = <0>; 1554 status = "disabled"; 1555 }; 1556 1557 i2c5: i2c@a94000 { 1558 compatible = "qcom,geni-i2c"; 1559 reg = <0 0x00a94000 0 0x4000>; 1560 clock-names = "se"; 1561 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1562 pinctrl-names = "default"; 1563 pinctrl-0 = <&qup_i2c5_data_clk>; 1564 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1565 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1566 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1567 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1568 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1569 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1570 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1571 dma-names = "tx", "rx"; 1572 #address-cells = <1>; 1573 #size-cells = <0>; 1574 status = "disabled"; 1575 }; 1576 1577 spi5: spi@a94000 { 1578 compatible = "qcom,geni-spi"; 1579 reg = <0 0x00a94000 0 0x4000>; 1580 clock-names = "se"; 1581 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1582 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1583 pinctrl-names = "default"; 1584 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1585 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1586 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1587 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1588 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1589 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1590 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1591 dma-names = "tx", "rx"; 1592 #address-cells = <1>; 1593 #size-cells = <0>; 1594 status = "disabled"; 1595 }; 1596 1597 i2c6: i2c@a98000 { 1598 compatible = "qcom,geni-i2c"; 1599 reg = <0 0x00a98000 0 0x4000>; 1600 clock-names = "se"; 1601 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1602 pinctrl-names = "default"; 1603 pinctrl-0 = <&qup_i2c6_data_clk>; 1604 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1605 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1606 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1607 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1608 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1609 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1610 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1611 dma-names = "tx", "rx"; 1612 #address-cells = <1>; 1613 #size-cells = <0>; 1614 status = "disabled"; 1615 }; 1616 1617 spi6: spi@a98000 { 1618 compatible = "qcom,geni-spi"; 1619 reg = <0 0x00a98000 0 0x4000>; 1620 clock-names = "se"; 1621 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1622 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1623 pinctrl-names = "default"; 1624 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1625 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1626 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1627 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1628 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1629 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1630 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1631 dma-names = "tx", "rx"; 1632 #address-cells = <1>; 1633 #size-cells = <0>; 1634 status = "disabled"; 1635 }; 1636 1637 uart7: serial@a9c000 { 1638 compatible = "qcom,geni-debug-uart"; 1639 reg = <0 0x00a9c000 0 0x4000>; 1640 clock-names = "se"; 1641 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1642 pinctrl-names = "default"; 1643 pinctrl-0 = <&qup_uart7_default>; 1644 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1645 interconnect-names = "qup-core", "qup-config"; 1646 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1647 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1648 status = "disabled"; 1649 }; 1650 }; 1651 1652 cnoc_main: interconnect@1500000 { 1653 compatible = "qcom,sm8550-cnoc-main"; 1654 reg = <0 0x01500000 0 0x13080>; 1655 #interconnect-cells = <2>; 1656 qcom,bcm-voters = <&apps_bcm_voter>; 1657 }; 1658 1659 config_noc: interconnect@1600000 { 1660 compatible = "qcom,sm8550-config-noc"; 1661 reg = <0 0x01600000 0 0x6200>; 1662 #interconnect-cells = <2>; 1663 qcom,bcm-voters = <&apps_bcm_voter>; 1664 }; 1665 1666 system_noc: interconnect@1680000 { 1667 compatible = "qcom,sm8550-system-noc"; 1668 reg = <0 0x01680000 0 0x1d080>; 1669 #interconnect-cells = <2>; 1670 qcom,bcm-voters = <&apps_bcm_voter>; 1671 }; 1672 1673 pcie_noc: interconnect@16c0000 { 1674 compatible = "qcom,sm8550-pcie-anoc"; 1675 reg = <0 0x016c0000 0 0x12200>; 1676 #interconnect-cells = <2>; 1677 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1678 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1679 qcom,bcm-voters = <&apps_bcm_voter>; 1680 }; 1681 1682 aggre1_noc: interconnect@16e0000 { 1683 compatible = "qcom,sm8550-aggre1-noc"; 1684 reg = <0 0x016e0000 0 0x14400>; 1685 #interconnect-cells = <2>; 1686 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1687 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1688 qcom,bcm-voters = <&apps_bcm_voter>; 1689 }; 1690 1691 aggre2_noc: interconnect@1700000 { 1692 compatible = "qcom,sm8550-aggre2-noc"; 1693 reg = <0 0x01700000 0 0x1e400>; 1694 #interconnect-cells = <2>; 1695 clocks = <&rpmhcc RPMH_IPA_CLK>; 1696 qcom,bcm-voters = <&apps_bcm_voter>; 1697 }; 1698 1699 mmss_noc: interconnect@1780000 { 1700 compatible = "qcom,sm8550-mmss-noc"; 1701 reg = <0 0x01780000 0 0x5b800>; 1702 #interconnect-cells = <2>; 1703 qcom,bcm-voters = <&apps_bcm_voter>; 1704 }; 1705 1706 rng: rng@10c3000 { 1707 compatible = "qcom,sm8550-trng", "qcom,trng"; 1708 reg = <0 0x010c3000 0 0x1000>; 1709 }; 1710 1711 pcie0: pcie@1c00000 { 1712 device_type = "pci"; 1713 compatible = "qcom,pcie-sm8550"; 1714 reg = <0 0x01c00000 0 0x3000>, 1715 <0 0x60000000 0 0xf1d>, 1716 <0 0x60000f20 0 0xa8>, 1717 <0 0x60001000 0 0x1000>, 1718 <0 0x60100000 0 0x100000>; 1719 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1720 #address-cells = <3>; 1721 #size-cells = <2>; 1722 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1723 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1724 bus-range = <0x00 0xff>; 1725 1726 dma-coherent; 1727 1728 linux,pci-domain = <0>; 1729 num-lanes = <2>; 1730 1731 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1740 interrupt-names = "msi0", 1741 "msi1", 1742 "msi2", 1743 "msi3", 1744 "msi4", 1745 "msi5", 1746 "msi6", 1747 "msi7", 1748 "global"; 1749 #interrupt-cells = <1>; 1750 interrupt-map-mask = <0 0 0 0x7>; 1751 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1752 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1753 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1754 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1755 1756 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1757 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1758 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1759 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1760 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1761 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1762 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; 1763 clock-names = "aux", 1764 "cfg", 1765 "bus_master", 1766 "bus_slave", 1767 "slave_q2a", 1768 "ddrss_sf_tbu", 1769 "noc_aggr"; 1770 1771 interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 1772 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; 1773 interconnect-names = "pcie-mem", "cpu-pcie"; 1774 1775 msi-map = <0x0 &gic_its 0x1400 0x1>, 1776 <0x100 &gic_its 0x1401 0x1>; 1777 iommu-map = <0x0 &apps_smmu 0x1400 0x1>, 1778 <0x100 &apps_smmu 0x1401 0x1>; 1779 1780 resets = <&gcc GCC_PCIE_0_BCR>; 1781 reset-names = "pci"; 1782 1783 power-domains = <&gcc PCIE_0_GDSC>; 1784 1785 phys = <&pcie0_phy>; 1786 phy-names = "pciephy"; 1787 1788 status = "disabled"; 1789 1790 pcieport0: pcie@0 { 1791 device_type = "pci"; 1792 reg = <0x0 0x0 0x0 0x0 0x0>; 1793 bus-range = <0x01 0xff>; 1794 1795 #address-cells = <3>; 1796 #size-cells = <2>; 1797 ranges; 1798 }; 1799 }; 1800 1801 pcie0_phy: phy@1c06000 { 1802 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; 1803 reg = <0 0x01c06000 0 0x2000>; 1804 1805 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1806 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1807 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 1808 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 1809 <&gcc GCC_PCIE_0_PIPE_CLK>; 1810 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1811 "pipe"; 1812 1813 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1814 reset-names = "phy"; 1815 1816 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1817 assigned-clock-rates = <100000000>; 1818 1819 power-domains = <&gcc PCIE_0_PHY_GDSC>; 1820 1821 #clock-cells = <0>; 1822 clock-output-names = "pcie0_pipe_clk"; 1823 1824 #phy-cells = <0>; 1825 1826 status = "disabled"; 1827 }; 1828 1829 pcie1: pcie@1c08000 { 1830 device_type = "pci"; 1831 compatible = "qcom,pcie-sm8550"; 1832 reg = <0x0 0x01c08000 0x0 0x3000>, 1833 <0x0 0x40000000 0x0 0xf1d>, 1834 <0x0 0x40000f20 0x0 0xa8>, 1835 <0x0 0x40001000 0x0 0x1000>, 1836 <0x0 0x40100000 0x0 0x100000>; 1837 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1838 #address-cells = <3>; 1839 #size-cells = <2>; 1840 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1841 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1842 bus-range = <0x00 0xff>; 1843 1844 dma-coherent; 1845 1846 linux,pci-domain = <1>; 1847 num-lanes = <2>; 1848 1849 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 1858 interrupt-names = "msi0", 1859 "msi1", 1860 "msi2", 1861 "msi3", 1862 "msi4", 1863 "msi5", 1864 "msi6", 1865 "msi7", 1866 "global"; 1867 #interrupt-cells = <1>; 1868 interrupt-map-mask = <0 0 0 0x7>; 1869 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1870 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1871 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1872 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1873 1874 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1875 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1876 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1877 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1878 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1879 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1880 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1881 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 1882 clock-names = "aux", 1883 "cfg", 1884 "bus_master", 1885 "bus_slave", 1886 "slave_q2a", 1887 "ddrss_sf_tbu", 1888 "noc_aggr", 1889 "cnoc_sf_axi"; 1890 1891 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1892 assigned-clock-rates = <19200000>; 1893 1894 interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 1895 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; 1896 interconnect-names = "pcie-mem", "cpu-pcie"; 1897 1898 msi-map = <0x0 &gic_its 0x1480 0x1>, 1899 <0x100 &gic_its 0x1481 0x1>; 1900 iommu-map = <0x0 &apps_smmu 0x1480 0x1>, 1901 <0x100 &apps_smmu 0x1481 0x1>; 1902 1903 resets = <&gcc GCC_PCIE_1_BCR>, 1904 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 1905 reset-names = "pci", "link_down"; 1906 1907 power-domains = <&gcc PCIE_1_GDSC>; 1908 1909 phys = <&pcie1_phy>; 1910 phy-names = "pciephy"; 1911 1912 status = "disabled"; 1913 1914 pcie@0 { 1915 device_type = "pci"; 1916 reg = <0x0 0x0 0x0 0x0 0x0>; 1917 bus-range = <0x01 0xff>; 1918 1919 #address-cells = <3>; 1920 #size-cells = <2>; 1921 ranges; 1922 }; 1923 }; 1924 1925 pcie1_phy: phy@1c0e000 { 1926 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; 1927 reg = <0x0 0x01c0e000 0x0 0x2000>; 1928 1929 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1930 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1931 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 1932 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 1933 <&gcc GCC_PCIE_1_PIPE_CLK>; 1934 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1935 "pipe"; 1936 1937 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 1938 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 1939 reset-names = "phy", "phy_nocsr"; 1940 1941 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1942 assigned-clock-rates = <100000000>; 1943 1944 power-domains = <&gcc PCIE_1_PHY_GDSC>; 1945 1946 #clock-cells = <1>; 1947 clock-output-names = "pcie1_pipe_clk"; 1948 1949 #phy-cells = <0>; 1950 1951 status = "disabled"; 1952 }; 1953 1954 cryptobam: dma-controller@1dc4000 { 1955 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1956 reg = <0x0 0x01dc4000 0x0 0x28000>; 1957 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1958 #dma-cells = <1>; 1959 qcom,ee = <0>; 1960 qcom,controlled-remotely; 1961 iommus = <&apps_smmu 0x480 0x0>, 1962 <&apps_smmu 0x481 0x0>; 1963 }; 1964 1965 crypto: crypto@1dfa000 { 1966 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce"; 1967 reg = <0x0 0x01dfa000 0x0 0x6000>; 1968 dmas = <&cryptobam 4>, <&cryptobam 5>; 1969 dma-names = "rx", "tx"; 1970 iommus = <&apps_smmu 0x480 0x0>, 1971 <&apps_smmu 0x481 0x0>; 1972 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1973 interconnect-names = "memory"; 1974 }; 1975 1976 ufs_mem_phy: phy@1d80000 { 1977 compatible = "qcom,sm8550-qmp-ufs-phy"; 1978 reg = <0x0 0x01d80000 0x0 0x2000>; 1979 clocks = <&rpmhcc RPMH_CXO_CLK>, 1980 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1981 <&tcsr TCSR_UFS_CLKREF_EN>; 1982 clock-names = "ref", 1983 "ref_aux", 1984 "qref"; 1985 1986 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 1987 1988 resets = <&ufs_mem_hc 0>; 1989 reset-names = "ufsphy"; 1990 1991 #clock-cells = <1>; 1992 #phy-cells = <0>; 1993 1994 status = "disabled"; 1995 }; 1996 1997 ufs_mem_hc: ufshc@1d84000 { 1998 compatible = "qcom,sm8550-ufshc", "qcom,ufshc", 1999 "jedec,ufs-2.0"; 2000 reg = <0x0 0x01d84000 0x0 0x3000>; 2001 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2002 phys = <&ufs_mem_phy>; 2003 phy-names = "ufsphy"; 2004 lanes-per-direction = <2>; 2005 #reset-cells = <1>; 2006 resets = <&gcc GCC_UFS_PHY_BCR>; 2007 reset-names = "rst"; 2008 2009 power-domains = <&gcc UFS_PHY_GDSC>; 2010 required-opps = <&rpmhpd_opp_nom>; 2011 2012 iommus = <&apps_smmu 0x60 0x0>; 2013 dma-coherent; 2014 2015 operating-points-v2 = <&ufs_opp_table>; 2016 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 2017 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 2018 2019 interconnect-names = "ufs-ddr", "cpu-ufs"; 2020 clock-names = "core_clk", 2021 "bus_aggr_clk", 2022 "iface_clk", 2023 "core_clk_unipro", 2024 "ref_clk", 2025 "tx_lane0_sync_clk", 2026 "rx_lane0_sync_clk", 2027 "rx_lane1_sync_clk"; 2028 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2029 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2030 <&gcc GCC_UFS_PHY_AHB_CLK>, 2031 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2032 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 2033 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2034 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2035 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2036 qcom,ice = <&ice>; 2037 2038 status = "disabled"; 2039 2040 ufs_opp_table: opp-table { 2041 compatible = "operating-points-v2"; 2042 2043 opp-75000000 { 2044 opp-hz = /bits/ 64 <75000000>, 2045 /bits/ 64 <0>, 2046 /bits/ 64 <0>, 2047 /bits/ 64 <75000000>, 2048 /bits/ 64 <0>, 2049 /bits/ 64 <0>, 2050 /bits/ 64 <0>, 2051 /bits/ 64 <0>; 2052 required-opps = <&rpmhpd_opp_low_svs>; 2053 }; 2054 2055 opp-150000000 { 2056 opp-hz = /bits/ 64 <150000000>, 2057 /bits/ 64 <0>, 2058 /bits/ 64 <0>, 2059 /bits/ 64 <150000000>, 2060 /bits/ 64 <0>, 2061 /bits/ 64 <0>, 2062 /bits/ 64 <0>, 2063 /bits/ 64 <0>; 2064 required-opps = <&rpmhpd_opp_svs>; 2065 }; 2066 2067 opp-300000000 { 2068 opp-hz = /bits/ 64 <300000000>, 2069 /bits/ 64 <0>, 2070 /bits/ 64 <0>, 2071 /bits/ 64 <300000000>, 2072 /bits/ 64 <0>, 2073 /bits/ 64 <0>, 2074 /bits/ 64 <0>, 2075 /bits/ 64 <0>; 2076 required-opps = <&rpmhpd_opp_nom>; 2077 }; 2078 }; 2079 }; 2080 2081 ice: crypto@1d88000 { 2082 compatible = "qcom,sm8550-inline-crypto-engine", 2083 "qcom,inline-crypto-engine"; 2084 reg = <0 0x01d88000 0 0x18000>; 2085 2086 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2087 }; 2088 2089 tcsr_mutex: hwlock@1f40000 { 2090 compatible = "qcom,tcsr-mutex"; 2091 reg = <0 0x01f40000 0 0x20000>; 2092 #hwlock-cells = <1>; 2093 }; 2094 2095 tcsr: clock-controller@1fc0000 { 2096 compatible = "qcom,sm8550-tcsr", "syscon"; 2097 reg = <0 0x01fc0000 0 0x30000>; 2098 clocks = <&rpmhcc RPMH_CXO_CLK>; 2099 #clock-cells = <1>; 2100 #reset-cells = <1>; 2101 }; 2102 2103 gpu: gpu@3d00000 { 2104 compatible = "qcom,adreno-43050a01", "qcom,adreno"; 2105 reg = <0x0 0x03d00000 0x0 0x40000>, 2106 <0x0 0x03d9e000 0x0 0x1000>, 2107 <0x0 0x03d61000 0x0 0x800>; 2108 reg-names = "kgsl_3d0_reg_memory", 2109 "cx_mem", 2110 "cx_dbgc"; 2111 2112 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2113 2114 iommus = <&adreno_smmu 0 0x0>, 2115 <&adreno_smmu 1 0x0>; 2116 2117 operating-points-v2 = <&gpu_opp_table>; 2118 2119 qcom,gmu = <&gmu>; 2120 #cooling-cells = <2>; 2121 2122 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 2123 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2124 interconnect-names = "gfx-mem"; 2125 2126 status = "disabled"; 2127 2128 zap-shader { 2129 memory-region = <&gpu_micro_code_mem>; 2130 }; 2131 2132 /* Speedbin needs more work on A740+, keep only lower freqs */ 2133 gpu_opp_table: opp-table { 2134 compatible = "operating-points-v2"; 2135 2136 opp-680000000 { 2137 opp-hz = /bits/ 64 <680000000>; 2138 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2139 opp-peak-kBps = <16500000>; 2140 }; 2141 2142 opp-615000000 { 2143 opp-hz = /bits/ 64 <615000000>; 2144 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2145 opp-peak-kBps = <12449218>; 2146 }; 2147 2148 opp-550000000 { 2149 opp-hz = /bits/ 64 <550000000>; 2150 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2151 opp-peak-kBps = <10687500>; 2152 }; 2153 2154 opp-475000000 { 2155 opp-hz = /bits/ 64 <475000000>; 2156 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 2157 opp-peak-kBps = <6074218>; 2158 }; 2159 2160 opp-401000000 { 2161 opp-hz = /bits/ 64 <401000000>; 2162 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2163 opp-peak-kBps = <6074218>; 2164 }; 2165 2166 opp-348000000 { 2167 opp-hz = /bits/ 64 <348000000>; 2168 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 2169 opp-peak-kBps = <6074218>; 2170 }; 2171 2172 opp-295000000 { 2173 opp-hz = /bits/ 64 <295000000>; 2174 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2175 opp-peak-kBps = <6074218>; 2176 }; 2177 2178 opp-220000000 { 2179 opp-hz = /bits/ 64 <220000000>; 2180 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 2181 opp-peak-kBps = <2136718>; 2182 }; 2183 }; 2184 }; 2185 2186 gmu: gmu@3d6a000 { 2187 compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu"; 2188 reg = <0x0 0x03d6a000 0x0 0x35000>, 2189 <0x0 0x03d50000 0x0 0x10000>, 2190 <0x0 0x0b280000 0x0 0x10000>; 2191 reg-names = "gmu", "rscc", "gmu_pdc"; 2192 2193 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2194 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2195 interrupt-names = "hfi", "gmu"; 2196 2197 clocks = <&gpucc GPU_CC_AHB_CLK>, 2198 <&gpucc GPU_CC_CX_GMU_CLK>, 2199 <&gpucc GPU_CC_CXO_CLK>, 2200 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2201 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2202 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2203 <&gpucc GPU_CC_DEMET_CLK>; 2204 clock-names = "ahb", 2205 "gmu", 2206 "cxo", 2207 "axi", 2208 "memnoc", 2209 "hub", 2210 "demet"; 2211 2212 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2213 <&gpucc GPU_CC_GX_GDSC>; 2214 power-domain-names = "cx", 2215 "gx"; 2216 2217 iommus = <&adreno_smmu 5 0x0>; 2218 2219 qcom,qmp = <&aoss_qmp>; 2220 2221 operating-points-v2 = <&gmu_opp_table>; 2222 2223 gmu_opp_table: opp-table { 2224 compatible = "operating-points-v2"; 2225 2226 opp-500000000 { 2227 opp-hz = /bits/ 64 <500000000>; 2228 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2229 }; 2230 2231 opp-200000000 { 2232 opp-hz = /bits/ 64 <200000000>; 2233 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2234 }; 2235 }; 2236 }; 2237 2238 gpucc: clock-controller@3d90000 { 2239 compatible = "qcom,sm8550-gpucc"; 2240 reg = <0 0x03d90000 0 0xa000>; 2241 clocks = <&bi_tcxo_div2>, 2242 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2243 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2244 #clock-cells = <1>; 2245 #reset-cells = <1>; 2246 #power-domain-cells = <1>; 2247 }; 2248 2249 adreno_smmu: iommu@3da0000 { 2250 compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu", 2251 "qcom,smmu-500", "arm,mmu-500"; 2252 reg = <0x0 0x03da0000 0x0 0x40000>; 2253 #iommu-cells = <2>; 2254 #global-interrupts = <1>; 2255 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2256 <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>, 2257 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2258 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2259 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2260 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2261 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2262 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2263 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2264 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2265 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2266 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2267 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2268 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 2269 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 2270 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 2271 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2272 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 2273 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>, 2274 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, 2275 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>, 2276 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 2277 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 2278 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, 2279 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 2280 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 2281 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2282 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2283 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2284 <&gpucc GPU_CC_AHB_CLK>; 2285 clock-names = "hlos", 2286 "bus", 2287 "iface", 2288 "ahb"; 2289 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2290 dma-coherent; 2291 }; 2292 2293 ipa: ipa@3f40000 { 2294 compatible = "qcom,sm8550-ipa"; 2295 2296 iommus = <&apps_smmu 0x4a0 0x0>, 2297 <&apps_smmu 0x4a2 0x0>; 2298 reg = <0 0x3f40000 0 0x10000>, 2299 <0 0x3f50000 0 0x5000>, 2300 <0 0x3e04000 0 0xfc000>; 2301 reg-names = "ipa-reg", 2302 "ipa-shared", 2303 "gsi"; 2304 2305 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2306 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2307 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2308 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2309 interrupt-names = "ipa", 2310 "gsi", 2311 "ipa-clock-query", 2312 "ipa-setup-ready"; 2313 2314 clocks = <&rpmhcc RPMH_IPA_CLK>; 2315 clock-names = "core"; 2316 2317 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2318 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2319 interconnect-names = "memory", 2320 "config"; 2321 2322 qcom,qmp = <&aoss_qmp>; 2323 2324 qcom,smem-states = <&ipa_smp2p_out 0>, 2325 <&ipa_smp2p_out 1>; 2326 qcom,smem-state-names = "ipa-clock-enabled-valid", 2327 "ipa-clock-enabled"; 2328 2329 status = "disabled"; 2330 }; 2331 2332 remoteproc_mpss: remoteproc@4080000 { 2333 compatible = "qcom,sm8550-mpss-pas"; 2334 reg = <0x0 0x04080000 0x0 0x10000>; 2335 2336 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2337 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2338 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2339 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2340 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2341 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2342 interrupt-names = "wdog", "fatal", "ready", "handover", 2343 "stop-ack", "shutdown-ack"; 2344 2345 clocks = <&rpmhcc RPMH_CXO_CLK>; 2346 clock-names = "xo"; 2347 2348 power-domains = <&rpmhpd RPMHPD_CX>, 2349 <&rpmhpd RPMHPD_MSS>; 2350 power-domain-names = "cx", "mss"; 2351 2352 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2353 2354 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; 2355 2356 qcom,qmp = <&aoss_qmp>; 2357 2358 qcom,smem-states = <&smp2p_modem_out 0>; 2359 qcom,smem-state-names = "stop"; 2360 2361 status = "disabled"; 2362 2363 glink-edge { 2364 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2365 IPCC_MPROC_SIGNAL_GLINK_QMP 2366 IRQ_TYPE_EDGE_RISING>; 2367 mboxes = <&ipcc IPCC_CLIENT_MPSS 2368 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2369 label = "mpss"; 2370 qcom,remote-pid = <1>; 2371 }; 2372 }; 2373 2374 remoteproc_adsp: remoteproc@6800000 { 2375 compatible = "qcom,sm8550-adsp-pas"; 2376 reg = <0x0 0x06800000 0x0 0x10000>; 2377 2378 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2379 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2380 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2381 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2382 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2383 interrupt-names = "wdog", "fatal", "ready", 2384 "handover", "stop-ack"; 2385 2386 clocks = <&rpmhcc RPMH_CXO_CLK>; 2387 clock-names = "xo"; 2388 2389 power-domains = <&rpmhpd RPMHPD_LCX>, 2390 <&rpmhpd RPMHPD_LMX>; 2391 power-domain-names = "lcx", "lmx"; 2392 2393 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 2394 2395 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 2396 2397 qcom,qmp = <&aoss_qmp>; 2398 2399 qcom,smem-states = <&smp2p_adsp_out 0>; 2400 qcom,smem-state-names = "stop"; 2401 2402 status = "disabled"; 2403 2404 remoteproc_adsp_glink: glink-edge { 2405 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2406 IPCC_MPROC_SIGNAL_GLINK_QMP 2407 IRQ_TYPE_EDGE_RISING>; 2408 mboxes = <&ipcc IPCC_CLIENT_LPASS 2409 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2410 2411 label = "lpass"; 2412 qcom,remote-pid = <2>; 2413 2414 fastrpc { 2415 compatible = "qcom,fastrpc"; 2416 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2417 label = "adsp"; 2418 qcom,non-secure-domain; 2419 #address-cells = <1>; 2420 #size-cells = <0>; 2421 2422 compute-cb@3 { 2423 compatible = "qcom,fastrpc-compute-cb"; 2424 reg = <3>; 2425 iommus = <&apps_smmu 0x1003 0x80>, 2426 <&apps_smmu 0x1063 0x0>; 2427 dma-coherent; 2428 }; 2429 2430 compute-cb@4 { 2431 compatible = "qcom,fastrpc-compute-cb"; 2432 reg = <4>; 2433 iommus = <&apps_smmu 0x1004 0x80>, 2434 <&apps_smmu 0x1064 0x0>; 2435 dma-coherent; 2436 }; 2437 2438 compute-cb@5 { 2439 compatible = "qcom,fastrpc-compute-cb"; 2440 reg = <5>; 2441 iommus = <&apps_smmu 0x1005 0x80>, 2442 <&apps_smmu 0x1065 0x0>; 2443 dma-coherent; 2444 }; 2445 2446 compute-cb@6 { 2447 compatible = "qcom,fastrpc-compute-cb"; 2448 reg = <6>; 2449 iommus = <&apps_smmu 0x1006 0x80>, 2450 <&apps_smmu 0x1066 0x0>; 2451 dma-coherent; 2452 }; 2453 2454 compute-cb@7 { 2455 compatible = "qcom,fastrpc-compute-cb"; 2456 reg = <7>; 2457 iommus = <&apps_smmu 0x1007 0x80>, 2458 <&apps_smmu 0x1067 0x0>; 2459 dma-coherent; 2460 }; 2461 }; 2462 2463 gpr { 2464 compatible = "qcom,gpr"; 2465 qcom,glink-channels = "adsp_apps"; 2466 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2467 qcom,intents = <512 20>; 2468 #address-cells = <1>; 2469 #size-cells = <0>; 2470 2471 q6apm: service@1 { 2472 compatible = "qcom,q6apm"; 2473 reg = <GPR_APM_MODULE_IID>; 2474 #sound-dai-cells = <0>; 2475 qcom,protection-domain = "avs/audio", 2476 "msm/adsp/audio_pd"; 2477 2478 q6apmdai: dais { 2479 compatible = "qcom,q6apm-dais"; 2480 iommus = <&apps_smmu 0x1001 0x80>, 2481 <&apps_smmu 0x1061 0x0>; 2482 }; 2483 2484 q6apmbedai: bedais { 2485 compatible = "qcom,q6apm-lpass-dais"; 2486 #sound-dai-cells = <1>; 2487 }; 2488 }; 2489 2490 q6prm: service@2 { 2491 compatible = "qcom,q6prm"; 2492 reg = <GPR_PRM_MODULE_IID>; 2493 qcom,protection-domain = "avs/audio", 2494 "msm/adsp/audio_pd"; 2495 2496 q6prmcc: clock-controller { 2497 compatible = "qcom,q6prm-lpass-clocks"; 2498 #clock-cells = <2>; 2499 }; 2500 }; 2501 }; 2502 }; 2503 }; 2504 2505 lpass_wsa2macro: codec@6aa0000 { 2506 compatible = "qcom,sm8550-lpass-wsa-macro"; 2507 reg = <0 0x06aa0000 0 0x1000>; 2508 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2509 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2510 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2511 <&lpass_vamacro>; 2512 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2513 2514 #clock-cells = <0>; 2515 clock-output-names = "wsa2-mclk"; 2516 #sound-dai-cells = <1>; 2517 }; 2518 2519 swr3: soundwire@6ab0000 { 2520 compatible = "qcom,soundwire-v2.0.0"; 2521 reg = <0 0x06ab0000 0 0x10000>; 2522 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2523 clocks = <&lpass_wsa2macro>; 2524 clock-names = "iface"; 2525 label = "WSA2"; 2526 2527 pinctrl-0 = <&wsa2_swr_active>; 2528 pinctrl-names = "default"; 2529 2530 qcom,din-ports = <4>; 2531 qcom,dout-ports = <9>; 2532 2533 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2534 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2535 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2536 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2537 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2538 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2539 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2540 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2541 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2542 2543 #address-cells = <2>; 2544 #size-cells = <0>; 2545 #sound-dai-cells = <1>; 2546 status = "disabled"; 2547 }; 2548 2549 lpass_rxmacro: codec@6ac0000 { 2550 compatible = "qcom,sm8550-lpass-rx-macro"; 2551 reg = <0 0x06ac0000 0 0x1000>; 2552 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2553 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2554 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2555 <&lpass_vamacro>; 2556 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2557 2558 #clock-cells = <0>; 2559 clock-output-names = "mclk"; 2560 #sound-dai-cells = <1>; 2561 }; 2562 2563 swr1: soundwire@6ad0000 { 2564 compatible = "qcom,soundwire-v2.0.0"; 2565 reg = <0 0x06ad0000 0 0x10000>; 2566 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2567 clocks = <&lpass_rxmacro>; 2568 clock-names = "iface"; 2569 label = "RX"; 2570 2571 pinctrl-0 = <&rx_swr_active>; 2572 pinctrl-names = "default"; 2573 2574 qcom,din-ports = <1>; 2575 qcom,dout-ports = <11>; 2576 2577 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>; 2578 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2579 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2580 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; 2581 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; 2582 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>; 2583 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2584 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2585 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2586 2587 #address-cells = <2>; 2588 #size-cells = <0>; 2589 #sound-dai-cells = <1>; 2590 status = "disabled"; 2591 }; 2592 2593 lpass_txmacro: codec@6ae0000 { 2594 compatible = "qcom,sm8550-lpass-tx-macro"; 2595 reg = <0 0x06ae0000 0 0x1000>; 2596 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2597 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2598 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2599 <&lpass_vamacro>; 2600 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2601 2602 #clock-cells = <0>; 2603 clock-output-names = "mclk"; 2604 #sound-dai-cells = <1>; 2605 }; 2606 2607 lpass_wsamacro: codec@6b00000 { 2608 compatible = "qcom,sm8550-lpass-wsa-macro"; 2609 reg = <0 0x06b00000 0 0x1000>; 2610 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2611 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2612 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2613 <&lpass_vamacro>; 2614 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2615 2616 #clock-cells = <0>; 2617 clock-output-names = "mclk"; 2618 #sound-dai-cells = <1>; 2619 }; 2620 2621 swr0: soundwire@6b10000 { 2622 compatible = "qcom,soundwire-v2.0.0"; 2623 reg = <0 0x06b10000 0 0x10000>; 2624 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2625 clocks = <&lpass_wsamacro>; 2626 clock-names = "iface"; 2627 label = "WSA"; 2628 2629 pinctrl-0 = <&wsa_swr_active>; 2630 pinctrl-names = "default"; 2631 2632 qcom,din-ports = <4>; 2633 qcom,dout-ports = <9>; 2634 2635 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2636 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2637 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2638 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2639 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2640 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2641 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2642 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2643 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2644 2645 #address-cells = <2>; 2646 #size-cells = <0>; 2647 #sound-dai-cells = <1>; 2648 status = "disabled"; 2649 }; 2650 2651 swr2: soundwire@6d30000 { 2652 compatible = "qcom,soundwire-v2.0.0"; 2653 reg = <0 0x06d30000 0 0x10000>; 2654 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2655 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2656 interrupt-names = "core", "wakeup"; 2657 clocks = <&lpass_txmacro>; 2658 clock-names = "iface"; 2659 label = "TX"; 2660 2661 pinctrl-0 = <&tx_swr_active>; 2662 pinctrl-names = "default"; 2663 2664 qcom,din-ports = <4>; 2665 qcom,dout-ports = <0>; 2666 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2667 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2668 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2669 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2670 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2671 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2672 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2673 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2674 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2675 2676 #address-cells = <2>; 2677 #size-cells = <0>; 2678 #sound-dai-cells = <1>; 2679 status = "disabled"; 2680 }; 2681 2682 lpass_vamacro: codec@6d44000 { 2683 compatible = "qcom,sm8550-lpass-va-macro"; 2684 reg = <0 0x06d44000 0 0x1000>; 2685 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2686 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2687 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2688 clock-names = "mclk", "macro", "dcodec"; 2689 2690 #clock-cells = <0>; 2691 clock-output-names = "fsgen"; 2692 #sound-dai-cells = <1>; 2693 }; 2694 2695 lpass_tlmm: pinctrl@6e80000 { 2696 compatible = "qcom,sm8550-lpass-lpi-pinctrl"; 2697 reg = <0 0x06e80000 0 0x20000>, 2698 <0 0x07250000 0 0x10000>; 2699 gpio-controller; 2700 #gpio-cells = <2>; 2701 gpio-ranges = <&lpass_tlmm 0 0 23>; 2702 2703 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2704 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2705 clock-names = "core", "audio"; 2706 2707 tx_swr_active: tx-swr-active-state { 2708 clk-pins { 2709 pins = "gpio0"; 2710 function = "swr_tx_clk"; 2711 drive-strength = <2>; 2712 slew-rate = <1>; 2713 bias-disable; 2714 }; 2715 2716 data-pins { 2717 pins = "gpio1", "gpio2", "gpio14"; 2718 function = "swr_tx_data"; 2719 drive-strength = <2>; 2720 slew-rate = <1>; 2721 bias-bus-hold; 2722 }; 2723 }; 2724 2725 rx_swr_active: rx-swr-active-state { 2726 clk-pins { 2727 pins = "gpio3"; 2728 function = "swr_rx_clk"; 2729 drive-strength = <2>; 2730 slew-rate = <1>; 2731 bias-disable; 2732 }; 2733 2734 data-pins { 2735 pins = "gpio4", "gpio5"; 2736 function = "swr_rx_data"; 2737 drive-strength = <2>; 2738 slew-rate = <1>; 2739 bias-bus-hold; 2740 }; 2741 }; 2742 2743 dmic01_default: dmic01-default-state { 2744 clk-pins { 2745 pins = "gpio6"; 2746 function = "dmic1_clk"; 2747 drive-strength = <8>; 2748 output-high; 2749 }; 2750 2751 data-pins { 2752 pins = "gpio7"; 2753 function = "dmic1_data"; 2754 drive-strength = <8>; 2755 input-enable; 2756 }; 2757 }; 2758 2759 dmic23_default: dmic23-default-state { 2760 clk-pins { 2761 pins = "gpio8"; 2762 function = "dmic2_clk"; 2763 drive-strength = <8>; 2764 output-high; 2765 }; 2766 2767 data-pins { 2768 pins = "gpio9"; 2769 function = "dmic2_data"; 2770 drive-strength = <8>; 2771 input-enable; 2772 }; 2773 }; 2774 2775 wsa_swr_active: wsa-swr-active-state { 2776 clk-pins { 2777 pins = "gpio10"; 2778 function = "wsa_swr_clk"; 2779 drive-strength = <2>; 2780 slew-rate = <1>; 2781 bias-disable; 2782 }; 2783 2784 data-pins { 2785 pins = "gpio11"; 2786 function = "wsa_swr_data"; 2787 drive-strength = <2>; 2788 slew-rate = <1>; 2789 bias-bus-hold; 2790 }; 2791 }; 2792 2793 wsa2_swr_active: wsa2-swr-active-state { 2794 clk-pins { 2795 pins = "gpio15"; 2796 function = "wsa2_swr_clk"; 2797 drive-strength = <2>; 2798 slew-rate = <1>; 2799 bias-disable; 2800 }; 2801 2802 data-pins { 2803 pins = "gpio16"; 2804 function = "wsa2_swr_data"; 2805 drive-strength = <2>; 2806 slew-rate = <1>; 2807 bias-bus-hold; 2808 }; 2809 }; 2810 }; 2811 2812 lpass_lpiaon_noc: interconnect@7400000 { 2813 compatible = "qcom,sm8550-lpass-lpiaon-noc"; 2814 reg = <0 0x07400000 0 0x19080>; 2815 #interconnect-cells = <2>; 2816 qcom,bcm-voters = <&apps_bcm_voter>; 2817 }; 2818 2819 lpass_lpicx_noc: interconnect@7430000 { 2820 compatible = "qcom,sm8550-lpass-lpicx-noc"; 2821 reg = <0 0x07430000 0 0x3a200>; 2822 #interconnect-cells = <2>; 2823 qcom,bcm-voters = <&apps_bcm_voter>; 2824 }; 2825 2826 lpass_ag_noc: interconnect@7e40000 { 2827 compatible = "qcom,sm8550-lpass-ag-noc"; 2828 reg = <0 0x07e40000 0 0xe080>; 2829 #interconnect-cells = <2>; 2830 qcom,bcm-voters = <&apps_bcm_voter>; 2831 }; 2832 2833 sdhc_2: mmc@8804000 { 2834 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; 2835 reg = <0 0x08804000 0 0x1000>; 2836 2837 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2838 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2839 interrupt-names = "hc_irq", "pwr_irq"; 2840 2841 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2842 <&gcc GCC_SDCC2_APPS_CLK>, 2843 <&rpmhcc RPMH_CXO_CLK>; 2844 clock-names = "iface", "core", "xo"; 2845 iommus = <&apps_smmu 0x540 0>; 2846 qcom,dll-config = <0x0007642c>; 2847 qcom,ddr-config = <0x80040868>; 2848 power-domains = <&rpmhpd RPMHPD_CX>; 2849 operating-points-v2 = <&sdhc2_opp_table>; 2850 2851 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2852 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2853 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 2854 bus-width = <4>; 2855 dma-coherent; 2856 2857 /* Forbid SDR104/SDR50 - broken hw! */ 2858 sdhci-caps-mask = <0x3 0>; 2859 2860 status = "disabled"; 2861 2862 sdhc2_opp_table: opp-table { 2863 compatible = "operating-points-v2"; 2864 2865 opp-19200000 { 2866 opp-hz = /bits/ 64 <19200000>; 2867 required-opps = <&rpmhpd_opp_min_svs>; 2868 }; 2869 2870 opp-50000000 { 2871 opp-hz = /bits/ 64 <50000000>; 2872 required-opps = <&rpmhpd_opp_low_svs>; 2873 }; 2874 2875 opp-100000000 { 2876 opp-hz = /bits/ 64 <100000000>; 2877 required-opps = <&rpmhpd_opp_svs>; 2878 }; 2879 2880 opp-202000000 { 2881 opp-hz = /bits/ 64 <202000000>; 2882 required-opps = <&rpmhpd_opp_svs_l1>; 2883 }; 2884 }; 2885 }; 2886 2887 videocc: clock-controller@aaf0000 { 2888 compatible = "qcom,sm8550-videocc"; 2889 reg = <0 0x0aaf0000 0 0x10000>; 2890 clocks = <&bi_tcxo_div2>, 2891 <&gcc GCC_VIDEO_AHB_CLK>; 2892 power-domains = <&rpmhpd RPMHPD_MMCX>; 2893 required-opps = <&rpmhpd_opp_low_svs>; 2894 #clock-cells = <1>; 2895 #reset-cells = <1>; 2896 #power-domain-cells = <1>; 2897 }; 2898 2899 cci0: cci@ac15000 { 2900 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; 2901 reg = <0 0x0ac15000 0 0x1000>; 2902 interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>; 2903 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 2904 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2905 <&camcc CAM_CC_CPAS_AHB_CLK>, 2906 <&camcc CAM_CC_CCI_0_CLK>; 2907 clock-names = "camnoc_axi", 2908 "cpas_ahb", 2909 "cci"; 2910 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 2911 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 2912 pinctrl-names = "default", "sleep"; 2913 status = "disabled"; 2914 #address-cells = <1>; 2915 #size-cells = <0>; 2916 2917 cci0_i2c0: i2c-bus@0 { 2918 reg = <0>; 2919 clock-frequency = <1000000>; 2920 #address-cells = <1>; 2921 #size-cells = <0>; 2922 }; 2923 2924 cci0_i2c1: i2c-bus@1 { 2925 reg = <1>; 2926 clock-frequency = <1000000>; 2927 #address-cells = <1>; 2928 #size-cells = <0>; 2929 }; 2930 }; 2931 2932 cci1: cci@ac16000 { 2933 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; 2934 reg = <0 0x0ac16000 0 0x1000>; 2935 interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>; 2936 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 2937 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2938 <&camcc CAM_CC_CPAS_AHB_CLK>, 2939 <&camcc CAM_CC_CCI_1_CLK>; 2940 clock-names = "camnoc_axi", 2941 "cpas_ahb", 2942 "cci"; 2943 pinctrl-0 = <&cci1_0_default>; 2944 pinctrl-1 = <&cci1_0_sleep>; 2945 pinctrl-names = "default", "sleep"; 2946 status = "disabled"; 2947 #address-cells = <1>; 2948 #size-cells = <0>; 2949 2950 cci1_i2c0: i2c-bus@0 { 2951 reg = <0>; 2952 clock-frequency = <1000000>; 2953 #address-cells = <1>; 2954 #size-cells = <0>; 2955 }; 2956 }; 2957 2958 cci2: cci@ac17000 { 2959 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; 2960 reg = <0 0x0ac17000 0 0x1000>; 2961 interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>; 2962 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 2963 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2964 <&camcc CAM_CC_CPAS_AHB_CLK>, 2965 <&camcc CAM_CC_CCI_2_CLK>; 2966 clock-names = "camnoc_axi", 2967 "cpas_ahb", 2968 "cci"; 2969 pinctrl-0 = <&cci2_0_default &cci2_1_default>; 2970 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; 2971 pinctrl-names = "default", "sleep"; 2972 status = "disabled"; 2973 #address-cells = <1>; 2974 #size-cells = <0>; 2975 2976 cci2_i2c0: i2c-bus@0 { 2977 reg = <0>; 2978 clock-frequency = <1000000>; 2979 #address-cells = <1>; 2980 #size-cells = <0>; 2981 }; 2982 2983 cci2_i2c1: i2c-bus@1 { 2984 reg = <1>; 2985 clock-frequency = <1000000>; 2986 #address-cells = <1>; 2987 #size-cells = <0>; 2988 }; 2989 }; 2990 2991 camcc: clock-controller@ade0000 { 2992 compatible = "qcom,sm8550-camcc"; 2993 reg = <0 0x0ade0000 0 0x20000>; 2994 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2995 <&bi_tcxo_div2>, 2996 <&bi_tcxo_ao_div2>, 2997 <&sleep_clk>; 2998 power-domains = <&rpmhpd SM8550_MMCX>; 2999 required-opps = <&rpmhpd_opp_low_svs>; 3000 #clock-cells = <1>; 3001 #reset-cells = <1>; 3002 #power-domain-cells = <1>; 3003 }; 3004 3005 mdss: display-subsystem@ae00000 { 3006 compatible = "qcom,sm8550-mdss"; 3007 reg = <0 0x0ae00000 0 0x1000>; 3008 reg-names = "mdss"; 3009 3010 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3011 interrupt-controller; 3012 #interrupt-cells = <1>; 3013 3014 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3015 <&gcc GCC_DISP_AHB_CLK>, 3016 <&gcc GCC_DISP_HF_AXI_CLK>, 3017 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3018 3019 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 3020 3021 power-domains = <&dispcc MDSS_GDSC>; 3022 3023 interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>; 3024 interconnect-names = "mdp0-mem"; 3025 3026 iommus = <&apps_smmu 0x1c00 0x2>; 3027 3028 #address-cells = <2>; 3029 #size-cells = <2>; 3030 ranges; 3031 3032 status = "disabled"; 3033 3034 mdss_mdp: display-controller@ae01000 { 3035 compatible = "qcom,sm8550-dpu"; 3036 reg = <0 0x0ae01000 0 0x8f000>, 3037 <0 0x0aeb0000 0 0x2008>; 3038 reg-names = "mdp", "vbif"; 3039 3040 interrupt-parent = <&mdss>; 3041 interrupts = <0>; 3042 3043 clocks = <&gcc GCC_DISP_AHB_CLK>, 3044 <&gcc GCC_DISP_HF_AXI_CLK>, 3045 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3046 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3047 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3048 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3049 clock-names = "bus", 3050 "nrt_bus", 3051 "iface", 3052 "lut", 3053 "core", 3054 "vsync"; 3055 3056 power-domains = <&rpmhpd RPMHPD_MMCX>; 3057 3058 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3059 assigned-clock-rates = <19200000>; 3060 3061 operating-points-v2 = <&mdp_opp_table>; 3062 3063 ports { 3064 #address-cells = <1>; 3065 #size-cells = <0>; 3066 3067 port@0 { 3068 reg = <0>; 3069 dpu_intf1_out: endpoint { 3070 remote-endpoint = <&mdss_dsi0_in>; 3071 }; 3072 }; 3073 3074 port@1 { 3075 reg = <1>; 3076 dpu_intf2_out: endpoint { 3077 remote-endpoint = <&mdss_dsi1_in>; 3078 }; 3079 }; 3080 3081 port@2 { 3082 reg = <2>; 3083 dpu_intf0_out: endpoint { 3084 remote-endpoint = <&mdss_dp0_in>; 3085 }; 3086 }; 3087 }; 3088 3089 mdp_opp_table: opp-table { 3090 compatible = "operating-points-v2"; 3091 3092 opp-200000000 { 3093 opp-hz = /bits/ 64 <200000000>; 3094 required-opps = <&rpmhpd_opp_low_svs>; 3095 }; 3096 3097 opp-325000000 { 3098 opp-hz = /bits/ 64 <325000000>; 3099 required-opps = <&rpmhpd_opp_svs>; 3100 }; 3101 3102 opp-375000000 { 3103 opp-hz = /bits/ 64 <375000000>; 3104 required-opps = <&rpmhpd_opp_svs_l1>; 3105 }; 3106 3107 opp-514000000 { 3108 opp-hz = /bits/ 64 <514000000>; 3109 required-opps = <&rpmhpd_opp_nom>; 3110 }; 3111 }; 3112 }; 3113 3114 mdss_dp0: displayport-controller@ae90000 { 3115 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp"; 3116 reg = <0 0xae90000 0 0x200>, 3117 <0 0xae90200 0 0x200>, 3118 <0 0xae90400 0 0xc00>, 3119 <0 0xae91000 0 0x400>, 3120 <0 0xae91400 0 0x400>; 3121 interrupt-parent = <&mdss>; 3122 interrupts = <12>; 3123 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3124 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 3125 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 3126 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3127 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3128 clock-names = "core_iface", 3129 "core_aux", 3130 "ctrl_link", 3131 "ctrl_link_iface", 3132 "stream_pixel"; 3133 3134 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3135 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3136 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3137 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3138 3139 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 3140 phy-names = "dp"; 3141 3142 #sound-dai-cells = <0>; 3143 3144 operating-points-v2 = <&dp_opp_table>; 3145 power-domains = <&rpmhpd RPMHPD_MMCX>; 3146 3147 status = "disabled"; 3148 3149 ports { 3150 #address-cells = <1>; 3151 #size-cells = <0>; 3152 3153 port@0 { 3154 reg = <0>; 3155 mdss_dp0_in: endpoint { 3156 remote-endpoint = <&dpu_intf0_out>; 3157 }; 3158 }; 3159 3160 port@1 { 3161 reg = <1>; 3162 mdss_dp0_out: endpoint { 3163 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 3164 }; 3165 }; 3166 }; 3167 3168 dp_opp_table: opp-table { 3169 compatible = "operating-points-v2"; 3170 3171 opp-162000000 { 3172 opp-hz = /bits/ 64 <162000000>; 3173 required-opps = <&rpmhpd_opp_low_svs_d1>; 3174 }; 3175 3176 opp-270000000 { 3177 opp-hz = /bits/ 64 <270000000>; 3178 required-opps = <&rpmhpd_opp_low_svs>; 3179 }; 3180 3181 opp-540000000 { 3182 opp-hz = /bits/ 64 <540000000>; 3183 required-opps = <&rpmhpd_opp_svs_l1>; 3184 }; 3185 3186 opp-810000000 { 3187 opp-hz = /bits/ 64 <810000000>; 3188 required-opps = <&rpmhpd_opp_nom>; 3189 }; 3190 }; 3191 }; 3192 3193 mdss_dsi0: dsi@ae94000 { 3194 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3195 reg = <0 0x0ae94000 0 0x400>; 3196 reg-names = "dsi_ctrl"; 3197 3198 interrupt-parent = <&mdss>; 3199 interrupts = <4>; 3200 3201 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3202 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3203 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3204 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3205 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3206 <&gcc GCC_DISP_HF_AXI_CLK>; 3207 clock-names = "byte", 3208 "byte_intf", 3209 "pixel", 3210 "core", 3211 "iface", 3212 "bus"; 3213 3214 power-domains = <&rpmhpd RPMHPD_MMCX>; 3215 3216 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3217 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3218 assigned-clock-parents = <&mdss_dsi0_phy 0>, 3219 <&mdss_dsi0_phy 1>; 3220 3221 operating-points-v2 = <&mdss_dsi_opp_table>; 3222 3223 phys = <&mdss_dsi0_phy>; 3224 phy-names = "dsi"; 3225 3226 #address-cells = <1>; 3227 #size-cells = <0>; 3228 3229 status = "disabled"; 3230 3231 ports { 3232 #address-cells = <1>; 3233 #size-cells = <0>; 3234 3235 port@0 { 3236 reg = <0>; 3237 mdss_dsi0_in: endpoint { 3238 remote-endpoint = <&dpu_intf1_out>; 3239 }; 3240 }; 3241 3242 port@1 { 3243 reg = <1>; 3244 mdss_dsi0_out: endpoint { 3245 }; 3246 }; 3247 }; 3248 3249 mdss_dsi_opp_table: opp-table { 3250 compatible = "operating-points-v2"; 3251 3252 opp-187500000 { 3253 opp-hz = /bits/ 64 <187500000>; 3254 required-opps = <&rpmhpd_opp_low_svs>; 3255 }; 3256 3257 opp-300000000 { 3258 opp-hz = /bits/ 64 <300000000>; 3259 required-opps = <&rpmhpd_opp_svs>; 3260 }; 3261 3262 opp-358000000 { 3263 opp-hz = /bits/ 64 <358000000>; 3264 required-opps = <&rpmhpd_opp_svs_l1>; 3265 }; 3266 }; 3267 }; 3268 3269 mdss_dsi0_phy: phy@ae95000 { 3270 compatible = "qcom,sm8550-dsi-phy-4nm"; 3271 reg = <0 0x0ae95000 0 0x200>, 3272 <0 0x0ae95200 0 0x280>, 3273 <0 0x0ae95500 0 0x400>; 3274 reg-names = "dsi_phy", 3275 "dsi_phy_lane", 3276 "dsi_pll"; 3277 3278 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3279 <&rpmhcc RPMH_CXO_CLK>; 3280 clock-names = "iface", "ref"; 3281 3282 #clock-cells = <1>; 3283 #phy-cells = <0>; 3284 3285 status = "disabled"; 3286 }; 3287 3288 mdss_dsi1: dsi@ae96000 { 3289 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3290 reg = <0 0x0ae96000 0 0x400>; 3291 reg-names = "dsi_ctrl"; 3292 3293 interrupt-parent = <&mdss>; 3294 interrupts = <5>; 3295 3296 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3297 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3298 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3299 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3300 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3301 <&gcc GCC_DISP_HF_AXI_CLK>; 3302 clock-names = "byte", 3303 "byte_intf", 3304 "pixel", 3305 "core", 3306 "iface", 3307 "bus"; 3308 3309 power-domains = <&rpmhpd RPMHPD_MMCX>; 3310 3311 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3312 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3313 assigned-clock-parents = <&mdss_dsi1_phy 0>, 3314 <&mdss_dsi1_phy 1>; 3315 3316 operating-points-v2 = <&mdss_dsi_opp_table>; 3317 3318 phys = <&mdss_dsi1_phy>; 3319 phy-names = "dsi"; 3320 3321 #address-cells = <1>; 3322 #size-cells = <0>; 3323 3324 status = "disabled"; 3325 3326 ports { 3327 #address-cells = <1>; 3328 #size-cells = <0>; 3329 3330 port@0 { 3331 reg = <0>; 3332 mdss_dsi1_in: endpoint { 3333 remote-endpoint = <&dpu_intf2_out>; 3334 }; 3335 }; 3336 3337 port@1 { 3338 reg = <1>; 3339 mdss_dsi1_out: endpoint { 3340 }; 3341 }; 3342 }; 3343 }; 3344 3345 mdss_dsi1_phy: phy@ae97000 { 3346 compatible = "qcom,sm8550-dsi-phy-4nm"; 3347 reg = <0 0x0ae97000 0 0x200>, 3348 <0 0x0ae97200 0 0x280>, 3349 <0 0x0ae97500 0 0x400>; 3350 reg-names = "dsi_phy", 3351 "dsi_phy_lane", 3352 "dsi_pll"; 3353 3354 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3355 <&rpmhcc RPMH_CXO_CLK>; 3356 clock-names = "iface", "ref"; 3357 3358 #clock-cells = <1>; 3359 #phy-cells = <0>; 3360 3361 status = "disabled"; 3362 }; 3363 }; 3364 3365 dispcc: clock-controller@af00000 { 3366 compatible = "qcom,sm8550-dispcc"; 3367 reg = <0 0x0af00000 0 0x20000>; 3368 clocks = <&bi_tcxo_div2>, 3369 <&bi_tcxo_ao_div2>, 3370 <&gcc GCC_DISP_AHB_CLK>, 3371 <&sleep_clk>, 3372 <&mdss_dsi0_phy 0>, 3373 <&mdss_dsi0_phy 1>, 3374 <&mdss_dsi1_phy 0>, 3375 <&mdss_dsi1_phy 1>, 3376 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3377 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3378 <0>, /* dp1 */ 3379 <0>, 3380 <0>, /* dp2 */ 3381 <0>, 3382 <0>, /* dp3 */ 3383 <0>; 3384 power-domains = <&rpmhpd RPMHPD_MMCX>; 3385 required-opps = <&rpmhpd_opp_low_svs>; 3386 #clock-cells = <1>; 3387 #reset-cells = <1>; 3388 #power-domain-cells = <1>; 3389 }; 3390 3391 usb_1_hsphy: phy@88e3000 { 3392 compatible = "qcom,sm8550-snps-eusb2-phy"; 3393 reg = <0x0 0x088e3000 0x0 0x154>; 3394 #phy-cells = <0>; 3395 3396 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 3397 clock-names = "ref"; 3398 3399 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3400 3401 status = "disabled"; 3402 }; 3403 3404 usb_dp_qmpphy: phy@88e8000 { 3405 compatible = "qcom,sm8550-qmp-usb3-dp-phy"; 3406 reg = <0x0 0x088e8000 0x0 0x3000>; 3407 3408 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3409 <&rpmhcc RPMH_CXO_CLK>, 3410 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3411 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3412 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3413 3414 power-domains = <&gcc USB3_PHY_GDSC>; 3415 3416 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3417 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 3418 reset-names = "phy", "common"; 3419 3420 #clock-cells = <1>; 3421 #phy-cells = <1>; 3422 3423 orientation-switch; 3424 3425 status = "disabled"; 3426 3427 ports { 3428 #address-cells = <1>; 3429 #size-cells = <0>; 3430 3431 port@0 { 3432 reg = <0>; 3433 3434 usb_dp_qmpphy_out: endpoint { 3435 }; 3436 }; 3437 3438 port@1 { 3439 reg = <1>; 3440 3441 usb_dp_qmpphy_usb_ss_in: endpoint { 3442 remote-endpoint = <&usb_1_dwc3_ss>; 3443 }; 3444 }; 3445 3446 port@2 { 3447 reg = <2>; 3448 3449 usb_dp_qmpphy_dp_in: endpoint { 3450 remote-endpoint = <&mdss_dp0_out>; 3451 }; 3452 }; 3453 }; 3454 }; 3455 3456 usb_1: usb@a6f8800 { 3457 compatible = "qcom,sm8550-dwc3", "qcom,dwc3"; 3458 reg = <0x0 0x0a6f8800 0x0 0x400>; 3459 #address-cells = <2>; 3460 #size-cells = <2>; 3461 ranges; 3462 3463 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3464 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3465 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3466 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3467 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3468 <&tcsr TCSR_USB3_CLKREF_EN>; 3469 clock-names = "cfg_noc", 3470 "core", 3471 "iface", 3472 "sleep", 3473 "mock_utmi", 3474 "xo"; 3475 3476 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3477 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3478 assigned-clock-rates = <19200000>, <200000000>; 3479 3480 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3481 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3482 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3483 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3484 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3485 interrupt-names = "pwr_event", 3486 "hs_phy_irq", 3487 "dp_hs_phy_irq", 3488 "dm_hs_phy_irq", 3489 "ss_phy_irq"; 3490 3491 power-domains = <&gcc USB30_PRIM_GDSC>; 3492 required-opps = <&rpmhpd_opp_nom>; 3493 3494 resets = <&gcc GCC_USB30_PRIM_BCR>; 3495 3496 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3497 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3498 interconnect-names = "usb-ddr", "apps-usb"; 3499 3500 status = "disabled"; 3501 3502 usb_1_dwc3: usb@a600000 { 3503 compatible = "snps,dwc3"; 3504 reg = <0x0 0x0a600000 0x0 0xcd00>; 3505 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3506 iommus = <&apps_smmu 0x40 0x0>; 3507 phys = <&usb_1_hsphy>, 3508 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 3509 phy-names = "usb2-phy", "usb3-phy"; 3510 snps,hird-threshold = /bits/ 8 <0x0>; 3511 snps,usb2-gadget-lpm-disable; 3512 snps,dis_u2_susphy_quirk; 3513 snps,dis_enblslpm_quirk; 3514 snps,dis-u1-entry-quirk; 3515 snps,dis-u2-entry-quirk; 3516 snps,is-utmi-l1-suspend; 3517 snps,usb3_lpm_capable; 3518 snps,usb2-lpm-disable; 3519 snps,has-lpm-erratum; 3520 tx-fifo-resize; 3521 dma-coherent; 3522 usb-role-switch; 3523 3524 ports { 3525 #address-cells = <1>; 3526 #size-cells = <0>; 3527 3528 port@0 { 3529 reg = <0>; 3530 3531 usb_1_dwc3_hs: endpoint { 3532 }; 3533 }; 3534 3535 port@1 { 3536 reg = <1>; 3537 3538 usb_1_dwc3_ss: endpoint { 3539 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 3540 }; 3541 }; 3542 }; 3543 }; 3544 }; 3545 3546 pdc: interrupt-controller@b220000 { 3547 compatible = "qcom,sm8550-pdc", "qcom,pdc"; 3548 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3549 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3550 <125 63 1>, <126 716 12>, 3551 <138 251 5>; 3552 #interrupt-cells = <2>; 3553 interrupt-parent = <&intc>; 3554 interrupt-controller; 3555 }; 3556 3557 tsens0: thermal-sensor@c271000 { 3558 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3559 reg = <0 0x0c271000 0 0x1000>, /* TM */ 3560 <0 0x0c222000 0 0x1000>; /* SROT */ 3561 #qcom,sensors = <16>; 3562 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3563 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 3564 interrupt-names = "uplow", "critical"; 3565 #thermal-sensor-cells = <1>; 3566 }; 3567 3568 tsens1: thermal-sensor@c272000 { 3569 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3570 reg = <0 0x0c272000 0 0x1000>, /* TM */ 3571 <0 0x0c223000 0 0x1000>; /* SROT */ 3572 #qcom,sensors = <16>; 3573 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3574 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 3575 interrupt-names = "uplow", "critical"; 3576 #thermal-sensor-cells = <1>; 3577 }; 3578 3579 tsens2: thermal-sensor@c273000 { 3580 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3581 reg = <0 0x0c273000 0 0x1000>, /* TM */ 3582 <0 0x0c224000 0 0x1000>; /* SROT */ 3583 #qcom,sensors = <16>; 3584 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 3585 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 3586 interrupt-names = "uplow", "critical"; 3587 #thermal-sensor-cells = <1>; 3588 }; 3589 3590 aoss_qmp: power-management@c300000 { 3591 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; 3592 reg = <0 0x0c300000 0 0x400>; 3593 interrupt-parent = <&ipcc>; 3594 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3595 IRQ_TYPE_EDGE_RISING>; 3596 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3597 3598 #clock-cells = <0>; 3599 }; 3600 3601 sram@c3f0000 { 3602 compatible = "qcom,rpmh-stats"; 3603 reg = <0 0x0c3f0000 0 0x400>; 3604 }; 3605 3606 spmi_bus: spmi@c400000 { 3607 compatible = "qcom,spmi-pmic-arb"; 3608 reg = <0 0x0c400000 0 0x3000>, 3609 <0 0x0c500000 0 0x400000>, 3610 <0 0x0c440000 0 0x80000>, 3611 <0 0x0c4c0000 0 0x20000>, 3612 <0 0x0c42d000 0 0x4000>; 3613 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3614 interrupt-names = "periph_irq"; 3615 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3616 qcom,ee = <0>; 3617 qcom,channel = <0>; 3618 qcom,bus-id = <0>; 3619 #address-cells = <2>; 3620 #size-cells = <0>; 3621 interrupt-controller; 3622 #interrupt-cells = <4>; 3623 }; 3624 3625 tlmm: pinctrl@f100000 { 3626 compatible = "qcom,sm8550-tlmm"; 3627 reg = <0 0x0f100000 0 0x300000>; 3628 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3629 gpio-controller; 3630 #gpio-cells = <2>; 3631 interrupt-controller; 3632 #interrupt-cells = <2>; 3633 gpio-ranges = <&tlmm 0 0 211>; 3634 wakeup-parent = <&pdc>; 3635 3636 cci0_0_default: cci0-0-default-state { 3637 sda-pins { 3638 pins = "gpio110"; 3639 function = "cci_i2c_sda"; 3640 drive-strength = <2>; 3641 bias-pull-up = <2200>; 3642 }; 3643 3644 scl-pins { 3645 pins = "gpio111"; 3646 function = "cci_i2c_scl"; 3647 drive-strength = <2>; 3648 bias-pull-up = <2200>; 3649 }; 3650 }; 3651 3652 cci0_0_sleep: cci0-0-sleep-state { 3653 sda-pins { 3654 pins = "gpio110"; 3655 function = "cci_i2c_sda"; 3656 drive-strength = <2>; 3657 bias-pull-down; 3658 }; 3659 3660 scl-pins { 3661 pins = "gpio111"; 3662 function = "cci_i2c_scl"; 3663 drive-strength = <2>; 3664 bias-pull-down; 3665 }; 3666 }; 3667 3668 cci0_1_default: cci0-1-default-state { 3669 sda-pins { 3670 pins = "gpio112"; 3671 function = "cci_i2c_sda"; 3672 drive-strength = <2>; 3673 bias-pull-up = <2200>; 3674 }; 3675 3676 scl-pins { 3677 pins = "gpio113"; 3678 function = "cci_i2c_scl"; 3679 drive-strength = <2>; 3680 bias-pull-up = <2200>; 3681 }; 3682 }; 3683 3684 cci0_1_sleep: cci0-1-sleep-state { 3685 sda-pins { 3686 pins = "gpio112"; 3687 function = "cci_i2c_sda"; 3688 drive-strength = <2>; 3689 bias-pull-down; 3690 }; 3691 3692 scl-pins { 3693 pins = "gpio113"; 3694 function = "cci_i2c_scl"; 3695 drive-strength = <2>; 3696 bias-pull-down; 3697 }; 3698 }; 3699 3700 cci1_0_default: cci1-0-default-state { 3701 sda-pins { 3702 pins = "gpio114"; 3703 function = "cci_i2c_sda"; 3704 drive-strength = <2>; 3705 bias-pull-up = <2200>; 3706 }; 3707 3708 scl-pins { 3709 pins = "gpio115"; 3710 function = "cci_i2c_scl"; 3711 drive-strength = <2>; 3712 bias-pull-up = <2200>; 3713 }; 3714 }; 3715 3716 cci1_0_sleep: cci1-0-sleep-state { 3717 sda-pins { 3718 pins = "gpio114"; 3719 function = "cci_i2c_sda"; 3720 drive-strength = <2>; 3721 bias-pull-down; 3722 }; 3723 3724 scl-pins { 3725 pins = "gpio115"; 3726 function = "cci_i2c_scl"; 3727 drive-strength = <2>; 3728 bias-pull-down; 3729 }; 3730 }; 3731 3732 cci2_0_default: cci2-0-default-state { 3733 sda-pins { 3734 pins = "gpio74"; 3735 function = "cci_i2c_sda"; 3736 drive-strength = <2>; 3737 bias-pull-up = <2200>; 3738 }; 3739 3740 scl-pins { 3741 pins = "gpio75"; 3742 function = "cci_i2c_scl"; 3743 drive-strength = <2>; 3744 bias-pull-up = <2200>; 3745 }; 3746 }; 3747 3748 cci2_0_sleep: cci2-0-sleep-state { 3749 sda-pins { 3750 pins = "gpio74"; 3751 function = "cci_i2c_sda"; 3752 drive-strength = <2>; 3753 bias-pull-down; 3754 }; 3755 3756 scl-pins { 3757 pins = "gpio75"; 3758 function = "cci_i2c_scl"; 3759 drive-strength = <2>; 3760 bias-pull-down; 3761 }; 3762 }; 3763 3764 cci2_1_default: cci2-1-default-state { 3765 sda-pins { 3766 pins = "gpio0"; 3767 function = "cci_i2c_sda"; 3768 drive-strength = <2>; 3769 bias-pull-up = <2200>; 3770 }; 3771 3772 scl-pins { 3773 pins = "gpio1"; 3774 function = "cci_i2c_scl"; 3775 drive-strength = <2>; 3776 bias-pull-up = <2200>; 3777 }; 3778 }; 3779 3780 cci2_1_sleep: cci2-1-sleep-state { 3781 sda-pins { 3782 pins = "gpio0"; 3783 function = "cci_i2c_sda"; 3784 drive-strength = <2>; 3785 bias-pull-down; 3786 }; 3787 3788 scl-pins { 3789 pins = "gpio1"; 3790 function = "cci_i2c_scl"; 3791 drive-strength = <2>; 3792 bias-pull-down; 3793 }; 3794 }; 3795 3796 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 3797 /* SDA, SCL */ 3798 pins = "gpio16", "gpio17"; 3799 function = "i2chub0_se0"; 3800 drive-strength = <2>; 3801 bias-pull-up; 3802 }; 3803 3804 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 3805 /* SDA, SCL */ 3806 pins = "gpio18", "gpio19"; 3807 function = "i2chub0_se1"; 3808 drive-strength = <2>; 3809 bias-pull-up; 3810 }; 3811 3812 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 3813 /* SDA, SCL */ 3814 pins = "gpio20", "gpio21"; 3815 function = "i2chub0_se2"; 3816 drive-strength = <2>; 3817 bias-pull-up; 3818 }; 3819 3820 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 3821 /* SDA, SCL */ 3822 pins = "gpio22", "gpio23"; 3823 function = "i2chub0_se3"; 3824 drive-strength = <2>; 3825 bias-pull-up; 3826 }; 3827 3828 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 3829 /* SDA, SCL */ 3830 pins = "gpio4", "gpio5"; 3831 function = "i2chub0_se4"; 3832 drive-strength = <2>; 3833 bias-pull-up; 3834 }; 3835 3836 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 3837 /* SDA, SCL */ 3838 pins = "gpio6", "gpio7"; 3839 function = "i2chub0_se5"; 3840 drive-strength = <2>; 3841 bias-pull-up; 3842 }; 3843 3844 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 3845 /* SDA, SCL */ 3846 pins = "gpio8", "gpio9"; 3847 function = "i2chub0_se6"; 3848 drive-strength = <2>; 3849 bias-pull-up; 3850 }; 3851 3852 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 3853 /* SDA, SCL */ 3854 pins = "gpio10", "gpio11"; 3855 function = "i2chub0_se7"; 3856 drive-strength = <2>; 3857 bias-pull-up; 3858 }; 3859 3860 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 3861 /* SDA, SCL */ 3862 pins = "gpio206", "gpio207"; 3863 function = "i2chub0_se8"; 3864 drive-strength = <2>; 3865 bias-pull-up; 3866 }; 3867 3868 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 3869 /* SDA, SCL */ 3870 pins = "gpio84", "gpio85"; 3871 function = "i2chub0_se9"; 3872 drive-strength = <2>; 3873 bias-pull-up; 3874 }; 3875 3876 pcie0_default_state: pcie0-default-state { 3877 perst-pins { 3878 pins = "gpio94"; 3879 function = "gpio"; 3880 drive-strength = <2>; 3881 bias-pull-down; 3882 }; 3883 3884 clkreq-pins { 3885 pins = "gpio95"; 3886 function = "pcie0_clk_req_n"; 3887 drive-strength = <2>; 3888 bias-pull-up; 3889 }; 3890 3891 wake-pins { 3892 pins = "gpio96"; 3893 function = "gpio"; 3894 drive-strength = <2>; 3895 bias-pull-up; 3896 }; 3897 }; 3898 3899 pcie1_default_state: pcie1-default-state { 3900 perst-pins { 3901 pins = "gpio97"; 3902 function = "gpio"; 3903 drive-strength = <2>; 3904 bias-pull-down; 3905 }; 3906 3907 clkreq-pins { 3908 pins = "gpio98"; 3909 function = "pcie1_clk_req_n"; 3910 drive-strength = <2>; 3911 bias-pull-up; 3912 }; 3913 3914 wake-pins { 3915 pins = "gpio99"; 3916 function = "gpio"; 3917 drive-strength = <2>; 3918 bias-pull-up; 3919 }; 3920 }; 3921 3922 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3923 /* SDA, SCL */ 3924 pins = "gpio28", "gpio29"; 3925 function = "qup1_se0"; 3926 drive-strength = <2>; 3927 bias-pull-up = <2200>; 3928 }; 3929 3930 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3931 /* SDA, SCL */ 3932 pins = "gpio32", "gpio33"; 3933 function = "qup1_se1"; 3934 drive-strength = <2>; 3935 bias-pull-up = <2200>; 3936 }; 3937 3938 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3939 /* SDA, SCL */ 3940 pins = "gpio36", "gpio37"; 3941 function = "qup1_se2"; 3942 drive-strength = <2>; 3943 bias-pull-up = <2200>; 3944 }; 3945 3946 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3947 /* SDA, SCL */ 3948 pins = "gpio40", "gpio41"; 3949 function = "qup1_se3"; 3950 drive-strength = <2>; 3951 bias-pull-up = <2200>; 3952 }; 3953 3954 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3955 /* SDA, SCL */ 3956 pins = "gpio44", "gpio45"; 3957 function = "qup1_se4"; 3958 drive-strength = <2>; 3959 bias-pull-up = <2200>; 3960 }; 3961 3962 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3963 /* SDA, SCL */ 3964 pins = "gpio52", "gpio53"; 3965 function = "qup1_se5"; 3966 drive-strength = <2>; 3967 bias-pull-up = <2200>; 3968 }; 3969 3970 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3971 /* SDA, SCL */ 3972 pins = "gpio48", "gpio49"; 3973 function = "qup1_se6"; 3974 drive-strength = <2>; 3975 bias-pull-up = <2200>; 3976 }; 3977 3978 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3979 scl-pins { 3980 pins = "gpio57"; 3981 function = "qup2_se0_l1_mira"; 3982 drive-strength = <2>; 3983 bias-pull-up = <2200>; 3984 }; 3985 3986 sda-pins { 3987 pins = "gpio56"; 3988 function = "qup2_se0_l0_mira"; 3989 drive-strength = <2>; 3990 bias-pull-up = <2200>; 3991 }; 3992 }; 3993 3994 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3995 /* SDA, SCL */ 3996 pins = "gpio60", "gpio61"; 3997 function = "qup2_se1"; 3998 drive-strength = <2>; 3999 bias-pull-up = <2200>; 4000 }; 4001 4002 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4003 /* SDA, SCL */ 4004 pins = "gpio64", "gpio65"; 4005 function = "qup2_se2"; 4006 drive-strength = <2>; 4007 bias-pull-up = <2200>; 4008 }; 4009 4010 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4011 /* SDA, SCL */ 4012 pins = "gpio68", "gpio69"; 4013 function = "qup2_se3"; 4014 drive-strength = <2>; 4015 bias-pull-up = <2200>; 4016 }; 4017 4018 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4019 /* SDA, SCL */ 4020 pins = "gpio2", "gpio3"; 4021 function = "qup2_se4"; 4022 drive-strength = <2>; 4023 bias-pull-up = <2200>; 4024 }; 4025 4026 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4027 /* SDA, SCL */ 4028 pins = "gpio80", "gpio81"; 4029 function = "qup2_se5"; 4030 drive-strength = <2>; 4031 bias-pull-up = <2200>; 4032 }; 4033 4034 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4035 /* SDA, SCL */ 4036 pins = "gpio72", "gpio106"; 4037 function = "qup2_se7"; 4038 drive-strength = <2>; 4039 bias-pull-up = <2200>; 4040 }; 4041 4042 qup_spi0_cs: qup-spi0-cs-state { 4043 pins = "gpio31"; 4044 function = "qup1_se0"; 4045 drive-strength = <6>; 4046 bias-disable; 4047 }; 4048 4049 qup_spi0_data_clk: qup-spi0-data-clk-state { 4050 /* MISO, MOSI, CLK */ 4051 pins = "gpio28", "gpio29", "gpio30"; 4052 function = "qup1_se0"; 4053 drive-strength = <6>; 4054 bias-disable; 4055 }; 4056 4057 qup_spi1_cs: qup-spi1-cs-state { 4058 pins = "gpio35"; 4059 function = "qup1_se1"; 4060 drive-strength = <6>; 4061 bias-disable; 4062 }; 4063 4064 qup_spi1_data_clk: qup-spi1-data-clk-state { 4065 /* MISO, MOSI, CLK */ 4066 pins = "gpio32", "gpio33", "gpio34"; 4067 function = "qup1_se1"; 4068 drive-strength = <6>; 4069 bias-disable; 4070 }; 4071 4072 qup_spi2_cs: qup-spi2-cs-state { 4073 pins = "gpio39"; 4074 function = "qup1_se2"; 4075 drive-strength = <6>; 4076 bias-disable; 4077 }; 4078 4079 qup_spi2_data_clk: qup-spi2-data-clk-state { 4080 /* MISO, MOSI, CLK */ 4081 pins = "gpio36", "gpio37", "gpio38"; 4082 function = "qup1_se2"; 4083 drive-strength = <6>; 4084 bias-disable; 4085 }; 4086 4087 qup_spi3_cs: qup-spi3-cs-state { 4088 pins = "gpio43"; 4089 function = "qup1_se3"; 4090 drive-strength = <6>; 4091 bias-disable; 4092 }; 4093 4094 qup_spi3_data_clk: qup-spi3-data-clk-state { 4095 /* MISO, MOSI, CLK */ 4096 pins = "gpio40", "gpio41", "gpio42"; 4097 function = "qup1_se3"; 4098 drive-strength = <6>; 4099 bias-disable; 4100 }; 4101 4102 qup_spi4_cs: qup-spi4-cs-state { 4103 pins = "gpio47"; 4104 function = "qup1_se4"; 4105 drive-strength = <6>; 4106 bias-disable; 4107 }; 4108 4109 qup_spi4_data_clk: qup-spi4-data-clk-state { 4110 /* MISO, MOSI, CLK */ 4111 pins = "gpio44", "gpio45", "gpio46"; 4112 function = "qup1_se4"; 4113 drive-strength = <6>; 4114 bias-disable; 4115 }; 4116 4117 qup_spi5_cs: qup-spi5-cs-state { 4118 pins = "gpio55"; 4119 function = "qup1_se5"; 4120 drive-strength = <6>; 4121 bias-disable; 4122 }; 4123 4124 qup_spi5_data_clk: qup-spi5-data-clk-state { 4125 /* MISO, MOSI, CLK */ 4126 pins = "gpio52", "gpio53", "gpio54"; 4127 function = "qup1_se5"; 4128 drive-strength = <6>; 4129 bias-disable; 4130 }; 4131 4132 qup_spi6_cs: qup-spi6-cs-state { 4133 pins = "gpio51"; 4134 function = "qup1_se6"; 4135 drive-strength = <6>; 4136 bias-disable; 4137 }; 4138 4139 qup_spi6_data_clk: qup-spi6-data-clk-state { 4140 /* MISO, MOSI, CLK */ 4141 pins = "gpio48", "gpio49", "gpio50"; 4142 function = "qup1_se6"; 4143 drive-strength = <6>; 4144 bias-disable; 4145 }; 4146 4147 qup_spi8_cs: qup-spi8-cs-state { 4148 pins = "gpio59"; 4149 function = "qup2_se0_l3_mira"; 4150 drive-strength = <6>; 4151 bias-disable; 4152 }; 4153 4154 qup_spi8_data_clk: qup-spi8-data-clk-state { 4155 /* MISO, MOSI, CLK */ 4156 pins = "gpio56", "gpio57", "gpio58"; 4157 function = "qup2_se0_l2_mira"; 4158 drive-strength = <6>; 4159 bias-disable; 4160 }; 4161 4162 qup_spi9_cs: qup-spi9-cs-state { 4163 pins = "gpio63"; 4164 function = "qup2_se1"; 4165 drive-strength = <6>; 4166 bias-disable; 4167 }; 4168 4169 qup_spi9_data_clk: qup-spi9-data-clk-state { 4170 /* MISO, MOSI, CLK */ 4171 pins = "gpio60", "gpio61", "gpio62"; 4172 function = "qup2_se1"; 4173 drive-strength = <6>; 4174 bias-disable; 4175 }; 4176 4177 qup_spi10_cs: qup-spi10-cs-state { 4178 pins = "gpio67"; 4179 function = "qup2_se2"; 4180 drive-strength = <6>; 4181 bias-disable; 4182 }; 4183 4184 qup_spi10_data_clk: qup-spi10-data-clk-state { 4185 /* MISO, MOSI, CLK */ 4186 pins = "gpio64", "gpio65", "gpio66"; 4187 function = "qup2_se2"; 4188 drive-strength = <6>; 4189 bias-disable; 4190 }; 4191 4192 qup_spi11_cs: qup-spi11-cs-state { 4193 pins = "gpio71"; 4194 function = "qup2_se3"; 4195 drive-strength = <6>; 4196 bias-disable; 4197 }; 4198 4199 qup_spi11_data_clk: qup-spi11-data-clk-state { 4200 /* MISO, MOSI, CLK */ 4201 pins = "gpio68", "gpio69", "gpio70"; 4202 function = "qup2_se3"; 4203 drive-strength = <6>; 4204 bias-disable; 4205 }; 4206 4207 qup_spi12_cs: qup-spi12-cs-state { 4208 pins = "gpio119"; 4209 function = "qup2_se4"; 4210 drive-strength = <6>; 4211 bias-disable; 4212 }; 4213 4214 qup_spi12_data_clk: qup-spi12-data-clk-state { 4215 /* MISO, MOSI, CLK */ 4216 pins = "gpio2", "gpio3", "gpio118"; 4217 function = "qup2_se4"; 4218 drive-strength = <6>; 4219 bias-disable; 4220 }; 4221 4222 qup_spi13_cs: qup-spi13-cs-state { 4223 pins = "gpio83"; 4224 function = "qup2_se5"; 4225 drive-strength = <6>; 4226 bias-disable; 4227 }; 4228 4229 qup_spi13_data_clk: qup-spi13-data-clk-state { 4230 /* MISO, MOSI, CLK */ 4231 pins = "gpio80", "gpio81", "gpio82"; 4232 function = "qup2_se5"; 4233 drive-strength = <6>; 4234 bias-disable; 4235 }; 4236 4237 qup_spi15_cs: qup-spi15-cs-state { 4238 pins = "gpio75"; 4239 function = "qup2_se7"; 4240 drive-strength = <6>; 4241 bias-disable; 4242 }; 4243 4244 qup_spi15_data_clk: qup-spi15-data-clk-state { 4245 /* MISO, MOSI, CLK */ 4246 pins = "gpio72", "gpio106", "gpio74"; 4247 function = "qup2_se7"; 4248 drive-strength = <6>; 4249 bias-disable; 4250 }; 4251 4252 qup_uart7_default: qup-uart7-default-state { 4253 /* TX, RX */ 4254 pins = "gpio26", "gpio27"; 4255 function = "qup1_se7"; 4256 drive-strength = <2>; 4257 bias-disable; 4258 }; 4259 4260 qup_uart14_default: qup-uart14-default-state { 4261 /* TX, RX */ 4262 pins = "gpio78", "gpio79"; 4263 function = "qup2_se6"; 4264 drive-strength = <2>; 4265 bias-pull-up; 4266 }; 4267 4268 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 4269 /* CTS, RTS */ 4270 pins = "gpio76", "gpio77"; 4271 function = "qup2_se6"; 4272 drive-strength = <2>; 4273 bias-pull-down; 4274 }; 4275 4276 sdc2_sleep: sdc2-sleep-state { 4277 clk-pins { 4278 pins = "sdc2_clk"; 4279 bias-disable; 4280 drive-strength = <2>; 4281 }; 4282 4283 cmd-pins { 4284 pins = "sdc2_cmd"; 4285 bias-pull-up; 4286 drive-strength = <2>; 4287 }; 4288 4289 data-pins { 4290 pins = "sdc2_data"; 4291 bias-pull-up; 4292 drive-strength = <2>; 4293 }; 4294 }; 4295 4296 sdc2_default: sdc2-default-state { 4297 clk-pins { 4298 pins = "sdc2_clk"; 4299 bias-disable; 4300 drive-strength = <16>; 4301 }; 4302 4303 cmd-pins { 4304 pins = "sdc2_cmd"; 4305 bias-pull-up; 4306 drive-strength = <10>; 4307 }; 4308 4309 data-pins { 4310 pins = "sdc2_data"; 4311 bias-pull-up; 4312 drive-strength = <10>; 4313 }; 4314 }; 4315 }; 4316 4317 apps_smmu: iommu@15000000 { 4318 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4319 reg = <0 0x15000000 0 0x100000>; 4320 #iommu-cells = <2>; 4321 #global-interrupts = <1>; 4322 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4323 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4324 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4325 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4326 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4327 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4328 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4329 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4330 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4331 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4332 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4333 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4334 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4335 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4336 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4337 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4338 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4339 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4340 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4341 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4342 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4343 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4344 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4345 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4346 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4347 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4348 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4349 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4350 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4351 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4352 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4353 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4354 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4355 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4356 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4357 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4358 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4359 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4360 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4361 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4362 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4363 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4364 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4365 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4366 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4367 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4368 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4369 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4370 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4371 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4372 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4373 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4374 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4375 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4376 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4377 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4378 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4379 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4380 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4381 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4382 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4383 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4384 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4385 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4386 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4387 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4388 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4389 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4390 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4391 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4392 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4393 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4394 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4395 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4396 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4397 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4398 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4399 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4400 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4401 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4402 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4403 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4404 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4405 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4406 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4407 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 4408 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4409 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4410 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4411 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 4412 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4413 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4414 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4415 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4416 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4417 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4418 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 4419 dma-coherent; 4420 }; 4421 4422 intc: interrupt-controller@17100000 { 4423 compatible = "arm,gic-v3"; 4424 reg = <0 0x17100000 0 0x10000>, /* GICD */ 4425 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 4426 ranges; 4427 #interrupt-cells = <3>; 4428 interrupt-controller; 4429 #redistributor-regions = <1>; 4430 redistributor-stride = <0 0x40000>; 4431 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 4432 #address-cells = <2>; 4433 #size-cells = <2>; 4434 4435 gic_its: msi-controller@17140000 { 4436 compatible = "arm,gic-v3-its"; 4437 reg = <0 0x17140000 0 0x20000>; 4438 msi-controller; 4439 #msi-cells = <1>; 4440 }; 4441 }; 4442 4443 timer@17420000 { 4444 compatible = "arm,armv7-timer-mem"; 4445 reg = <0 0x17420000 0 0x1000>; 4446 ranges = <0 0 0 0x20000000>; 4447 #address-cells = <1>; 4448 #size-cells = <1>; 4449 4450 frame@17421000 { 4451 reg = <0x17421000 0x1000>, 4452 <0x17422000 0x1000>; 4453 frame-number = <0>; 4454 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4455 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4456 }; 4457 4458 frame@17423000 { 4459 reg = <0x17423000 0x1000>; 4460 frame-number = <1>; 4461 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4462 status = "disabled"; 4463 }; 4464 4465 frame@17425000 { 4466 reg = <0x17425000 0x1000>; 4467 frame-number = <2>; 4468 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4469 status = "disabled"; 4470 }; 4471 4472 frame@17427000 { 4473 reg = <0x17427000 0x1000>; 4474 frame-number = <3>; 4475 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4476 status = "disabled"; 4477 }; 4478 4479 frame@17429000 { 4480 reg = <0x17429000 0x1000>; 4481 frame-number = <4>; 4482 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4483 status = "disabled"; 4484 }; 4485 4486 frame@1742b000 { 4487 reg = <0x1742b000 0x1000>; 4488 frame-number = <5>; 4489 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4490 status = "disabled"; 4491 }; 4492 4493 frame@1742d000 { 4494 reg = <0x1742d000 0x1000>; 4495 frame-number = <6>; 4496 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4497 status = "disabled"; 4498 }; 4499 }; 4500 4501 apps_rsc: rsc@17a00000 { 4502 label = "apps_rsc"; 4503 compatible = "qcom,rpmh-rsc"; 4504 reg = <0 0x17a00000 0 0x10000>, 4505 <0 0x17a10000 0 0x10000>, 4506 <0 0x17a20000 0 0x10000>, 4507 <0 0x17a30000 0 0x10000>; 4508 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 4509 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4510 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4511 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4512 qcom,tcs-offset = <0xd00>; 4513 qcom,drv-id = <2>; 4514 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 4515 <WAKE_TCS 2>, <CONTROL_TCS 0>; 4516 power-domains = <&cluster_pd>; 4517 4518 apps_bcm_voter: bcm-voter { 4519 compatible = "qcom,bcm-voter"; 4520 }; 4521 4522 rpmhcc: clock-controller { 4523 compatible = "qcom,sm8550-rpmh-clk"; 4524 #clock-cells = <1>; 4525 clock-names = "xo"; 4526 clocks = <&xo_board>; 4527 }; 4528 4529 rpmhpd: power-controller { 4530 compatible = "qcom,sm8550-rpmhpd"; 4531 #power-domain-cells = <1>; 4532 operating-points-v2 = <&rpmhpd_opp_table>; 4533 4534 rpmhpd_opp_table: opp-table { 4535 compatible = "operating-points-v2"; 4536 4537 rpmhpd_opp_ret: opp-16 { 4538 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4539 }; 4540 4541 rpmhpd_opp_min_svs: opp-48 { 4542 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4543 }; 4544 4545 rpmhpd_opp_low_svs_d2: opp-52 { 4546 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 4547 }; 4548 4549 rpmhpd_opp_low_svs_d1: opp-56 { 4550 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4551 }; 4552 4553 rpmhpd_opp_low_svs_d0: opp-60 { 4554 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 4555 }; 4556 4557 rpmhpd_opp_low_svs: opp-64 { 4558 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4559 }; 4560 4561 rpmhpd_opp_low_svs_l1: opp-80 { 4562 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 4563 }; 4564 4565 rpmhpd_opp_svs: opp-128 { 4566 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4567 }; 4568 4569 rpmhpd_opp_svs_l0: opp-144 { 4570 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 4571 }; 4572 4573 rpmhpd_opp_svs_l1: opp-192 { 4574 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4575 }; 4576 4577 rpmhpd_opp_nom: opp-256 { 4578 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4579 }; 4580 4581 rpmhpd_opp_nom_l1: opp-320 { 4582 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4583 }; 4584 4585 rpmhpd_opp_nom_l2: opp-336 { 4586 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4587 }; 4588 4589 rpmhpd_opp_turbo: opp-384 { 4590 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4591 }; 4592 4593 rpmhpd_opp_turbo_l1: opp-416 { 4594 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4595 }; 4596 }; 4597 }; 4598 }; 4599 4600 cpufreq_hw: cpufreq@17d91000 { 4601 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; 4602 reg = <0 0x17d91000 0 0x1000>, 4603 <0 0x17d92000 0 0x1000>, 4604 <0 0x17d93000 0 0x1000>; 4605 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 4606 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 4607 clock-names = "xo", "alternate"; 4608 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 4609 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 4610 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 4611 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 4612 #freq-domain-cells = <1>; 4613 #clock-cells = <1>; 4614 }; 4615 4616 pmu@24091000 { 4617 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 4618 reg = <0 0x24091000 0 0x1000>; 4619 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 4620 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 4621 4622 operating-points-v2 = <&llcc_bwmon_opp_table>; 4623 4624 llcc_bwmon_opp_table: opp-table { 4625 compatible = "operating-points-v2"; 4626 4627 opp-0 { 4628 opp-peak-kBps = <2086000>; 4629 }; 4630 4631 opp-1 { 4632 opp-peak-kBps = <2929000>; 4633 }; 4634 4635 opp-2 { 4636 opp-peak-kBps = <5931000>; 4637 }; 4638 4639 opp-3 { 4640 opp-peak-kBps = <6515000>; 4641 }; 4642 4643 opp-4 { 4644 opp-peak-kBps = <7980000>; 4645 }; 4646 4647 opp-5 { 4648 opp-peak-kBps = <10437000>; 4649 }; 4650 4651 opp-6 { 4652 opp-peak-kBps = <12157000>; 4653 }; 4654 4655 opp-7 { 4656 opp-peak-kBps = <14060000>; 4657 }; 4658 4659 opp-8 { 4660 opp-peak-kBps = <16113000>; 4661 }; 4662 }; 4663 }; 4664 4665 pmu@240b6400 { 4666 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; 4667 reg = <0 0x240b6400 0 0x600>; 4668 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4669 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 4670 4671 operating-points-v2 = <&cpu_bwmon_opp_table>; 4672 4673 cpu_bwmon_opp_table: opp-table { 4674 compatible = "operating-points-v2"; 4675 4676 opp-0 { 4677 opp-peak-kBps = <4577000>; 4678 }; 4679 4680 opp-1 { 4681 opp-peak-kBps = <7110000>; 4682 }; 4683 4684 opp-2 { 4685 opp-peak-kBps = <9155000>; 4686 }; 4687 4688 opp-3 { 4689 opp-peak-kBps = <12298000>; 4690 }; 4691 4692 opp-4 { 4693 opp-peak-kBps = <14236000>; 4694 }; 4695 4696 opp-5 { 4697 opp-peak-kBps = <16265000>; 4698 }; 4699 }; 4700 }; 4701 4702 gem_noc: interconnect@24100000 { 4703 compatible = "qcom,sm8550-gem-noc"; 4704 reg = <0 0x24100000 0 0xbb800>; 4705 #interconnect-cells = <2>; 4706 qcom,bcm-voters = <&apps_bcm_voter>; 4707 }; 4708 4709 system-cache-controller@25000000 { 4710 compatible = "qcom,sm8550-llcc"; 4711 reg = <0 0x25000000 0 0x200000>, 4712 <0 0x25200000 0 0x200000>, 4713 <0 0x25400000 0 0x200000>, 4714 <0 0x25600000 0 0x200000>, 4715 <0 0x25800000 0 0x200000>, 4716 <0 0x25a00000 0 0x200000>; 4717 reg-names = "llcc0_base", 4718 "llcc1_base", 4719 "llcc2_base", 4720 "llcc3_base", 4721 "llcc_broadcast_base", 4722 "llcc_broadcast_and_base"; 4723 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 4724 }; 4725 4726 nsp_noc: interconnect@320c0000 { 4727 compatible = "qcom,sm8550-nsp-noc"; 4728 reg = <0 0x320c0000 0 0xe080>; 4729 #interconnect-cells = <2>; 4730 qcom,bcm-voters = <&apps_bcm_voter>; 4731 }; 4732 4733 remoteproc_cdsp: remoteproc@32300000 { 4734 compatible = "qcom,sm8550-cdsp-pas"; 4735 reg = <0x0 0x32300000 0x0 0x10000>; 4736 4737 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4738 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 4739 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 4740 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 4741 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 4742 interrupt-names = "wdog", "fatal", "ready", 4743 "handover", "stop-ack"; 4744 4745 clocks = <&rpmhcc RPMH_CXO_CLK>; 4746 clock-names = "xo"; 4747 4748 power-domains = <&rpmhpd RPMHPD_CX>, 4749 <&rpmhpd RPMHPD_MXC>, 4750 <&rpmhpd RPMHPD_NSP>; 4751 power-domain-names = "cx", "mxc", "nsp"; 4752 4753 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4754 4755 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 4756 4757 qcom,qmp = <&aoss_qmp>; 4758 4759 qcom,smem-states = <&smp2p_cdsp_out 0>; 4760 qcom,smem-state-names = "stop"; 4761 4762 status = "disabled"; 4763 4764 glink-edge { 4765 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4766 IPCC_MPROC_SIGNAL_GLINK_QMP 4767 IRQ_TYPE_EDGE_RISING>; 4768 mboxes = <&ipcc IPCC_CLIENT_CDSP 4769 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4770 4771 label = "cdsp"; 4772 qcom,remote-pid = <5>; 4773 4774 fastrpc { 4775 compatible = "qcom,fastrpc"; 4776 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4777 label = "cdsp"; 4778 qcom,non-secure-domain; 4779 #address-cells = <1>; 4780 #size-cells = <0>; 4781 4782 compute-cb@1 { 4783 compatible = "qcom,fastrpc-compute-cb"; 4784 reg = <1>; 4785 iommus = <&apps_smmu 0x1961 0x0>, 4786 <&apps_smmu 0x0c01 0x20>, 4787 <&apps_smmu 0x19c1 0x10>; 4788 dma-coherent; 4789 }; 4790 4791 compute-cb@2 { 4792 compatible = "qcom,fastrpc-compute-cb"; 4793 reg = <2>; 4794 iommus = <&apps_smmu 0x1962 0x0>, 4795 <&apps_smmu 0x0c02 0x20>, 4796 <&apps_smmu 0x19c2 0x10>; 4797 dma-coherent; 4798 }; 4799 4800 compute-cb@3 { 4801 compatible = "qcom,fastrpc-compute-cb"; 4802 reg = <3>; 4803 iommus = <&apps_smmu 0x1963 0x0>, 4804 <&apps_smmu 0x0c03 0x20>, 4805 <&apps_smmu 0x19c3 0x10>; 4806 dma-coherent; 4807 }; 4808 4809 compute-cb@4 { 4810 compatible = "qcom,fastrpc-compute-cb"; 4811 reg = <4>; 4812 iommus = <&apps_smmu 0x1964 0x0>, 4813 <&apps_smmu 0x0c04 0x20>, 4814 <&apps_smmu 0x19c4 0x10>; 4815 dma-coherent; 4816 }; 4817 4818 compute-cb@5 { 4819 compatible = "qcom,fastrpc-compute-cb"; 4820 reg = <5>; 4821 iommus = <&apps_smmu 0x1965 0x0>, 4822 <&apps_smmu 0x0c05 0x20>, 4823 <&apps_smmu 0x19c5 0x10>; 4824 dma-coherent; 4825 }; 4826 4827 compute-cb@6 { 4828 compatible = "qcom,fastrpc-compute-cb"; 4829 reg = <6>; 4830 iommus = <&apps_smmu 0x1966 0x0>, 4831 <&apps_smmu 0x0c06 0x20>, 4832 <&apps_smmu 0x19c6 0x10>; 4833 dma-coherent; 4834 }; 4835 4836 compute-cb@7 { 4837 compatible = "qcom,fastrpc-compute-cb"; 4838 reg = <7>; 4839 iommus = <&apps_smmu 0x1967 0x0>, 4840 <&apps_smmu 0x0c07 0x20>, 4841 <&apps_smmu 0x19c7 0x10>; 4842 dma-coherent; 4843 }; 4844 4845 compute-cb@8 { 4846 compatible = "qcom,fastrpc-compute-cb"; 4847 reg = <8>; 4848 iommus = <&apps_smmu 0x1968 0x0>, 4849 <&apps_smmu 0x0c08 0x20>, 4850 <&apps_smmu 0x19c8 0x10>; 4851 dma-coherent; 4852 }; 4853 4854 /* note: secure cb9 in downstream */ 4855 }; 4856 }; 4857 }; 4858 }; 4859 4860 thermal-zones { 4861 aoss0-thermal { 4862 thermal-sensors = <&tsens0 0>; 4863 4864 trips { 4865 thermal-engine-config { 4866 temperature = <125000>; 4867 hysteresis = <1000>; 4868 type = "passive"; 4869 }; 4870 4871 reset-mon-config { 4872 temperature = <115000>; 4873 hysteresis = <5000>; 4874 type = "passive"; 4875 }; 4876 }; 4877 }; 4878 4879 cpuss0-thermal { 4880 thermal-sensors = <&tsens0 1>; 4881 4882 trips { 4883 thermal-engine-config { 4884 temperature = <125000>; 4885 hysteresis = <1000>; 4886 type = "passive"; 4887 }; 4888 4889 reset-mon-config { 4890 temperature = <115000>; 4891 hysteresis = <5000>; 4892 type = "passive"; 4893 }; 4894 }; 4895 }; 4896 4897 cpuss1-thermal { 4898 thermal-sensors = <&tsens0 2>; 4899 4900 trips { 4901 thermal-engine-config { 4902 temperature = <125000>; 4903 hysteresis = <1000>; 4904 type = "passive"; 4905 }; 4906 4907 reset-mon-config { 4908 temperature = <115000>; 4909 hysteresis = <5000>; 4910 type = "passive"; 4911 }; 4912 }; 4913 }; 4914 4915 cpuss2-thermal { 4916 thermal-sensors = <&tsens0 3>; 4917 4918 trips { 4919 thermal-engine-config { 4920 temperature = <125000>; 4921 hysteresis = <1000>; 4922 type = "passive"; 4923 }; 4924 4925 reset-mon-config { 4926 temperature = <115000>; 4927 hysteresis = <5000>; 4928 type = "passive"; 4929 }; 4930 }; 4931 }; 4932 4933 cpuss3-thermal { 4934 thermal-sensors = <&tsens0 4>; 4935 4936 trips { 4937 thermal-engine-config { 4938 temperature = <125000>; 4939 hysteresis = <1000>; 4940 type = "passive"; 4941 }; 4942 4943 reset-mon-config { 4944 temperature = <115000>; 4945 hysteresis = <5000>; 4946 type = "passive"; 4947 }; 4948 }; 4949 }; 4950 4951 cpu3-top-thermal { 4952 thermal-sensors = <&tsens0 5>; 4953 4954 trips { 4955 cpu3_top_alert0: trip-point0 { 4956 temperature = <90000>; 4957 hysteresis = <2000>; 4958 type = "passive"; 4959 }; 4960 4961 cpu3_top_alert1: trip-point1 { 4962 temperature = <95000>; 4963 hysteresis = <2000>; 4964 type = "passive"; 4965 }; 4966 4967 cpu3_top_crit: cpu-critical { 4968 temperature = <110000>; 4969 hysteresis = <1000>; 4970 type = "critical"; 4971 }; 4972 }; 4973 }; 4974 4975 cpu3-bottom-thermal { 4976 thermal-sensors = <&tsens0 6>; 4977 4978 trips { 4979 cpu3_bottom_alert0: trip-point0 { 4980 temperature = <90000>; 4981 hysteresis = <2000>; 4982 type = "passive"; 4983 }; 4984 4985 cpu3_bottom_alert1: trip-point1 { 4986 temperature = <95000>; 4987 hysteresis = <2000>; 4988 type = "passive"; 4989 }; 4990 4991 cpu3_bottom_crit: cpu-critical { 4992 temperature = <110000>; 4993 hysteresis = <1000>; 4994 type = "critical"; 4995 }; 4996 }; 4997 }; 4998 4999 cpu4-top-thermal { 5000 thermal-sensors = <&tsens0 7>; 5001 5002 trips { 5003 cpu4_top_alert0: trip-point0 { 5004 temperature = <90000>; 5005 hysteresis = <2000>; 5006 type = "passive"; 5007 }; 5008 5009 cpu4_top_alert1: trip-point1 { 5010 temperature = <95000>; 5011 hysteresis = <2000>; 5012 type = "passive"; 5013 }; 5014 5015 cpu4_top_crit: cpu-critical { 5016 temperature = <110000>; 5017 hysteresis = <1000>; 5018 type = "critical"; 5019 }; 5020 }; 5021 }; 5022 5023 cpu4-bottom-thermal { 5024 thermal-sensors = <&tsens0 8>; 5025 5026 trips { 5027 cpu4_bottom_alert0: trip-point0 { 5028 temperature = <90000>; 5029 hysteresis = <2000>; 5030 type = "passive"; 5031 }; 5032 5033 cpu4_bottom_alert1: trip-point1 { 5034 temperature = <95000>; 5035 hysteresis = <2000>; 5036 type = "passive"; 5037 }; 5038 5039 cpu4_bottom_crit: cpu-critical { 5040 temperature = <110000>; 5041 hysteresis = <1000>; 5042 type = "critical"; 5043 }; 5044 }; 5045 }; 5046 5047 cpu5-top-thermal { 5048 thermal-sensors = <&tsens0 9>; 5049 5050 trips { 5051 cpu5_top_alert0: trip-point0 { 5052 temperature = <90000>; 5053 hysteresis = <2000>; 5054 type = "passive"; 5055 }; 5056 5057 cpu5_top_alert1: trip-point1 { 5058 temperature = <95000>; 5059 hysteresis = <2000>; 5060 type = "passive"; 5061 }; 5062 5063 cpu5_top_crit: cpu-critical { 5064 temperature = <110000>; 5065 hysteresis = <1000>; 5066 type = "critical"; 5067 }; 5068 }; 5069 }; 5070 5071 cpu5-bottom-thermal { 5072 thermal-sensors = <&tsens0 10>; 5073 5074 trips { 5075 cpu5_bottom_alert0: trip-point0 { 5076 temperature = <90000>; 5077 hysteresis = <2000>; 5078 type = "passive"; 5079 }; 5080 5081 cpu5_bottom_alert1: trip-point1 { 5082 temperature = <95000>; 5083 hysteresis = <2000>; 5084 type = "passive"; 5085 }; 5086 5087 cpu5_bottom_crit: cpu-critical { 5088 temperature = <110000>; 5089 hysteresis = <1000>; 5090 type = "critical"; 5091 }; 5092 }; 5093 }; 5094 5095 cpu6-top-thermal { 5096 thermal-sensors = <&tsens0 11>; 5097 5098 trips { 5099 cpu6_top_alert0: trip-point0 { 5100 temperature = <90000>; 5101 hysteresis = <2000>; 5102 type = "passive"; 5103 }; 5104 5105 cpu6_top_alert1: trip-point1 { 5106 temperature = <95000>; 5107 hysteresis = <2000>; 5108 type = "passive"; 5109 }; 5110 5111 cpu6_top_crit: cpu-critical { 5112 temperature = <110000>; 5113 hysteresis = <1000>; 5114 type = "critical"; 5115 }; 5116 }; 5117 }; 5118 5119 cpu6-bottom-thermal { 5120 thermal-sensors = <&tsens0 12>; 5121 5122 trips { 5123 cpu6_bottom_alert0: trip-point0 { 5124 temperature = <90000>; 5125 hysteresis = <2000>; 5126 type = "passive"; 5127 }; 5128 5129 cpu6_bottom_alert1: trip-point1 { 5130 temperature = <95000>; 5131 hysteresis = <2000>; 5132 type = "passive"; 5133 }; 5134 5135 cpu6_bottom_crit: cpu-critical { 5136 temperature = <110000>; 5137 hysteresis = <1000>; 5138 type = "critical"; 5139 }; 5140 }; 5141 }; 5142 5143 cpu7-top-thermal { 5144 thermal-sensors = <&tsens0 13>; 5145 5146 trips { 5147 cpu7_top_alert0: trip-point0 { 5148 temperature = <90000>; 5149 hysteresis = <2000>; 5150 type = "passive"; 5151 }; 5152 5153 cpu7_top_alert1: trip-point1 { 5154 temperature = <95000>; 5155 hysteresis = <2000>; 5156 type = "passive"; 5157 }; 5158 5159 cpu7_top_crit: cpu-critical { 5160 temperature = <110000>; 5161 hysteresis = <1000>; 5162 type = "critical"; 5163 }; 5164 }; 5165 }; 5166 5167 cpu7-middle-thermal { 5168 thermal-sensors = <&tsens0 14>; 5169 5170 trips { 5171 cpu7_middle_alert0: trip-point0 { 5172 temperature = <90000>; 5173 hysteresis = <2000>; 5174 type = "passive"; 5175 }; 5176 5177 cpu7_middle_alert1: trip-point1 { 5178 temperature = <95000>; 5179 hysteresis = <2000>; 5180 type = "passive"; 5181 }; 5182 5183 cpu7_middle_crit: cpu-critical { 5184 temperature = <110000>; 5185 hysteresis = <1000>; 5186 type = "critical"; 5187 }; 5188 }; 5189 }; 5190 5191 cpu7-bottom-thermal { 5192 thermal-sensors = <&tsens0 15>; 5193 5194 trips { 5195 cpu7_bottom_alert0: trip-point0 { 5196 temperature = <90000>; 5197 hysteresis = <2000>; 5198 type = "passive"; 5199 }; 5200 5201 cpu7_bottom_alert1: trip-point1 { 5202 temperature = <95000>; 5203 hysteresis = <2000>; 5204 type = "passive"; 5205 }; 5206 5207 cpu7_bottom_crit: cpu-critical { 5208 temperature = <110000>; 5209 hysteresis = <1000>; 5210 type = "critical"; 5211 }; 5212 }; 5213 }; 5214 5215 aoss1-thermal { 5216 thermal-sensors = <&tsens1 0>; 5217 5218 trips { 5219 thermal-engine-config { 5220 temperature = <125000>; 5221 hysteresis = <1000>; 5222 type = "passive"; 5223 }; 5224 5225 reset-mon-config { 5226 temperature = <115000>; 5227 hysteresis = <5000>; 5228 type = "passive"; 5229 }; 5230 }; 5231 }; 5232 5233 cpu0-thermal { 5234 thermal-sensors = <&tsens1 1>; 5235 5236 trips { 5237 cpu0_alert0: trip-point0 { 5238 temperature = <90000>; 5239 hysteresis = <2000>; 5240 type = "passive"; 5241 }; 5242 5243 cpu0_alert1: trip-point1 { 5244 temperature = <95000>; 5245 hysteresis = <2000>; 5246 type = "passive"; 5247 }; 5248 5249 cpu0_crit: cpu-critical { 5250 temperature = <110000>; 5251 hysteresis = <1000>; 5252 type = "critical"; 5253 }; 5254 }; 5255 }; 5256 5257 cpu1-thermal { 5258 thermal-sensors = <&tsens1 2>; 5259 5260 trips { 5261 cpu1_alert0: trip-point0 { 5262 temperature = <90000>; 5263 hysteresis = <2000>; 5264 type = "passive"; 5265 }; 5266 5267 cpu1_alert1: trip-point1 { 5268 temperature = <95000>; 5269 hysteresis = <2000>; 5270 type = "passive"; 5271 }; 5272 5273 cpu1_crit: cpu-critical { 5274 temperature = <110000>; 5275 hysteresis = <1000>; 5276 type = "critical"; 5277 }; 5278 }; 5279 }; 5280 5281 cpu2-thermal { 5282 thermal-sensors = <&tsens1 3>; 5283 5284 trips { 5285 cpu2_alert0: trip-point0 { 5286 temperature = <90000>; 5287 hysteresis = <2000>; 5288 type = "passive"; 5289 }; 5290 5291 cpu2_alert1: trip-point1 { 5292 temperature = <95000>; 5293 hysteresis = <2000>; 5294 type = "passive"; 5295 }; 5296 5297 cpu2_crit: cpu-critical { 5298 temperature = <110000>; 5299 hysteresis = <1000>; 5300 type = "critical"; 5301 }; 5302 }; 5303 }; 5304 5305 cdsp0-thermal { 5306 polling-delay-passive = <10>; 5307 5308 thermal-sensors = <&tsens2 4>; 5309 5310 trips { 5311 thermal-engine-config { 5312 temperature = <125000>; 5313 hysteresis = <1000>; 5314 type = "passive"; 5315 }; 5316 5317 thermal-hal-config { 5318 temperature = <125000>; 5319 hysteresis = <1000>; 5320 type = "passive"; 5321 }; 5322 5323 reset-mon-config { 5324 temperature = <115000>; 5325 hysteresis = <5000>; 5326 type = "passive"; 5327 }; 5328 5329 cdsp0_junction_config: junction-config { 5330 temperature = <95000>; 5331 hysteresis = <5000>; 5332 type = "passive"; 5333 }; 5334 }; 5335 }; 5336 5337 cdsp1-thermal { 5338 polling-delay-passive = <10>; 5339 5340 thermal-sensors = <&tsens2 5>; 5341 5342 trips { 5343 thermal-engine-config { 5344 temperature = <125000>; 5345 hysteresis = <1000>; 5346 type = "passive"; 5347 }; 5348 5349 thermal-hal-config { 5350 temperature = <125000>; 5351 hysteresis = <1000>; 5352 type = "passive"; 5353 }; 5354 5355 reset-mon-config { 5356 temperature = <115000>; 5357 hysteresis = <5000>; 5358 type = "passive"; 5359 }; 5360 5361 cdsp1_junction_config: junction-config { 5362 temperature = <95000>; 5363 hysteresis = <5000>; 5364 type = "passive"; 5365 }; 5366 }; 5367 }; 5368 5369 cdsp2-thermal { 5370 polling-delay-passive = <10>; 5371 5372 thermal-sensors = <&tsens2 6>; 5373 5374 trips { 5375 thermal-engine-config { 5376 temperature = <125000>; 5377 hysteresis = <1000>; 5378 type = "passive"; 5379 }; 5380 5381 thermal-hal-config { 5382 temperature = <125000>; 5383 hysteresis = <1000>; 5384 type = "passive"; 5385 }; 5386 5387 reset-mon-config { 5388 temperature = <115000>; 5389 hysteresis = <5000>; 5390 type = "passive"; 5391 }; 5392 5393 cdsp2_junction_config: junction-config { 5394 temperature = <95000>; 5395 hysteresis = <5000>; 5396 type = "passive"; 5397 }; 5398 }; 5399 }; 5400 5401 cdsp3-thermal { 5402 polling-delay-passive = <10>; 5403 5404 thermal-sensors = <&tsens2 7>; 5405 5406 trips { 5407 thermal-engine-config { 5408 temperature = <125000>; 5409 hysteresis = <1000>; 5410 type = "passive"; 5411 }; 5412 5413 thermal-hal-config { 5414 temperature = <125000>; 5415 hysteresis = <1000>; 5416 type = "passive"; 5417 }; 5418 5419 reset-mon-config { 5420 temperature = <115000>; 5421 hysteresis = <5000>; 5422 type = "passive"; 5423 }; 5424 5425 cdsp3_junction_config: junction-config { 5426 temperature = <95000>; 5427 hysteresis = <5000>; 5428 type = "passive"; 5429 }; 5430 }; 5431 }; 5432 5433 video-thermal { 5434 thermal-sensors = <&tsens1 8>; 5435 5436 trips { 5437 thermal-engine-config { 5438 temperature = <125000>; 5439 hysteresis = <1000>; 5440 type = "passive"; 5441 }; 5442 5443 reset-mon-config { 5444 temperature = <115000>; 5445 hysteresis = <5000>; 5446 type = "passive"; 5447 }; 5448 }; 5449 }; 5450 5451 mem-thermal { 5452 polling-delay-passive = <10>; 5453 5454 thermal-sensors = <&tsens1 9>; 5455 5456 trips { 5457 thermal-engine-config { 5458 temperature = <125000>; 5459 hysteresis = <1000>; 5460 type = "passive"; 5461 }; 5462 5463 ddr_config0: ddr0-config { 5464 temperature = <90000>; 5465 hysteresis = <5000>; 5466 type = "passive"; 5467 }; 5468 5469 reset-mon-config { 5470 temperature = <115000>; 5471 hysteresis = <5000>; 5472 type = "passive"; 5473 }; 5474 }; 5475 }; 5476 5477 modem0-thermal { 5478 thermal-sensors = <&tsens1 10>; 5479 5480 trips { 5481 thermal-engine-config { 5482 temperature = <125000>; 5483 hysteresis = <1000>; 5484 type = "passive"; 5485 }; 5486 5487 mdmss0_config0: mdmss0-config0 { 5488 temperature = <102000>; 5489 hysteresis = <3000>; 5490 type = "passive"; 5491 }; 5492 5493 mdmss0_config1: mdmss0-config1 { 5494 temperature = <105000>; 5495 hysteresis = <3000>; 5496 type = "passive"; 5497 }; 5498 5499 reset-mon-config { 5500 temperature = <115000>; 5501 hysteresis = <5000>; 5502 type = "passive"; 5503 }; 5504 }; 5505 }; 5506 5507 modem1-thermal { 5508 thermal-sensors = <&tsens1 11>; 5509 5510 trips { 5511 thermal-engine-config { 5512 temperature = <125000>; 5513 hysteresis = <1000>; 5514 type = "passive"; 5515 }; 5516 5517 mdmss1_config0: mdmss1-config0 { 5518 temperature = <102000>; 5519 hysteresis = <3000>; 5520 type = "passive"; 5521 }; 5522 5523 mdmss1_config1: mdmss1-config1 { 5524 temperature = <105000>; 5525 hysteresis = <3000>; 5526 type = "passive"; 5527 }; 5528 5529 reset-mon-config { 5530 temperature = <115000>; 5531 hysteresis = <5000>; 5532 type = "passive"; 5533 }; 5534 }; 5535 }; 5536 5537 modem2-thermal { 5538 thermal-sensors = <&tsens1 12>; 5539 5540 trips { 5541 thermal-engine-config { 5542 temperature = <125000>; 5543 hysteresis = <1000>; 5544 type = "passive"; 5545 }; 5546 5547 mdmss2_config0: mdmss2-config0 { 5548 temperature = <102000>; 5549 hysteresis = <3000>; 5550 type = "passive"; 5551 }; 5552 5553 mdmss2_config1: mdmss2-config1 { 5554 temperature = <105000>; 5555 hysteresis = <3000>; 5556 type = "passive"; 5557 }; 5558 5559 reset-mon-config { 5560 temperature = <115000>; 5561 hysteresis = <5000>; 5562 type = "passive"; 5563 }; 5564 }; 5565 }; 5566 5567 modem3-thermal { 5568 thermal-sensors = <&tsens1 13>; 5569 5570 trips { 5571 thermal-engine-config { 5572 temperature = <125000>; 5573 hysteresis = <1000>; 5574 type = "passive"; 5575 }; 5576 5577 mdmss3_config0: mdmss3-config0 { 5578 temperature = <102000>; 5579 hysteresis = <3000>; 5580 type = "passive"; 5581 }; 5582 5583 mdmss3_config1: mdmss3-config1 { 5584 temperature = <105000>; 5585 hysteresis = <3000>; 5586 type = "passive"; 5587 }; 5588 5589 reset-mon-config { 5590 temperature = <115000>; 5591 hysteresis = <5000>; 5592 type = "passive"; 5593 }; 5594 }; 5595 }; 5596 5597 camera0-thermal { 5598 thermal-sensors = <&tsens1 14>; 5599 5600 trips { 5601 thermal-engine-config { 5602 temperature = <125000>; 5603 hysteresis = <1000>; 5604 type = "passive"; 5605 }; 5606 5607 reset-mon-config { 5608 temperature = <115000>; 5609 hysteresis = <5000>; 5610 type = "passive"; 5611 }; 5612 }; 5613 }; 5614 5615 camera1-thermal { 5616 thermal-sensors = <&tsens1 15>; 5617 5618 trips { 5619 thermal-engine-config { 5620 temperature = <125000>; 5621 hysteresis = <1000>; 5622 type = "passive"; 5623 }; 5624 5625 reset-mon-config { 5626 temperature = <115000>; 5627 hysteresis = <5000>; 5628 type = "passive"; 5629 }; 5630 }; 5631 }; 5632 5633 aoss2-thermal { 5634 thermal-sensors = <&tsens2 0>; 5635 5636 trips { 5637 thermal-engine-config { 5638 temperature = <125000>; 5639 hysteresis = <1000>; 5640 type = "passive"; 5641 }; 5642 5643 reset-mon-config { 5644 temperature = <115000>; 5645 hysteresis = <5000>; 5646 type = "passive"; 5647 }; 5648 }; 5649 }; 5650 5651 gpuss-0-thermal { 5652 polling-delay-passive = <10>; 5653 5654 thermal-sensors = <&tsens2 1>; 5655 5656 cooling-maps { 5657 map0 { 5658 trip = <&gpu0_alert0>; 5659 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5660 }; 5661 }; 5662 5663 trips { 5664 gpu0_alert0: trip-point0 { 5665 temperature = <85000>; 5666 hysteresis = <1000>; 5667 type = "passive"; 5668 }; 5669 5670 trip-point1 { 5671 temperature = <90000>; 5672 hysteresis = <1000>; 5673 type = "hot"; 5674 }; 5675 5676 trip-point2 { 5677 temperature = <110000>; 5678 hysteresis = <1000>; 5679 type = "critical"; 5680 }; 5681 }; 5682 }; 5683 5684 gpuss-1-thermal { 5685 polling-delay-passive = <10>; 5686 5687 thermal-sensors = <&tsens2 2>; 5688 5689 cooling-maps { 5690 map0 { 5691 trip = <&gpu1_alert0>; 5692 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5693 }; 5694 }; 5695 5696 trips { 5697 gpu1_alert0: trip-point0 { 5698 temperature = <85000>; 5699 hysteresis = <1000>; 5700 type = "passive"; 5701 }; 5702 5703 trip-point1 { 5704 temperature = <90000>; 5705 hysteresis = <1000>; 5706 type = "hot"; 5707 }; 5708 5709 trip-point2 { 5710 temperature = <110000>; 5711 hysteresis = <1000>; 5712 type = "critical"; 5713 }; 5714 }; 5715 }; 5716 5717 gpuss-2-thermal { 5718 polling-delay-passive = <10>; 5719 5720 thermal-sensors = <&tsens2 3>; 5721 5722 cooling-maps { 5723 map0 { 5724 trip = <&gpu2_alert0>; 5725 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5726 }; 5727 }; 5728 5729 trips { 5730 gpu2_alert0: trip-point0 { 5731 temperature = <85000>; 5732 hysteresis = <1000>; 5733 type = "passive"; 5734 }; 5735 5736 trip-point1 { 5737 temperature = <90000>; 5738 hysteresis = <1000>; 5739 type = "hot"; 5740 }; 5741 5742 trip-point2 { 5743 temperature = <110000>; 5744 hysteresis = <1000>; 5745 type = "critical"; 5746 }; 5747 }; 5748 }; 5749 5750 gpuss-3-thermal { 5751 polling-delay-passive = <10>; 5752 5753 thermal-sensors = <&tsens2 4>; 5754 5755 cooling-maps { 5756 map0 { 5757 trip = <&gpu3_alert0>; 5758 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5759 }; 5760 }; 5761 5762 trips { 5763 gpu3_alert0: trip-point0 { 5764 temperature = <85000>; 5765 hysteresis = <1000>; 5766 type = "passive"; 5767 }; 5768 5769 trip-point1 { 5770 temperature = <90000>; 5771 hysteresis = <1000>; 5772 type = "hot"; 5773 }; 5774 5775 trip-point2 { 5776 temperature = <110000>; 5777 hysteresis = <1000>; 5778 type = "critical"; 5779 }; 5780 }; 5781 }; 5782 5783 gpuss-4-thermal { 5784 polling-delay-passive = <10>; 5785 5786 thermal-sensors = <&tsens2 5>; 5787 5788 cooling-maps { 5789 map0 { 5790 trip = <&gpu4_alert0>; 5791 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5792 }; 5793 }; 5794 5795 trips { 5796 gpu4_alert0: trip-point0 { 5797 temperature = <85000>; 5798 hysteresis = <1000>; 5799 type = "passive"; 5800 }; 5801 5802 trip-point1 { 5803 temperature = <90000>; 5804 hysteresis = <1000>; 5805 type = "hot"; 5806 }; 5807 5808 trip-point2 { 5809 temperature = <110000>; 5810 hysteresis = <1000>; 5811 type = "critical"; 5812 }; 5813 }; 5814 }; 5815 5816 gpuss-5-thermal { 5817 polling-delay-passive = <10>; 5818 5819 thermal-sensors = <&tsens2 6>; 5820 5821 cooling-maps { 5822 map0 { 5823 trip = <&gpu5_alert0>; 5824 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5825 }; 5826 }; 5827 5828 trips { 5829 gpu5_alert0: trip-point0 { 5830 temperature = <85000>; 5831 hysteresis = <1000>; 5832 type = "passive"; 5833 }; 5834 5835 trip-point1 { 5836 temperature = <90000>; 5837 hysteresis = <1000>; 5838 type = "hot"; 5839 }; 5840 5841 trip-point2 { 5842 temperature = <110000>; 5843 hysteresis = <1000>; 5844 type = "critical"; 5845 }; 5846 }; 5847 }; 5848 5849 gpuss-6-thermal { 5850 polling-delay-passive = <10>; 5851 5852 thermal-sensors = <&tsens2 7>; 5853 5854 cooling-maps { 5855 map0 { 5856 trip = <&gpu6_alert0>; 5857 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5858 }; 5859 }; 5860 5861 trips { 5862 gpu6_alert0: trip-point0 { 5863 temperature = <85000>; 5864 hysteresis = <1000>; 5865 type = "passive"; 5866 }; 5867 5868 trip-point1 { 5869 temperature = <90000>; 5870 hysteresis = <1000>; 5871 type = "hot"; 5872 }; 5873 5874 trip-point2 { 5875 temperature = <110000>; 5876 hysteresis = <1000>; 5877 type = "critical"; 5878 }; 5879 }; 5880 }; 5881 5882 gpuss-7-thermal { 5883 polling-delay-passive = <10>; 5884 5885 thermal-sensors = <&tsens2 8>; 5886 5887 cooling-maps { 5888 map0 { 5889 trip = <&gpu7_alert0>; 5890 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5891 }; 5892 }; 5893 5894 trips { 5895 gpu7_alert0: trip-point0 { 5896 temperature = <85000>; 5897 hysteresis = <1000>; 5898 type = "passive"; 5899 }; 5900 5901 trip-point1 { 5902 temperature = <90000>; 5903 hysteresis = <1000>; 5904 type = "hot"; 5905 }; 5906 5907 trip-point2 { 5908 temperature = <110000>; 5909 hysteresis = <1000>; 5910 type = "critical"; 5911 }; 5912 }; 5913 }; 5914 }; 5915 5916 timer { 5917 compatible = "arm,armv8-timer"; 5918 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5919 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5920 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5921 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5922 }; 5923}; 5924