1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm8650-camcc.h> 8#include <dt-bindings/clock/qcom,sm8650-dispcc.h> 9#include <dt-bindings/clock/qcom,sm8650-gcc.h> 10#include <dt-bindings/clock/qcom,sm8650-gpucc.h> 11#include <dt-bindings/clock/qcom,sm8650-tcsr.h> 12#include <dt-bindings/clock/qcom,sm8650-videocc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/interconnect/qcom,icc.h> 17#include <dt-bindings/interconnect/qcom,sm8650-rpmh.h> 18#include <dt-bindings/interrupt-controller/arm-gic.h> 19#include <dt-bindings/mailbox/qcom-ipcc.h> 20#include <dt-bindings/phy/phy-qcom-qmp.h> 21#include <dt-bindings/power/qcom,rpmhpd.h> 22#include <dt-bindings/power/qcom-rpmpd.h> 23#include <dt-bindings/reset/qcom,sm8650-gpucc.h> 24#include <dt-bindings/soc/qcom,gpr.h> 25#include <dt-bindings/soc/qcom,rpmh-rsc.h> 26#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 27#include <dt-bindings/thermal/thermal.h> 28 29/ { 30 interrupt-parent = <&intc>; 31 32 #address-cells = <2>; 33 #size-cells = <2>; 34 35 chosen { }; 36 37 clocks { 38 xo_board: xo-board { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 }; 47 48 bi_tcxo_div2: bi-tcxo-div2-clk { 49 compatible = "fixed-factor-clock"; 50 #clock-cells = <0>; 51 52 clocks = <&rpmhcc RPMH_CXO_CLK>; 53 clock-mult = <1>; 54 clock-div = <2>; 55 }; 56 57 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 58 compatible = "fixed-factor-clock"; 59 #clock-cells = <0>; 60 61 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 62 clock-mult = <1>; 63 clock-div = <2>; 64 }; 65 }; 66 67 cpus { 68 #address-cells = <2>; 69 #size-cells = <0>; 70 71 cpu0: cpu@0 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a520"; 74 reg = <0 0>; 75 76 clocks = <&cpufreq_hw 0>; 77 78 power-domains = <&cpu_pd0>; 79 power-domain-names = "psci"; 80 81 enable-method = "psci"; 82 next-level-cache = <&l2_0>; 83 capacity-dmips-mhz = <1024>; 84 dynamic-power-coefficient = <100>; 85 86 qcom,freq-domain = <&cpufreq_hw 0>; 87 88 #cooling-cells = <2>; 89 90 l2_0: l2-cache { 91 compatible = "cache"; 92 cache-level = <2>; 93 cache-unified; 94 next-level-cache = <&l3_0>; 95 96 l3_0: l3-cache { 97 compatible = "cache"; 98 cache-level = <3>; 99 cache-unified; 100 }; 101 }; 102 }; 103 104 cpu1: cpu@100 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a520"; 107 reg = <0 0x100>; 108 109 clocks = <&cpufreq_hw 0>; 110 111 power-domains = <&cpu_pd1>; 112 power-domain-names = "psci"; 113 114 enable-method = "psci"; 115 next-level-cache = <&l2_0>; 116 capacity-dmips-mhz = <1024>; 117 dynamic-power-coefficient = <100>; 118 119 qcom,freq-domain = <&cpufreq_hw 0>; 120 121 #cooling-cells = <2>; 122 }; 123 124 cpu2: cpu@200 { 125 device_type = "cpu"; 126 compatible = "arm,cortex-a720"; 127 reg = <0 0x200>; 128 129 clocks = <&cpufreq_hw 3>; 130 131 power-domains = <&cpu_pd2>; 132 power-domain-names = "psci"; 133 134 enable-method = "psci"; 135 next-level-cache = <&l2_200>; 136 capacity-dmips-mhz = <1792>; 137 dynamic-power-coefficient = <238>; 138 139 qcom,freq-domain = <&cpufreq_hw 3>; 140 141 #cooling-cells = <2>; 142 143 l2_200: l2-cache { 144 compatible = "cache"; 145 cache-level = <2>; 146 cache-unified; 147 next-level-cache = <&l3_0>; 148 }; 149 }; 150 151 cpu3: cpu@300 { 152 device_type = "cpu"; 153 compatible = "arm,cortex-a720"; 154 reg = <0 0x300>; 155 156 clocks = <&cpufreq_hw 3>; 157 158 power-domains = <&cpu_pd3>; 159 power-domain-names = "psci"; 160 161 enable-method = "psci"; 162 next-level-cache = <&l2_200>; 163 capacity-dmips-mhz = <1792>; 164 dynamic-power-coefficient = <238>; 165 166 qcom,freq-domain = <&cpufreq_hw 3>; 167 168 #cooling-cells = <2>; 169 }; 170 171 cpu4: cpu@400 { 172 device_type = "cpu"; 173 compatible = "arm,cortex-a720"; 174 reg = <0 0x400>; 175 176 clocks = <&cpufreq_hw 3>; 177 178 power-domains = <&cpu_pd4>; 179 power-domain-names = "psci"; 180 181 enable-method = "psci"; 182 next-level-cache = <&l2_400>; 183 capacity-dmips-mhz = <1792>; 184 dynamic-power-coefficient = <238>; 185 186 qcom,freq-domain = <&cpufreq_hw 3>; 187 188 #cooling-cells = <2>; 189 190 l2_400: l2-cache { 191 compatible = "cache"; 192 cache-level = <2>; 193 cache-unified; 194 next-level-cache = <&l3_0>; 195 }; 196 }; 197 198 cpu5: cpu@500 { 199 device_type = "cpu"; 200 compatible = "arm,cortex-a720"; 201 reg = <0 0x500>; 202 203 clocks = <&cpufreq_hw 1>; 204 205 power-domains = <&cpu_pd5>; 206 power-domain-names = "psci"; 207 208 enable-method = "psci"; 209 next-level-cache = <&l2_500>; 210 capacity-dmips-mhz = <1792>; 211 dynamic-power-coefficient = <238>; 212 213 qcom,freq-domain = <&cpufreq_hw 1>; 214 215 #cooling-cells = <2>; 216 217 l2_500: l2-cache { 218 compatible = "cache"; 219 cache-level = <2>; 220 cache-unified; 221 next-level-cache = <&l3_0>; 222 }; 223 }; 224 225 cpu6: cpu@600 { 226 device_type = "cpu"; 227 compatible = "arm,cortex-a720"; 228 reg = <0 0x600>; 229 230 clocks = <&cpufreq_hw 1>; 231 232 power-domains = <&cpu_pd6>; 233 power-domain-names = "psci"; 234 235 enable-method = "psci"; 236 next-level-cache = <&l2_600>; 237 capacity-dmips-mhz = <1792>; 238 dynamic-power-coefficient = <238>; 239 240 qcom,freq-domain = <&cpufreq_hw 1>; 241 242 #cooling-cells = <2>; 243 244 l2_600: l2-cache { 245 compatible = "cache"; 246 cache-level = <2>; 247 cache-unified; 248 next-level-cache = <&l3_0>; 249 }; 250 }; 251 252 cpu7: cpu@700 { 253 device_type = "cpu"; 254 compatible = "arm,cortex-x4"; 255 reg = <0 0x700>; 256 257 clocks = <&cpufreq_hw 2>; 258 259 power-domains = <&cpu_pd7>; 260 power-domain-names = "psci"; 261 262 enable-method = "psci"; 263 next-level-cache = <&l2_700>; 264 capacity-dmips-mhz = <1894>; 265 dynamic-power-coefficient = <588>; 266 267 qcom,freq-domain = <&cpufreq_hw 2>; 268 269 #cooling-cells = <2>; 270 271 l2_700: l2-cache { 272 compatible = "cache"; 273 cache-level = <2>; 274 cache-unified; 275 next-level-cache = <&l3_0>; 276 }; 277 }; 278 279 cpu-map { 280 cluster0 { 281 core0 { 282 cpu = <&cpu0>; 283 }; 284 285 core1 { 286 cpu = <&cpu1>; 287 }; 288 289 core2 { 290 cpu = <&cpu2>; 291 }; 292 293 core3 { 294 cpu = <&cpu3>; 295 }; 296 297 core4 { 298 cpu = <&cpu4>; 299 }; 300 301 core5 { 302 cpu = <&cpu5>; 303 }; 304 305 core6 { 306 cpu = <&cpu6>; 307 }; 308 309 core7 { 310 cpu = <&cpu7>; 311 }; 312 }; 313 }; 314 315 idle-states { 316 entry-method = "psci"; 317 318 silver_cpu_sleep_0: cpu-sleep-0-0 { 319 compatible = "arm,idle-state"; 320 idle-state-name = "silver-rail-power-collapse"; 321 arm,psci-suspend-param = <0x40000004>; 322 entry-latency-us = <550>; 323 exit-latency-us = <750>; 324 min-residency-us = <6700>; 325 local-timer-stop; 326 }; 327 328 gold_cpu_sleep_0: cpu-sleep-1-0 { 329 compatible = "arm,idle-state"; 330 idle-state-name = "gold-rail-power-collapse"; 331 arm,psci-suspend-param = <0x40000004>; 332 entry-latency-us = <600>; 333 exit-latency-us = <1300>; 334 min-residency-us = <8136>; 335 local-timer-stop; 336 }; 337 338 gold_plus_cpu_sleep_0: cpu-sleep-2-0 { 339 compatible = "arm,idle-state"; 340 idle-state-name = "gold-plus-rail-power-collapse"; 341 arm,psci-suspend-param = <0x40000004>; 342 entry-latency-us = <500>; 343 exit-latency-us = <1350>; 344 min-residency-us = <7480>; 345 local-timer-stop; 346 }; 347 }; 348 349 domain-idle-states { 350 cluster_sleep_0: cluster-sleep-0 { 351 compatible = "domain-idle-state"; 352 arm,psci-suspend-param = <0x41000044>; 353 entry-latency-us = <750>; 354 exit-latency-us = <2350>; 355 min-residency-us = <9144>; 356 }; 357 358 cluster_sleep_1: cluster-sleep-1 { 359 compatible = "domain-idle-state"; 360 arm,psci-suspend-param = <0x4100c344>; 361 entry-latency-us = <2800>; 362 exit-latency-us = <4400>; 363 min-residency-us = <10150>; 364 }; 365 }; 366 }; 367 368 ete0 { 369 compatible = "arm,embedded-trace-extension"; 370 371 cpu = <&cpu0>; 372 373 out-ports { 374 port { 375 ete0_out_funnel_ete: endpoint { 376 remote-endpoint = <&funnel_ete_in_ete0>; 377 }; 378 }; 379 }; 380 }; 381 382 funnel-ete { 383 compatible = "arm,coresight-static-funnel"; 384 385 in-ports { 386 port { 387 funnel_ete_in_ete0: endpoint { 388 remote-endpoint = <&ete0_out_funnel_ete>; 389 }; 390 }; 391 }; 392 393 out-ports { 394 port { 395 funnel_ete_out_funnel_apss: endpoint { 396 remote-endpoint = <&funnel_apss_in_funnel_ete>; 397 }; 398 }; 399 }; 400 }; 401 402 firmware { 403 scm: scm { 404 compatible = "qcom,scm-sm8650", "qcom,scm"; 405 qcom,dload-mode = <&tcsr 0x19000>; 406 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 407 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 408 }; 409 }; 410 411 clk_virt: interconnect-0 { 412 compatible = "qcom,sm8650-clk-virt"; 413 #interconnect-cells = <2>; 414 qcom,bcm-voters = <&apps_bcm_voter>; 415 }; 416 417 mc_virt: interconnect-1 { 418 compatible = "qcom,sm8650-mc-virt"; 419 #interconnect-cells = <2>; 420 qcom,bcm-voters = <&apps_bcm_voter>; 421 }; 422 423 memory@a0000000 { 424 device_type = "memory"; 425 /* We expect the bootloader to fill in the size */ 426 reg = <0 0xa0000000 0 0>; 427 }; 428 429 pmu-a520 { 430 compatible = "arm,cortex-a520-pmu"; 431 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 432 }; 433 434 pmu-a720 { 435 compatible = "arm,cortex-a720-pmu"; 436 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 437 }; 438 439 pmu-x4 { 440 compatible = "arm,cortex-x4-pmu"; 441 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 442 }; 443 444 psci { 445 compatible = "arm,psci-1.0"; 446 method = "smc"; 447 448 cpu_pd0: power-domain-cpu0 { 449 #power-domain-cells = <0>; 450 power-domains = <&cluster_pd>; 451 domain-idle-states = <&silver_cpu_sleep_0>; 452 }; 453 454 cpu_pd1: power-domain-cpu1 { 455 #power-domain-cells = <0>; 456 power-domains = <&cluster_pd>; 457 domain-idle-states = <&silver_cpu_sleep_0>; 458 }; 459 460 cpu_pd2: power-domain-cpu2 { 461 #power-domain-cells = <0>; 462 power-domains = <&cluster_pd>; 463 domain-idle-states = <&silver_cpu_sleep_0>; 464 }; 465 466 cpu_pd3: power-domain-cpu3 { 467 #power-domain-cells = <0>; 468 power-domains = <&cluster_pd>; 469 domain-idle-states = <&gold_cpu_sleep_0>; 470 }; 471 472 cpu_pd4: power-domain-cpu4 { 473 #power-domain-cells = <0>; 474 power-domains = <&cluster_pd>; 475 domain-idle-states = <&gold_cpu_sleep_0>; 476 }; 477 478 cpu_pd5: power-domain-cpu5 { 479 #power-domain-cells = <0>; 480 power-domains = <&cluster_pd>; 481 domain-idle-states = <&gold_cpu_sleep_0>; 482 }; 483 484 cpu_pd6: power-domain-cpu6 { 485 #power-domain-cells = <0>; 486 power-domains = <&cluster_pd>; 487 domain-idle-states = <&gold_cpu_sleep_0>; 488 }; 489 490 cpu_pd7: power-domain-cpu7 { 491 #power-domain-cells = <0>; 492 power-domains = <&cluster_pd>; 493 domain-idle-states = <&gold_plus_cpu_sleep_0>; 494 }; 495 496 cluster_pd: power-domain-cluster { 497 #power-domain-cells = <0>; 498 domain-idle-states = <&cluster_sleep_0>, 499 <&cluster_sleep_1>; 500 }; 501 }; 502 503 reserved_memory: reserved-memory { 504 #address-cells = <2>; 505 #size-cells = <2>; 506 ranges; 507 508 hyp_mem: hyp@80000000 { 509 reg = <0 0x80000000 0 0xe00000>; 510 no-map; 511 }; 512 513 cpusys_vm_mem: cpusys-vm@80e00000 { 514 reg = <0 0x80e00000 0 0x400000>; 515 no-map; 516 }; 517 518 /* Merged xbl_dtlog, xbl_ramdump and aop_image regions */ 519 xbl_dt_log_merged_mem: xbl-dt-log-merged@81a00000 { 520 reg = <0 0x81a00000 0 0x260000>; 521 no-map; 522 }; 523 524 aop_cmd_db_mem: aop-cmd-db@81c60000 { 525 compatible = "qcom,cmd-db"; 526 reg = <0 0x81c60000 0 0x20000>; 527 no-map; 528 }; 529 530 /* Merged aop_config, tme_crash_dump, tme_log, uefi_log, and chipinfo regions */ 531 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { 532 reg = <0 0x81c80000 0 0x75000>; 533 no-map; 534 }; 535 536 /* Secdata region can be reused by apps */ 537 538 smem: smem@81d00000 { 539 compatible = "qcom,smem"; 540 reg = <0 0x81d00000 0 0x200000>; 541 hwlocks = <&tcsr_mutex 3>; 542 no-map; 543 }; 544 545 adsp_mhi_mem: adsp-mhi@81f00000 { 546 reg = <0 0x81f00000 0 0x20000>; 547 no-map; 548 }; 549 550 pvmfw_mem: pvmfw@824a0000 { 551 reg = <0 0x824a0000 0 0x100000>; 552 no-map; 553 }; 554 555 global_sync_mem: global-sync@82600000 { 556 reg = <0 0x82600000 0 0x100000>; 557 no-map; 558 }; 559 560 tz_stat_mem: tz-stat@82700000 { 561 reg = <0 0x82700000 0 0x100000>; 562 no-map; 563 }; 564 565 qdss_mem: qdss@82800000 { 566 reg = <0 0x82800000 0 0x2000000>; 567 no-map; 568 }; 569 570 qlink_logging_mem: qlink-logging@84800000 { 571 reg = <0 0x84800000 0 0x200000>; 572 no-map; 573 }; 574 575 mpss_dsm_mem: mpss-dsm@86b00000 { 576 reg = <0 0x86b00000 0 0x4900000>; 577 no-map; 578 }; 579 580 mpss_dsm_mem_2: mpss-dsm-2@8b400000 { 581 reg = <0 0x8b400000 0 0x800000>; 582 no-map; 583 }; 584 585 mpss_mem: mpss@8bc00000 { 586 reg = <0 0x8bc00000 0 0xf400000>; 587 no-map; 588 }; 589 590 q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 { 591 reg = <0 0x9b000000 0 0x80000>; 592 no-map; 593 }; 594 595 ipa_fw_mem: ipa-fw@9b080000 { 596 reg = <0 0x9b080000 0 0x10000>; 597 no-map; 598 }; 599 600 ipa_gsi_mem: ipa-gsi@9b090000 { 601 reg = <0 0x9b090000 0 0xa000>; 602 no-map; 603 }; 604 605 gpu_micro_code_mem: gpu-micro-code@9b09a000 { 606 reg = <0 0x9b09a000 0 0x2000>; 607 no-map; 608 }; 609 610 spss_region_mem: spss@9b0a0000 { 611 reg = <0 0x9b0a0000 0 0x1e0000>; 612 no-map; 613 }; 614 615 /* First part of the "SPU secure shared memory" region */ 616 spu_tz_shared_mem: spu-tz-shared@9b280000 { 617 reg = <0 0x9b280000 0 0x60000>; 618 no-map; 619 }; 620 621 /* Second part of the "SPU secure shared memory" region */ 622 spu_modem_shared_mem: spu-modem-shared@9b2e0000 { 623 reg = <0 0x9b2e0000 0 0x20000>; 624 no-map; 625 }; 626 627 camera_mem: camera@9b300000 { 628 reg = <0 0x9b300000 0 0x800000>; 629 no-map; 630 }; 631 632 video_mem: video@9bb00000 { 633 reg = <0 0x9bb00000 0 0x800000>; 634 no-map; 635 }; 636 637 cvp_mem: cvp@9c300000 { 638 reg = <0 0x9c300000 0 0x700000>; 639 no-map; 640 }; 641 642 cdsp_mem: cdsp@9ca00000 { 643 reg = <0 0x9ca00000 0 0x1400000>; 644 no-map; 645 }; 646 647 q6_cdsp_dtb_mem: q6-cdsp-dtb@9de00000 { 648 reg = <0 0x9de00000 0 0x80000>; 649 no-map; 650 }; 651 652 q6_adsp_dtb_mem: q6-adsp-dtb@9de80000 { 653 reg = <0 0x9de80000 0 0x80000>; 654 no-map; 655 }; 656 657 adspslpi_mem: adspslpi@9df00000 { 658 reg = <0 0x9df00000 0 0x4080000>; 659 no-map; 660 }; 661 662 rmtfs_mem: rmtfs@d7c00000 { 663 compatible = "qcom,rmtfs-mem"; 664 reg = <0 0xd7c00000 0 0x400000>; 665 no-map; 666 667 qcom,client-id = <1>; 668 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 669 }; 670 671 /* Merged tz_reserved, xbl_sc, cpucp_fw and qtee regions */ 672 tz_merged_mem: tz-merged@d8000000 { 673 reg = <0 0xd8000000 0 0x800000>; 674 no-map; 675 }; 676 677 hwfence_shbuf: hwfence-shbuf@e6440000 { 678 reg = <0 0xe6440000 0 0x2dd000>; 679 no-map; 680 }; 681 682 trust_ui_vm_mem: trust-ui-vm@f3800000 { 683 reg = <0 0xf3800000 0 0x4400000>; 684 no-map; 685 }; 686 687 oem_vm_mem: oem-vm@f7c00000 { 688 reg = <0 0xf7c00000 0 0x4c00000>; 689 no-map; 690 }; 691 692 llcc_lpi_mem: llcc-lpi@ff800000 { 693 reg = <0 0xff800000 0 0x600000>; 694 no-map; 695 }; 696 }; 697 698 smp2p-adsp { 699 compatible = "qcom,smp2p"; 700 701 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 702 IPCC_MPROC_SIGNAL_SMP2P 703 IRQ_TYPE_EDGE_RISING>; 704 705 mboxes = <&ipcc IPCC_CLIENT_LPASS 706 IPCC_MPROC_SIGNAL_SMP2P>; 707 708 qcom,smem = <443>, <429>; 709 qcom,local-pid = <0>; 710 qcom,remote-pid = <2>; 711 712 smp2p_adsp_out: master-kernel { 713 qcom,entry-name = "master-kernel"; 714 #qcom,smem-state-cells = <1>; 715 }; 716 717 smp2p_adsp_in: slave-kernel { 718 qcom,entry-name = "slave-kernel"; 719 interrupt-controller; 720 #interrupt-cells = <2>; 721 }; 722 }; 723 724 smp2p-cdsp { 725 compatible = "qcom,smp2p"; 726 727 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 728 IPCC_MPROC_SIGNAL_SMP2P 729 IRQ_TYPE_EDGE_RISING>; 730 731 mboxes = <&ipcc IPCC_CLIENT_CDSP 732 IPCC_MPROC_SIGNAL_SMP2P>; 733 734 qcom,smem = <94>, <432>; 735 qcom,local-pid = <0>; 736 qcom,remote-pid = <5>; 737 738 smp2p_cdsp_out: master-kernel { 739 qcom,entry-name = "master-kernel"; 740 #qcom,smem-state-cells = <1>; 741 }; 742 743 smp2p_cdsp_in: slave-kernel { 744 qcom,entry-name = "slave-kernel"; 745 interrupt-controller; 746 #interrupt-cells = <2>; 747 }; 748 }; 749 750 smp2p-modem { 751 compatible = "qcom,smp2p"; 752 753 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 754 IPCC_MPROC_SIGNAL_SMP2P 755 IRQ_TYPE_EDGE_RISING>; 756 757 mboxes = <&ipcc IPCC_CLIENT_MPSS 758 IPCC_MPROC_SIGNAL_SMP2P>; 759 760 qcom,smem = <435>, <428>; 761 qcom,local-pid = <0>; 762 qcom,remote-pid = <1>; 763 764 smp2p_modem_out: master-kernel { 765 qcom,entry-name = "master-kernel"; 766 #qcom,smem-state-cells = <1>; 767 }; 768 769 smp2p_modem_in: slave-kernel { 770 qcom,entry-name = "slave-kernel"; 771 interrupt-controller; 772 #interrupt-cells = <2>; 773 }; 774 775 ipa_smp2p_out: ipa-ap-to-modem { 776 qcom,entry-name = "ipa"; 777 #qcom,smem-state-cells = <1>; 778 }; 779 780 ipa_smp2p_in: ipa-modem-to-ap { 781 qcom,entry-name = "ipa"; 782 interrupt-controller; 783 #interrupt-cells = <2>; 784 }; 785 }; 786 787 soc: soc@0 { 788 compatible = "simple-bus"; 789 790 #address-cells = <2>; 791 #size-cells = <2>; 792 dma-ranges = <0 0 0 0 0x10 0>; 793 ranges = <0 0 0 0 0x10 0>; 794 795 gcc: clock-controller@100000 { 796 compatible = "qcom,sm8650-gcc"; 797 reg = <0 0x00100000 0 0x1f4200>; 798 799 clocks = <&bi_tcxo_div2>, 800 <&bi_tcxo_ao_div2>, 801 <&sleep_clk>, 802 <&pcie0_phy>, 803 <&pcie1_phy QMP_PCIE_PIPE_CLK>, 804 <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, 805 <&ufs_mem_phy 0>, 806 <&ufs_mem_phy 1>, 807 <&ufs_mem_phy 2>, 808 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 809 810 #clock-cells = <1>; 811 #reset-cells = <1>; 812 #power-domain-cells = <1>; 813 }; 814 815 ipcc: mailbox@406000 { 816 compatible = "qcom,sm8650-ipcc", "qcom,ipcc"; 817 reg = <0 0x00406000 0 0x1000>; 818 819 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 820 interrupt-controller; 821 #interrupt-cells = <3>; 822 823 #mbox-cells = <2>; 824 }; 825 826 gpi_dma2: dma-controller@800000 { 827 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; 828 reg = <0 0x00800000 0 0x60000>; 829 830 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 842 843 dma-channels = <12>; 844 dma-channel-mask = <0x3f>; 845 #dma-cells = <3>; 846 847 iommus = <&apps_smmu 0x436 0>; 848 849 dma-coherent; 850 851 status = "disabled"; 852 }; 853 854 qupv3_id_1: geniqup@8c0000 { 855 compatible = "qcom,geni-se-qup"; 856 reg = <0 0x008c0000 0 0x2000>; 857 858 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 859 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 860 clock-names = "m-ahb", 861 "s-ahb"; 862 863 iommus = <&apps_smmu 0x423 0>; 864 865 dma-coherent; 866 867 #address-cells = <2>; 868 #size-cells = <2>; 869 ranges; 870 871 status = "disabled"; 872 873 i2c8: i2c@880000 { 874 compatible = "qcom,geni-i2c"; 875 reg = <0 0x00880000 0 0x4000>; 876 877 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 878 879 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 880 clock-names = "se"; 881 882 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 883 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 884 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 885 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 886 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 887 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 888 interconnect-names = "qup-core", 889 "qup-config", 890 "qup-memory"; 891 892 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 893 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 894 dma-names = "tx", 895 "rx"; 896 897 pinctrl-0 = <&qup_i2c8_data_clk>; 898 pinctrl-names = "default"; 899 900 #address-cells = <1>; 901 #size-cells = <0>; 902 903 status = "disabled"; 904 }; 905 906 spi8: spi@880000 { 907 compatible = "qcom,geni-spi"; 908 reg = <0 0x00880000 0 0x4000>; 909 910 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 911 912 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 913 clock-names = "se"; 914 915 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 916 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 917 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 918 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 919 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 920 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 921 interconnect-names = "qup-core", 922 "qup-config", 923 "qup-memory"; 924 925 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 926 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 927 dma-names = "tx", 928 "rx"; 929 930 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 931 pinctrl-names = "default"; 932 933 #address-cells = <1>; 934 #size-cells = <0>; 935 936 status = "disabled"; 937 }; 938 939 i2c9: i2c@884000 { 940 compatible = "qcom,geni-i2c"; 941 reg = <0 0x00884000 0 0x4000>; 942 943 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 944 945 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 946 clock-names = "se"; 947 948 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 949 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 950 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 951 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 952 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 953 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 954 interconnect-names = "qup-core", 955 "qup-config", 956 "qup-memory"; 957 958 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 959 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 960 dma-names = "tx", 961 "rx"; 962 963 pinctrl-0 = <&qup_i2c9_data_clk>; 964 pinctrl-names = "default"; 965 966 #address-cells = <1>; 967 #size-cells = <0>; 968 969 status = "disabled"; 970 }; 971 972 spi9: spi@884000 { 973 compatible = "qcom,geni-spi"; 974 reg = <0 0x00884000 0 0x4000>; 975 976 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 977 978 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 979 clock-names = "se"; 980 981 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 982 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 983 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 984 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 985 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 986 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 987 interconnect-names = "qup-core", 988 "qup-config", 989 "qup-memory"; 990 991 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 992 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 993 dma-names = "tx", 994 "rx"; 995 996 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 997 pinctrl-names = "default"; 998 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 1002 status = "disabled"; 1003 }; 1004 1005 i2c10: i2c@888000 { 1006 compatible = "qcom,geni-i2c"; 1007 reg = <0 0x00888000 0 0x4000>; 1008 1009 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1010 1011 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1012 clock-names = "se"; 1013 1014 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1015 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1016 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1017 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1018 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1019 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1020 interconnect-names = "qup-core", 1021 "qup-config", 1022 "qup-memory"; 1023 1024 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1025 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1026 dma-names = "tx", 1027 "rx"; 1028 1029 pinctrl-0 = <&qup_i2c10_data_clk>; 1030 pinctrl-names = "default"; 1031 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 1035 status = "disabled"; 1036 }; 1037 1038 spi10: spi@888000 { 1039 compatible = "qcom,geni-spi"; 1040 reg = <0 0x00888000 0 0x4000>; 1041 1042 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1043 1044 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1045 clock-names = "se"; 1046 1047 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1048 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1049 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1050 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1051 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1052 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1053 interconnect-names = "qup-core", 1054 "qup-config", 1055 "qup-memory"; 1056 1057 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1058 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1059 dma-names = "tx", 1060 "rx"; 1061 1062 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1063 pinctrl-names = "default"; 1064 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 1068 status = "disabled"; 1069 }; 1070 1071 i2c11: i2c@88c000 { 1072 compatible = "qcom,geni-i2c"; 1073 reg = <0 0x0088c000 0 0x4000>; 1074 1075 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1076 1077 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1078 clock-names = "se"; 1079 1080 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1081 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1082 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1083 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1084 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1085 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1086 interconnect-names = "qup-core", 1087 "qup-config", 1088 "qup-memory"; 1089 1090 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1091 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1092 dma-names = "tx", 1093 "rx"; 1094 1095 pinctrl-0 = <&qup_i2c11_data_clk>; 1096 pinctrl-names = "default"; 1097 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 1101 status = "disabled"; 1102 }; 1103 1104 spi11: spi@88c000 { 1105 compatible = "qcom,geni-spi"; 1106 reg = <0 0x0088c000 0 0x4000>; 1107 1108 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1109 1110 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1111 clock-names = "se"; 1112 1113 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1114 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1115 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1116 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1117 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1118 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1119 interconnect-names = "qup-core", 1120 "qup-config", 1121 "qup-memory"; 1122 1123 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1124 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1125 dma-names = "tx", 1126 "rx"; 1127 1128 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1129 pinctrl-names = "default"; 1130 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 1134 status = "disabled"; 1135 }; 1136 1137 i2c12: i2c@890000 { 1138 compatible = "qcom,geni-i2c"; 1139 reg = <0 0x00890000 0 0x4000>; 1140 1141 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1142 1143 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1144 clock-names = "se"; 1145 1146 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1147 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1148 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1149 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1150 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1151 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1152 interconnect-names = "qup-core", 1153 "qup-config", 1154 "qup-memory"; 1155 1156 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1157 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1158 dma-names = "tx", 1159 "rx"; 1160 1161 pinctrl-0 = <&qup_i2c12_data_clk>; 1162 pinctrl-names = "default"; 1163 1164 #address-cells = <1>; 1165 #size-cells = <0>; 1166 1167 status = "disabled"; 1168 }; 1169 1170 spi12: spi@890000 { 1171 compatible = "qcom,geni-spi"; 1172 reg = <0 0x00890000 0 0x4000>; 1173 1174 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1175 1176 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1177 clock-names = "se"; 1178 1179 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1180 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1181 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1182 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1183 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1184 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1185 interconnect-names = "qup-core", 1186 "qup-config", 1187 "qup-memory"; 1188 1189 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1190 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1191 dma-names = "tx", 1192 "rx"; 1193 1194 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1195 pinctrl-names = "default"; 1196 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 1200 status = "disabled"; 1201 }; 1202 1203 i2c13: i2c@894000 { 1204 compatible = "qcom,geni-i2c"; 1205 reg = <0 0x00894000 0 0x4000>; 1206 1207 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1208 1209 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1210 clock-names = "se"; 1211 1212 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1213 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1214 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1215 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1216 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1217 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1218 interconnect-names = "qup-core", 1219 "qup-config", 1220 "qup-memory"; 1221 1222 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1223 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1224 dma-names = "tx", 1225 "rx"; 1226 1227 pinctrl-0 = <&qup_i2c13_data_clk>; 1228 pinctrl-names = "default"; 1229 1230 #address-cells = <1>; 1231 #size-cells = <0>; 1232 1233 status = "disabled"; 1234 }; 1235 1236 spi13: spi@894000 { 1237 compatible = "qcom,geni-spi"; 1238 reg = <0 0x00894000 0 0x4000>; 1239 1240 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1241 1242 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1243 clock-names = "se"; 1244 1245 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1246 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1247 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1248 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1249 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1250 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1251 interconnect-names = "qup-core", 1252 "qup-config", 1253 "qup-memory"; 1254 1255 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1256 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1257 dma-names = "tx", 1258 "rx"; 1259 1260 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1261 pinctrl-names = "default"; 1262 1263 #address-cells = <1>; 1264 #size-cells = <0>; 1265 1266 status = "disabled"; 1267 }; 1268 1269 uart14: serial@898000 { 1270 compatible = "qcom,geni-uart"; 1271 reg = <0 0x00898000 0 0x4000>; 1272 1273 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1274 1275 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1276 clock-names = "se"; 1277 1278 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1279 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1280 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1281 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1282 interconnect-names = "qup-core", 1283 "qup-config"; 1284 1285 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; 1286 pinctrl-names = "default"; 1287 1288 status = "disabled"; 1289 }; 1290 1291 uart15: serial@89c000 { 1292 compatible = "qcom,geni-debug-uart"; 1293 reg = <0 0x0089c000 0 0x4000>; 1294 1295 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1296 1297 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1298 clock-names = "se"; 1299 1300 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1301 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1302 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1303 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1304 interconnect-names = "qup-core", 1305 "qup-config"; 1306 1307 pinctrl-0 = <&qup_uart15_default>; 1308 pinctrl-names = "default"; 1309 1310 status = "disabled"; 1311 }; 1312 }; 1313 1314 i2c_master_hub_0: geniqup@9c0000 { 1315 compatible = "qcom,geni-se-i2c-master-hub"; 1316 reg = <0 0x009c0000 0 0x2000>; 1317 1318 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1319 clock-names = "s-ahb"; 1320 1321 #address-cells = <2>; 1322 #size-cells = <2>; 1323 ranges; 1324 1325 status = "disabled"; 1326 1327 i2c_hub_0: i2c@980000 { 1328 compatible = "qcom,geni-i2c-master-hub"; 1329 reg = <0 0x00980000 0 0x4000>; 1330 1331 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1332 1333 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1334 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1335 clock-names = "se", 1336 "core"; 1337 1338 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1339 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1340 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1341 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1342 interconnect-names = "qup-core", 1343 "qup-config"; 1344 1345 pinctrl-0 = <&hub_i2c0_data_clk>; 1346 pinctrl-names = "default"; 1347 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 1351 status = "disabled"; 1352 }; 1353 1354 i2c_hub_1: i2c@984000 { 1355 compatible = "qcom,geni-i2c-master-hub"; 1356 reg = <0 0x00984000 0 0x4000>; 1357 1358 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1359 1360 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1361 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1362 clock-names = "se", 1363 "core"; 1364 1365 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1366 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1367 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1368 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1369 interconnect-names = "qup-core", 1370 "qup-config"; 1371 1372 pinctrl-0 = <&hub_i2c1_data_clk>; 1373 pinctrl-names = "default"; 1374 1375 #address-cells = <1>; 1376 #size-cells = <0>; 1377 1378 status = "disabled"; 1379 }; 1380 1381 i2c_hub_2: i2c@988000 { 1382 compatible = "qcom,geni-i2c-master-hub"; 1383 reg = <0 0x00988000 0 0x4000>; 1384 1385 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1386 1387 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1388 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1389 clock-names = "se", 1390 "core"; 1391 1392 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1393 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1394 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1395 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1396 interconnect-names = "qup-core", 1397 "qup-config"; 1398 1399 pinctrl-0 = <&hub_i2c2_data_clk>; 1400 pinctrl-names = "default"; 1401 1402 #address-cells = <1>; 1403 #size-cells = <0>; 1404 1405 status = "disabled"; 1406 }; 1407 1408 i2c_hub_3: i2c@98c000 { 1409 compatible = "qcom,geni-i2c-master-hub"; 1410 reg = <0 0x0098c000 0 0x4000>; 1411 1412 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1413 1414 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1415 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1416 clock-names = "se", 1417 "core"; 1418 1419 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1420 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1421 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1422 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1423 interconnect-names = "qup-core", 1424 "qup-config"; 1425 1426 pinctrl-0 = <&hub_i2c3_data_clk>; 1427 pinctrl-names = "default"; 1428 1429 #address-cells = <1>; 1430 #size-cells = <0>; 1431 1432 status = "disabled"; 1433 }; 1434 1435 i2c_hub_4: i2c@990000 { 1436 compatible = "qcom,geni-i2c-master-hub"; 1437 reg = <0 0x00990000 0 0x4000>; 1438 1439 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1440 1441 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1442 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1443 clock-names = "se", 1444 "core"; 1445 1446 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1447 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1448 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1449 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1450 interconnect-names = "qup-core", 1451 "qup-config"; 1452 1453 pinctrl-0 = <&hub_i2c4_data_clk>; 1454 pinctrl-names = "default"; 1455 1456 #address-cells = <1>; 1457 #size-cells = <0>; 1458 1459 status = "disabled"; 1460 }; 1461 1462 i2c_hub_5: i2c@994000 { 1463 compatible = "qcom,geni-i2c-master-hub"; 1464 reg = <0 0x00994000 0 0x4000>; 1465 1466 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1467 1468 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1469 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1470 clock-names = "se", 1471 "core"; 1472 1473 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1474 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1475 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1476 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1477 interconnect-names = "qup-core", 1478 "qup-config"; 1479 1480 pinctrl-0 = <&hub_i2c5_data_clk>; 1481 pinctrl-names = "default"; 1482 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 1486 status = "disabled"; 1487 }; 1488 1489 i2c_hub_6: i2c@998000 { 1490 compatible = "qcom,geni-i2c-master-hub"; 1491 reg = <0 0x00998000 0 0x4000>; 1492 1493 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1494 1495 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1496 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1497 clock-names = "se", 1498 "core"; 1499 1500 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1501 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1502 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1503 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1504 interconnect-names = "qup-core", 1505 "qup-config"; 1506 1507 pinctrl-0 = <&hub_i2c6_data_clk>; 1508 pinctrl-names = "default"; 1509 1510 #address-cells = <1>; 1511 #size-cells = <0>; 1512 1513 status = "disabled"; 1514 }; 1515 1516 i2c_hub_7: i2c@99c000 { 1517 compatible = "qcom,geni-i2c-master-hub"; 1518 reg = <0 0x0099c000 0 0x4000>; 1519 1520 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1521 1522 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1523 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1524 clock-names = "se", 1525 "core"; 1526 1527 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1528 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1529 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1530 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1531 interconnect-names = "qup-core", 1532 "qup-config"; 1533 1534 pinctrl-0 = <&hub_i2c7_data_clk>; 1535 pinctrl-names = "default"; 1536 1537 #address-cells = <1>; 1538 #size-cells = <0>; 1539 1540 status = "disabled"; 1541 }; 1542 1543 i2c_hub_8: i2c@9a0000 { 1544 compatible = "qcom,geni-i2c-master-hub"; 1545 reg = <0 0x009a0000 0 0x4000>; 1546 1547 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1548 1549 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1550 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1551 clock-names = "se", 1552 "core"; 1553 1554 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1555 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1556 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1557 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1558 interconnect-names = "qup-core", 1559 "qup-config"; 1560 1561 pinctrl-0 = <&hub_i2c8_data_clk>; 1562 pinctrl-names = "default"; 1563 1564 #address-cells = <1>; 1565 #size-cells = <0>; 1566 1567 status = "disabled"; 1568 }; 1569 1570 i2c_hub_9: i2c@9a4000 { 1571 compatible = "qcom,geni-i2c-master-hub"; 1572 reg = <0 0x009a4000 0 0x4000>; 1573 1574 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1575 1576 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1577 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1578 clock-names = "se", 1579 "core"; 1580 1581 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1582 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1583 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1584 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1585 interconnect-names = "qup-core", 1586 "qup-config"; 1587 1588 pinctrl-0 = <&hub_i2c9_data_clk>; 1589 pinctrl-names = "default"; 1590 1591 #address-cells = <1>; 1592 #size-cells = <0>; 1593 1594 status = "disabled"; 1595 }; 1596 }; 1597 1598 gpi_dma1: dma-controller@a00000 { 1599 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; 1600 reg = <0 0x00a00000 0 0x60000>; 1601 1602 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1614 1615 dma-channels = <12>; 1616 dma-channel-mask = <0xc>; 1617 #dma-cells = <3>; 1618 1619 iommus = <&apps_smmu 0xb6 0>; 1620 dma-coherent; 1621 1622 status = "disabled"; 1623 }; 1624 1625 qupv3_id_0: geniqup@ac0000 { 1626 compatible = "qcom,geni-se-qup"; 1627 reg = <0 0x00ac0000 0 0x2000>; 1628 1629 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1630 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1631 clock-names = "m-ahb", 1632 "s-ahb"; 1633 1634 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1635 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; 1636 interconnect-names = "qup-core"; 1637 1638 iommus = <&apps_smmu 0xa3 0>; 1639 1640 dma-coherent; 1641 1642 #address-cells = <2>; 1643 #size-cells = <2>; 1644 ranges; 1645 1646 status = "disabled"; 1647 1648 i2c0: i2c@a80000 { 1649 compatible = "qcom,geni-i2c"; 1650 reg = <0 0x00a80000 0 0x4000>; 1651 1652 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1653 1654 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1655 clock-names = "se"; 1656 1657 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1658 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1659 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1660 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1661 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1662 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1663 interconnect-names = "qup-core", 1664 "qup-config", 1665 "qup-memory"; 1666 1667 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1668 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1669 dma-names = "tx", 1670 "rx"; 1671 1672 pinctrl-0 = <&qup_i2c0_data_clk>; 1673 pinctrl-names = "default"; 1674 1675 #address-cells = <1>; 1676 #size-cells = <0>; 1677 1678 status = "disabled"; 1679 }; 1680 1681 spi0: spi@a80000 { 1682 compatible = "qcom,geni-spi"; 1683 reg = <0 0x00a80000 0 0x4000>; 1684 1685 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1686 1687 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1688 clock-names = "se"; 1689 1690 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1691 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1692 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1693 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1694 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1695 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1696 interconnect-names = "qup-core", 1697 "qup-config", 1698 "qup-memory"; 1699 1700 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1701 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1702 dma-names = "tx", 1703 "rx"; 1704 1705 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1706 pinctrl-names = "default"; 1707 1708 #address-cells = <1>; 1709 #size-cells = <0>; 1710 1711 status = "disabled"; 1712 }; 1713 1714 i2c1: i2c@a84000 { 1715 compatible = "qcom,geni-i2c"; 1716 reg = <0 0x00a84000 0 0x4000>; 1717 1718 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1719 1720 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1721 clock-names = "se"; 1722 1723 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1724 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1725 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1726 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1727 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1728 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1729 interconnect-names = "qup-core", 1730 "qup-config", 1731 "qup-memory"; 1732 1733 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1734 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1735 dma-names = "tx", 1736 "rx"; 1737 1738 pinctrl-0 = <&qup_i2c1_data_clk>; 1739 pinctrl-names = "default"; 1740 1741 #address-cells = <1>; 1742 #size-cells = <0>; 1743 1744 status = "disabled"; 1745 }; 1746 1747 spi1: spi@a84000 { 1748 compatible = "qcom,geni-spi"; 1749 reg = <0 0x00a84000 0 0x4000>; 1750 1751 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1752 1753 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1754 clock-names = "se"; 1755 1756 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1757 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1758 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1759 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1760 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1761 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1762 interconnect-names = "qup-core", 1763 "qup-config", 1764 "qup-memory"; 1765 1766 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1767 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1768 dma-names = "tx", 1769 "rx"; 1770 1771 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1772 pinctrl-names = "default"; 1773 1774 #address-cells = <1>; 1775 #size-cells = <0>; 1776 1777 status = "disabled"; 1778 }; 1779 1780 i2c2: i2c@a88000 { 1781 compatible = "qcom,geni-i2c"; 1782 reg = <0 0x00a88000 0 0x4000>; 1783 1784 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1785 1786 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1787 clock-names = "se"; 1788 1789 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1790 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1791 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1792 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1793 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1794 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1795 interconnect-names = "qup-core", 1796 "qup-config", 1797 "qup-memory"; 1798 1799 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1800 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1801 dma-names = "tx", 1802 "rx"; 1803 1804 pinctrl-0 = <&qup_i2c2_data_clk>; 1805 pinctrl-names = "default"; 1806 1807 #address-cells = <1>; 1808 #size-cells = <0>; 1809 1810 status = "disabled"; 1811 }; 1812 1813 spi2: spi@a88000 { 1814 compatible = "qcom,geni-spi"; 1815 reg = <0 0x00a88000 0 0x4000>; 1816 1817 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1818 1819 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1820 clock-names = "se"; 1821 1822 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1823 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1824 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1825 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1826 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1827 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1828 interconnect-names = "qup-core", 1829 "qup-config", 1830 "qup-memory"; 1831 1832 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1833 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1834 dma-names = "tx", 1835 "rx"; 1836 1837 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1838 pinctrl-names = "default"; 1839 1840 #address-cells = <1>; 1841 #size-cells = <0>; 1842 1843 status = "disabled"; 1844 }; 1845 1846 i2c3: i2c@a8c000 { 1847 compatible = "qcom,geni-i2c"; 1848 reg = <0 0x00a8c000 0 0x4000>; 1849 1850 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1851 1852 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1853 clock-names = "se"; 1854 1855 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1856 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1857 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1858 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1859 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1860 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1861 interconnect-names = "qup-core", 1862 "qup-config", 1863 "qup-memory"; 1864 1865 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1866 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1867 dma-names = "tx", 1868 "rx"; 1869 1870 pinctrl-0 = <&qup_i2c3_data_clk>; 1871 pinctrl-names = "default"; 1872 1873 #address-cells = <1>; 1874 #size-cells = <0>; 1875 1876 status = "disabled"; 1877 }; 1878 1879 spi3: spi@a8c000 { 1880 compatible = "qcom,geni-spi"; 1881 reg = <0 0x00a8c000 0 0x4000>; 1882 1883 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1884 1885 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1886 clock-names = "se"; 1887 1888 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1889 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1890 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1891 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1892 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1893 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1894 interconnect-names = "qup-core", 1895 "qup-config", 1896 "qup-memory"; 1897 1898 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1899 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1900 dma-names = "tx", 1901 "rx"; 1902 1903 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1904 pinctrl-names = "default"; 1905 1906 #address-cells = <1>; 1907 #size-cells = <0>; 1908 1909 status = "disabled"; 1910 }; 1911 1912 i2c4: i2c@a90000 { 1913 compatible = "qcom,geni-i2c"; 1914 reg = <0 0x00a90000 0 0x4000>; 1915 1916 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1917 1918 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1919 clock-names = "se"; 1920 1921 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1922 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1923 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1924 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1925 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1926 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1927 interconnect-names = "qup-core", 1928 "qup-config", 1929 "qup-memory"; 1930 1931 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1932 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1933 dma-names = "tx", 1934 "rx"; 1935 1936 pinctrl-0 = <&qup_i2c4_data_clk>; 1937 pinctrl-names = "default"; 1938 1939 #address-cells = <1>; 1940 #size-cells = <0>; 1941 1942 status = "disabled"; 1943 }; 1944 1945 spi4: spi@a90000 { 1946 compatible = "qcom,geni-spi"; 1947 reg = <0 0x00a90000 0 0x4000>; 1948 1949 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1950 1951 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1952 clock-names = "se"; 1953 1954 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1955 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1956 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1957 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1958 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1959 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1960 interconnect-names = "qup-core", 1961 "qup-config", 1962 "qup-memory"; 1963 1964 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1965 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1966 dma-names = "tx", 1967 "rx"; 1968 1969 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1970 pinctrl-names = "default"; 1971 1972 #address-cells = <1>; 1973 #size-cells = <0>; 1974 1975 status = "disabled"; 1976 }; 1977 1978 i2c5: i2c@a94000 { 1979 compatible = "qcom,geni-i2c"; 1980 reg = <0 0x00a94000 0 0x4000>; 1981 1982 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1983 1984 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1985 clock-names = "se"; 1986 1987 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1988 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1989 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1990 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1991 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1992 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1993 interconnect-names = "qup-core", 1994 "qup-config", 1995 "qup-memory"; 1996 1997 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1998 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1999 dma-names = "tx", 2000 "rx"; 2001 2002 pinctrl-0 = <&qup_i2c5_data_clk>; 2003 pinctrl-names = "default"; 2004 2005 #address-cells = <1>; 2006 #size-cells = <0>; 2007 2008 status = "disabled"; 2009 }; 2010 2011 spi5: spi@a94000 { 2012 compatible = "qcom,geni-spi"; 2013 reg = <0 0x00a94000 0 0x4000>; 2014 2015 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2016 2017 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2018 clock-names = "se"; 2019 2020 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2021 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2022 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2023 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2024 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2025 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2026 interconnect-names = "qup-core", 2027 "qup-config", 2028 "qup-memory"; 2029 2030 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2031 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2032 dma-names = "tx", 2033 "rx"; 2034 2035 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2036 pinctrl-names = "default"; 2037 2038 #address-cells = <1>; 2039 #size-cells = <0>; 2040 2041 status = "disabled"; 2042 }; 2043 2044 i2c6: i2c@a98000 { 2045 compatible = "qcom,geni-i2c"; 2046 reg = <0 0x00a98000 0 0x4000>; 2047 2048 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 2049 2050 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2051 clock-names = "se"; 2052 2053 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2054 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2055 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2056 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2057 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2058 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2059 interconnect-names = "qup-core", 2060 "qup-config", 2061 "qup-memory"; 2062 2063 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2064 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2065 dma-names = "tx", 2066 "rx"; 2067 2068 pinctrl-0 = <&qup_i2c6_data_clk>; 2069 pinctrl-names = "default"; 2070 2071 #address-cells = <1>; 2072 #size-cells = <0>; 2073 2074 status = "disabled"; 2075 }; 2076 2077 spi6: spi@a98000 { 2078 compatible = "qcom,geni-spi"; 2079 reg = <0 0x00a98000 0 0x4000>; 2080 2081 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 2082 2083 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2084 clock-names = "se"; 2085 2086 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2087 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2088 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2089 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2090 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2091 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2092 interconnect-names = "qup-core", 2093 "qup-config", 2094 "qup-memory"; 2095 2096 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2097 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2098 dma-names = "tx", 2099 "rx"; 2100 2101 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2102 pinctrl-names = "default"; 2103 2104 #address-cells = <1>; 2105 #size-cells = <0>; 2106 2107 status = "disabled"; 2108 }; 2109 2110 i2c7: i2c@a9c000 { 2111 compatible = "qcom,geni-i2c"; 2112 reg = <0 0x00a9c000 0 0x4000>; 2113 2114 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 2115 2116 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2117 clock-names = "se"; 2118 2119 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2120 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2121 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2122 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2123 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2124 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2125 interconnect-names = "qup-core", 2126 "qup-config", 2127 "qup-memory"; 2128 2129 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2130 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2131 dma-names = "tx", 2132 "rx"; 2133 2134 pinctrl-0 = <&qup_i2c7_data_clk>; 2135 pinctrl-names = "default"; 2136 2137 #address-cells = <1>; 2138 #size-cells = <0>; 2139 2140 status = "disabled"; 2141 }; 2142 2143 spi7: spi@a9c000 { 2144 compatible = "qcom,geni-spi"; 2145 reg = <0 0x00a9c000 0 0x4000>; 2146 2147 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 2148 2149 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2150 clock-names = "se"; 2151 2152 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2153 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2154 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2155 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2156 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2157 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2158 interconnect-names = "qup-core", 2159 "qup-config", 2160 "qup-memory"; 2161 2162 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2163 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2164 dma-names = "tx", 2165 "rx"; 2166 2167 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2168 pinctrl-names = "default"; 2169 2170 #address-cells = <1>; 2171 #size-cells = <0>; 2172 2173 status = "disabled"; 2174 }; 2175 }; 2176 2177 cnoc_main: interconnect@1500000 { 2178 compatible = "qcom,sm8650-cnoc-main"; 2179 reg = <0 0x01500000 0 0x14080>; 2180 2181 qcom,bcm-voters = <&apps_bcm_voter>; 2182 2183 #interconnect-cells = <2>; 2184 }; 2185 2186 config_noc: interconnect@1600000 { 2187 compatible = "qcom,sm8650-config-noc"; 2188 reg = <0 0x01600000 0 0x6200>; 2189 2190 qcom,bcm-voters = <&apps_bcm_voter>; 2191 2192 #interconnect-cells = <2>; 2193 }; 2194 2195 system_noc: interconnect@1680000 { 2196 compatible = "qcom,sm8650-system-noc"; 2197 reg = <0 0x01680000 0 0x1d080>; 2198 2199 qcom,bcm-voters = <&apps_bcm_voter>; 2200 2201 #interconnect-cells = <2>; 2202 }; 2203 2204 pcie_noc: interconnect@16c0000 { 2205 compatible = "qcom,sm8650-pcie-anoc"; 2206 reg = <0 0x016c0000 0 0x12200>; 2207 2208 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 2209 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 2210 2211 qcom,bcm-voters = <&apps_bcm_voter>; 2212 2213 #interconnect-cells = <2>; 2214 }; 2215 2216 aggre1_noc: interconnect@16e0000 { 2217 compatible = "qcom,sm8650-aggre1-noc"; 2218 reg = <0 0x016e0000 0 0x16400>; 2219 2220 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2221 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2222 2223 qcom,bcm-voters = <&apps_bcm_voter>; 2224 2225 #interconnect-cells = <2>; 2226 }; 2227 2228 aggre2_noc: interconnect@1700000 { 2229 compatible = "qcom,sm8650-aggre2-noc"; 2230 reg = <0 0x01700000 0 0x1e400>; 2231 2232 clocks = <&rpmhcc RPMH_IPA_CLK>; 2233 2234 qcom,bcm-voters = <&apps_bcm_voter>; 2235 2236 #interconnect-cells = <2>; 2237 }; 2238 2239 mmss_noc: interconnect@1780000 { 2240 compatible = "qcom,sm8650-mmss-noc"; 2241 reg = <0 0x01780000 0 0x5b800>; 2242 2243 qcom,bcm-voters = <&apps_bcm_voter>; 2244 2245 #interconnect-cells = <2>; 2246 }; 2247 2248 rng: rng@10c3000 { 2249 compatible = "qcom,sm8650-trng", "qcom,trng"; 2250 reg = <0 0x010c3000 0 0x1000>; 2251 }; 2252 2253 pcie0: pcie@1c00000 { 2254 device_type = "pci"; 2255 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; 2256 reg = <0 0x01c00000 0 0x3000>, 2257 <0 0x60000000 0 0xf1d>, 2258 <0 0x60000f20 0 0xa8>, 2259 <0 0x60001000 0 0x1000>, 2260 <0 0x60100000 0 0x100000>; 2261 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2262 2263 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2264 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2265 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2266 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2267 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2268 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2269 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2270 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2271 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2272 interrupt-names = "msi0", 2273 "msi1", 2274 "msi2", 2275 "msi3", 2276 "msi4", 2277 "msi5", 2278 "msi6", 2279 "msi7", 2280 "global"; 2281 2282 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2283 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2284 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2285 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2286 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2287 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 2288 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 2289 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 2290 clock-names = "aux", 2291 "cfg", 2292 "bus_master", 2293 "bus_slave", 2294 "slave_q2a", 2295 "ddrss_sf_tbu", 2296 "noc_aggr", 2297 "cnoc_sf_axi"; 2298 2299 resets = <&gcc GCC_PCIE_0_BCR>; 2300 reset-names = "pci"; 2301 2302 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 2303 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2304 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2305 &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; 2306 interconnect-names = "pcie-mem", 2307 "cpu-pcie"; 2308 2309 power-domains = <&gcc PCIE_0_GDSC>; 2310 2311 iommu-map = <0 &apps_smmu 0x1400 0x1>, 2312 <0x100 &apps_smmu 0x1401 0x1>; 2313 2314 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, 2315 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, 2316 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, 2317 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; 2318 interrupt-map-mask = <0 0 0 0x7>; 2319 #interrupt-cells = <1>; 2320 2321 msi-map = <0x0 &gic_its 0x1400 0x1>, 2322 <0x100 &gic_its 0x1401 0x1>; 2323 msi-map-mask = <0xff00>; 2324 2325 linux,pci-domain = <0>; 2326 num-lanes = <2>; 2327 bus-range = <0 0xff>; 2328 2329 phys = <&pcie0_phy>; 2330 phy-names = "pciephy"; 2331 2332 #address-cells = <3>; 2333 #size-cells = <2>; 2334 ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>, 2335 <0x02000000 0 0x60300000 0 0x60300000 0 0x3d00000>; 2336 2337 dma-coherent; 2338 2339 status = "disabled"; 2340 2341 pcieport0: pcie@0 { 2342 device_type = "pci"; 2343 reg = <0x0 0x0 0x0 0x0 0x0>; 2344 bus-range = <0x01 0xff>; 2345 2346 #address-cells = <3>; 2347 #size-cells = <2>; 2348 ranges; 2349 }; 2350 }; 2351 2352 pcie0_phy: phy@1c06000 { 2353 compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy"; 2354 reg = <0 0x01c06000 0 0x2000>; 2355 2356 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2357 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2358 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 2359 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 2360 <&gcc GCC_PCIE_0_PIPE_CLK>; 2361 clock-names = "aux", 2362 "cfg_ahb", 2363 "ref", 2364 "rchng", 2365 "pipe"; 2366 2367 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 2368 assigned-clock-rates = <100000000>; 2369 2370 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2371 reset-names = "phy"; 2372 2373 power-domains = <&gcc PCIE_0_PHY_GDSC>; 2374 2375 #clock-cells = <0>; 2376 clock-output-names = "pcie0_pipe_clk"; 2377 2378 #phy-cells = <0>; 2379 2380 status = "disabled"; 2381 }; 2382 2383 pcie1: pcie@1c08000 { 2384 device_type = "pci"; 2385 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; 2386 reg = <0 0x01c08000 0 0x3000>, 2387 <0 0x40000000 0 0xf1d>, 2388 <0 0x40000f20 0 0xa8>, 2389 <0 0x40001000 0 0x1000>, 2390 <0 0x40100000 0 0x100000>; 2391 reg-names = "parf", 2392 "dbi", 2393 "elbi", 2394 "atu", 2395 "config"; 2396 2397 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2398 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2399 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2400 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2401 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2402 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2403 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2404 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2405 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 2406 interrupt-names = "msi0", 2407 "msi1", 2408 "msi2", 2409 "msi3", 2410 "msi4", 2411 "msi5", 2412 "msi6", 2413 "msi7", 2414 "global"; 2415 2416 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2417 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2418 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2419 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2420 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2421 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 2422 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 2423 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 2424 clock-names = "aux", 2425 "cfg", 2426 "bus_master", 2427 "bus_slave", 2428 "slave_q2a", 2429 "ddrss_sf_tbu", 2430 "noc_aggr", 2431 "cnoc_sf_axi"; 2432 2433 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2434 assigned-clock-rates = <19200000>; 2435 2436 resets = <&gcc GCC_PCIE_1_BCR>, 2437 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 2438 reset-names = "pci", 2439 "link_down"; 2440 2441 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 2442 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2443 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2444 &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; 2445 interconnect-names = "pcie-mem", 2446 "cpu-pcie"; 2447 2448 power-domains = <&gcc PCIE_1_GDSC>; 2449 2450 iommu-map = <0 &apps_smmu 0x1480 0x1>, 2451 <0x100 &apps_smmu 0x1481 0x1>; 2452 2453 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2454 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2455 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2456 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2457 interrupt-map-mask = <0 0 0 0x7>; 2458 #interrupt-cells = <1>; 2459 2460 msi-map = <0x0 &gic_its 0x1480 0x1>, 2461 <0x100 &gic_its 0x1481 0x1>; 2462 msi-map-mask = <0xff00>; 2463 2464 linux,pci-domain = <1>; 2465 num-lanes = <2>; 2466 bus-range = <0 0xff>; 2467 2468 phys = <&pcie1_phy>; 2469 phy-names = "pciephy"; 2470 2471 dma-coherent; 2472 2473 #address-cells = <3>; 2474 #size-cells = <2>; 2475 ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>, 2476 <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>; 2477 2478 status = "disabled"; 2479 2480 pcie@0 { 2481 device_type = "pci"; 2482 reg = <0x0 0x0 0x0 0x0 0x0>; 2483 bus-range = <0x01 0xff>; 2484 2485 #address-cells = <3>; 2486 #size-cells = <2>; 2487 ranges; 2488 }; 2489 }; 2490 2491 pcie1_phy: phy@1c0e000 { 2492 compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy"; 2493 reg = <0 0x01c0e000 0 0x2000>; 2494 2495 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 2496 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2497 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 2498 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 2499 <&gcc GCC_PCIE_1_PIPE_CLK>; 2500 clock-names = "aux", 2501 "cfg_ahb", 2502 "ref", 2503 "rchng", 2504 "pipe"; 2505 2506 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 2507 assigned-clock-rates = <100000000>; 2508 2509 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 2510 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 2511 reset-names = "phy", 2512 "phy_nocsr"; 2513 2514 power-domains = <&gcc PCIE_1_PHY_GDSC>; 2515 2516 #clock-cells = <1>; 2517 clock-output-names = "pcie1_pipe_clk"; 2518 2519 #phy-cells = <0>; 2520 2521 status = "disabled"; 2522 }; 2523 2524 cryptobam: dma-controller@1dc4000 { 2525 compatible = "qcom,bam-v1.7.0"; 2526 reg = <0 0x01dc4000 0 0x28000>; 2527 2528 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2529 2530 #dma-cells = <1>; 2531 2532 iommus = <&apps_smmu 0x480 0>, 2533 <&apps_smmu 0x481 0>; 2534 2535 qcom,ee = <0>; 2536 qcom,controlled-remotely; 2537 }; 2538 2539 crypto: crypto@1dfa000 { 2540 compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce"; 2541 reg = <0 0x01dfa000 0 0x6000>; 2542 2543 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 2544 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2545 interconnect-names = "memory"; 2546 2547 dmas = <&cryptobam 4>, <&cryptobam 5>; 2548 dma-names = "rx", "tx"; 2549 2550 iommus = <&apps_smmu 0x480 0>, 2551 <&apps_smmu 0x481 0>; 2552 }; 2553 2554 ufs_mem_phy: phy@1d80000 { 2555 compatible = "qcom,sm8650-qmp-ufs-phy"; 2556 reg = <0 0x01d80000 0 0x2000>; 2557 2558 clocks = <&rpmhcc RPMH_CXO_CLK>, 2559 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2560 <&tcsr TCSR_UFS_CLKREF_EN>; 2561 clock-names = "ref", 2562 "ref_aux", 2563 "qref"; 2564 2565 resets = <&ufs_mem_hc 0>; 2566 reset-names = "ufsphy"; 2567 2568 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 2569 2570 #clock-cells = <1>; 2571 #phy-cells = <0>; 2572 2573 status = "disabled"; 2574 }; 2575 2576 ufs_mem_hc: ufshc@1d84000 { 2577 compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 2578 reg = <0 0x01d84000 0 0x3000>; 2579 2580 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2581 2582 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2583 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2584 <&gcc GCC_UFS_PHY_AHB_CLK>, 2585 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2586 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 2587 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2588 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2589 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2590 clock-names = "core_clk", 2591 "bus_aggr_clk", 2592 "iface_clk", 2593 "core_clk_unipro", 2594 "ref_clk", 2595 "tx_lane0_sync_clk", 2596 "rx_lane0_sync_clk", 2597 "rx_lane1_sync_clk"; 2598 freq-table-hz = <100000000 403000000>, 2599 <0 0>, 2600 <0 0>, 2601 <100000000 403000000>, 2602 <100000000 403000000>, 2603 <0 0>, 2604 <0 0>, 2605 <0 0>; 2606 2607 resets = <&gcc GCC_UFS_PHY_BCR>; 2608 reset-names = "rst"; 2609 2610 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2611 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2612 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2613 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 2614 interconnect-names = "ufs-ddr", 2615 "cpu-ufs"; 2616 2617 power-domains = <&gcc UFS_PHY_GDSC>; 2618 required-opps = <&rpmhpd_opp_nom>; 2619 2620 iommus = <&apps_smmu 0x60 0>; 2621 2622 lanes-per-direction = <2>; 2623 qcom,ice = <&ice>; 2624 2625 phys = <&ufs_mem_phy>; 2626 phy-names = "ufsphy"; 2627 2628 #reset-cells = <1>; 2629 2630 status = "disabled"; 2631 }; 2632 2633 ice: crypto@1d88000 { 2634 compatible = "qcom,sm8650-inline-crypto-engine", 2635 "qcom,inline-crypto-engine"; 2636 reg = <0 0x01d88000 0 0x18000>; 2637 2638 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2639 }; 2640 2641 tcsr_mutex: hwlock@1f40000 { 2642 compatible = "qcom,tcsr-mutex"; 2643 reg = <0 0x01f40000 0 0x20000>; 2644 2645 #hwlock-cells = <1>; 2646 }; 2647 2648 tcsr: clock-controller@1fc0000 { 2649 compatible = "qcom,sm8650-tcsr", "syscon"; 2650 reg = <0 0x01fc0000 0 0xa0000>; 2651 2652 clocks = <&rpmhcc RPMH_CXO_CLK>; 2653 2654 #clock-cells = <1>; 2655 #reset-cells = <1>; 2656 }; 2657 2658 gpu: gpu@3d00000 { 2659 compatible = "qcom,adreno-43051401", "qcom,adreno"; 2660 reg = <0x0 0x03d00000 0x0 0x40000>, 2661 <0x0 0x03d9e000 0x0 0x2000>, 2662 <0x0 0x03d61000 0x0 0x800>; 2663 reg-names = "kgsl_3d0_reg_memory", 2664 "cx_mem", 2665 "cx_dbgc"; 2666 2667 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2668 2669 iommus = <&adreno_smmu 0 0x0>, 2670 <&adreno_smmu 1 0x0>; 2671 2672 operating-points-v2 = <&gpu_opp_table>; 2673 2674 qcom,gmu = <&gmu>; 2675 #cooling-cells = <2>; 2676 2677 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 2678 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2679 interconnect-names = "gfx-mem"; 2680 2681 status = "disabled"; 2682 2683 zap-shader { 2684 memory-region = <&gpu_micro_code_mem>; 2685 }; 2686 2687 /* Speedbin needs more work on A740+, keep only lower freqs */ 2688 gpu_opp_table: opp-table { 2689 compatible = "operating-points-v2"; 2690 2691 opp-231000000 { 2692 opp-hz = /bits/ 64 <231000000>; 2693 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 2694 opp-peak-kBps = <2136718>; 2695 }; 2696 2697 opp-310000000 { 2698 opp-hz = /bits/ 64 <310000000>; 2699 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2700 opp-peak-kBps = <2136718>; 2701 }; 2702 2703 opp-366000000 { 2704 opp-hz = /bits/ 64 <366000000>; 2705 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 2706 opp-peak-kBps = <6074218>; 2707 }; 2708 2709 opp-422000000 { 2710 opp-hz = /bits/ 64 <422000000>; 2711 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2712 opp-peak-kBps = <8171875>; 2713 }; 2714 2715 opp-500000000 { 2716 opp-hz = /bits/ 64 <500000000>; 2717 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 2718 opp-peak-kBps = <8171875>; 2719 }; 2720 2721 opp-578000000 { 2722 opp-hz = /bits/ 64 <578000000>; 2723 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2724 opp-peak-kBps = <8171875>; 2725 }; 2726 2727 opp-629000000 { 2728 opp-hz = /bits/ 64 <629000000>; 2729 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2730 opp-peak-kBps = <10687500>; 2731 }; 2732 2733 opp-680000000 { 2734 opp-hz = /bits/ 64 <680000000>; 2735 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2736 opp-peak-kBps = <12449218>; 2737 }; 2738 2739 opp-720000000 { 2740 opp-hz = /bits/ 64 <720000000>; 2741 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2742 opp-peak-kBps = <12449218>; 2743 }; 2744 2745 opp-770000000 { 2746 opp-hz = /bits/ 64 <770000000>; 2747 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2748 opp-peak-kBps = <12449218>; 2749 }; 2750 2751 opp-834000000 { 2752 opp-hz = /bits/ 64 <834000000>; 2753 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2754 opp-peak-kBps = <14398437>; 2755 }; 2756 }; 2757 }; 2758 2759 gmu: gmu@3d6a000 { 2760 compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu"; 2761 reg = <0x0 0x03d6a000 0x0 0x35000>, 2762 <0x0 0x03d50000 0x0 0x10000>, 2763 <0x0 0x0b280000 0x0 0x10000>; 2764 reg-names = "gmu", "rscc", "gmu_pdc"; 2765 2766 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2767 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2768 interrupt-names = "hfi", "gmu"; 2769 2770 clocks = <&gpucc GPU_CC_AHB_CLK>, 2771 <&gpucc GPU_CC_CX_GMU_CLK>, 2772 <&gpucc GPU_CC_CXO_CLK>, 2773 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2774 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2775 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2776 <&gpucc GPU_CC_DEMET_CLK>; 2777 clock-names = "ahb", 2778 "gmu", 2779 "cxo", 2780 "axi", 2781 "memnoc", 2782 "hub", 2783 "demet"; 2784 2785 power-domains = <&gpucc GPU_CX_GDSC>, 2786 <&gpucc GPU_GX_GDSC>; 2787 power-domain-names = "cx", 2788 "gx"; 2789 2790 iommus = <&adreno_smmu 5 0x0>; 2791 2792 qcom,qmp = <&aoss_qmp>; 2793 2794 operating-points-v2 = <&gmu_opp_table>; 2795 2796 gmu_opp_table: opp-table { 2797 compatible = "operating-points-v2"; 2798 2799 opp-260000000 { 2800 opp-hz = /bits/ 64 <260000000>; 2801 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2802 }; 2803 2804 opp-625000000 { 2805 opp-hz = /bits/ 64 <625000000>; 2806 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2807 }; 2808 }; 2809 }; 2810 2811 gpucc: clock-controller@3d90000 { 2812 compatible = "qcom,sm8650-gpucc"; 2813 reg = <0 0x03d90000 0 0xa000>; 2814 2815 clocks = <&bi_tcxo_div2>, 2816 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2817 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2818 2819 #clock-cells = <1>; 2820 #reset-cells = <1>; 2821 #power-domain-cells = <1>; 2822 }; 2823 2824 adreno_smmu: iommu@3da0000 { 2825 compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu", 2826 "qcom,smmu-500", "arm,mmu-500"; 2827 reg = <0x0 0x03da0000 0x0 0x40000>; 2828 #iommu-cells = <2>; 2829 #global-interrupts = <1>; 2830 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2831 <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>, 2832 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2833 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2834 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2835 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2836 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2837 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2838 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2839 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2840 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2841 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2842 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2843 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 2844 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 2845 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 2846 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2847 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 2848 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>, 2849 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, 2850 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>, 2851 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 2852 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 2853 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, 2854 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 2855 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 2856 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2857 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2858 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2859 <&gpucc GPU_CC_AHB_CLK>; 2860 clock-names = "hlos", 2861 "bus", 2862 "iface", 2863 "ahb"; 2864 power-domains = <&gpucc GPU_CX_GDSC>; 2865 dma-coherent; 2866 }; 2867 2868 ipa: ipa@3f40000 { 2869 compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa"; 2870 2871 iommus = <&apps_smmu 0x4a0 0x0>, 2872 <&apps_smmu 0x4a2 0x0>; 2873 reg = <0 0x3f40000 0 0x10000>, 2874 <0 0x3f50000 0 0x5000>, 2875 <0 0x3e04000 0 0xfc000>; 2876 reg-names = "ipa-reg", 2877 "ipa-shared", 2878 "gsi"; 2879 2880 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2881 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2882 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2883 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2884 interrupt-names = "ipa", 2885 "gsi", 2886 "ipa-clock-query", 2887 "ipa-setup-ready"; 2888 2889 clocks = <&rpmhcc RPMH_IPA_CLK>; 2890 clock-names = "core"; 2891 2892 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2893 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2894 interconnect-names = "memory", 2895 "config"; 2896 2897 qcom,qmp = <&aoss_qmp>; 2898 2899 qcom,smem-states = <&ipa_smp2p_out 0>, 2900 <&ipa_smp2p_out 1>; 2901 qcom,smem-state-names = "ipa-clock-enabled-valid", 2902 "ipa-clock-enabled"; 2903 2904 status = "disabled"; 2905 }; 2906 2907 remoteproc_mpss: remoteproc@4080000 { 2908 compatible = "qcom,sm8650-mpss-pas"; 2909 reg = <0x0 0x04080000 0x0 0x10000>; 2910 2911 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2912 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2913 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2914 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2915 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2916 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2917 interrupt-names = "wdog", 2918 "fatal", 2919 "ready", 2920 "handover", 2921 "stop-ack", 2922 "shutdown-ack"; 2923 2924 clocks = <&rpmhcc RPMH_CXO_CLK>; 2925 clock-names = "xo"; 2926 2927 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 2928 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2929 2930 power-domains = <&rpmhpd RPMHPD_CX>, 2931 <&rpmhpd RPMHPD_MSS>; 2932 power-domain-names = "cx", 2933 "mss"; 2934 2935 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, 2936 <&mpss_dsm_mem>, <&mpss_dsm_mem_2>, 2937 <&qlink_logging_mem>; 2938 2939 qcom,qmp = <&aoss_qmp>; 2940 2941 qcom,smem-states = <&smp2p_modem_out 0>; 2942 qcom,smem-state-names = "stop"; 2943 2944 status = "disabled"; 2945 2946 glink-edge { 2947 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2948 IPCC_MPROC_SIGNAL_GLINK_QMP 2949 IRQ_TYPE_EDGE_RISING>; 2950 2951 mboxes = <&ipcc IPCC_CLIENT_MPSS 2952 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2953 2954 qcom,remote-pid = <1>; 2955 2956 label = "mpss"; 2957 }; 2958 }; 2959 2960 remoteproc_adsp: remoteproc@6800000 { 2961 compatible = "qcom,sm8650-adsp-pas"; 2962 reg = <0x0 0x06800000 0x0 0x10000>; 2963 2964 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2965 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2966 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2967 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2968 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2969 interrupt-names = "wdog", 2970 "fatal", 2971 "ready", 2972 "handover", 2973 "stop-ack"; 2974 2975 clocks = <&rpmhcc RPMH_CXO_CLK>; 2976 clock-names = "xo"; 2977 2978 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 2979 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2980 2981 power-domains = <&rpmhpd RPMHPD_LCX>, 2982 <&rpmhpd RPMHPD_LMX>; 2983 power-domain-names = "lcx", 2984 "lmx"; 2985 2986 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 2987 2988 qcom,qmp = <&aoss_qmp>; 2989 2990 qcom,smem-states = <&smp2p_adsp_out 0>; 2991 qcom,smem-state-names = "stop"; 2992 2993 status = "disabled"; 2994 2995 remoteproc_adsp_glink: glink-edge { 2996 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2997 IPCC_MPROC_SIGNAL_GLINK_QMP 2998 IRQ_TYPE_EDGE_RISING>; 2999 3000 mboxes = <&ipcc IPCC_CLIENT_LPASS 3001 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3002 3003 qcom,remote-pid = <2>; 3004 3005 label = "lpass"; 3006 3007 fastrpc { 3008 compatible = "qcom,fastrpc"; 3009 3010 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3011 3012 label = "adsp"; 3013 3014 qcom,non-secure-domain; 3015 3016 #address-cells = <1>; 3017 #size-cells = <0>; 3018 3019 compute-cb@3 { 3020 compatible = "qcom,fastrpc-compute-cb"; 3021 reg = <3>; 3022 3023 iommus = <&apps_smmu 0x1003 0x80>, 3024 <&apps_smmu 0x1043 0x20>; 3025 dma-coherent; 3026 }; 3027 3028 compute-cb@4 { 3029 compatible = "qcom,fastrpc-compute-cb"; 3030 reg = <4>; 3031 3032 iommus = <&apps_smmu 0x1004 0x80>, 3033 <&apps_smmu 0x1044 0x20>; 3034 dma-coherent; 3035 }; 3036 3037 compute-cb@5 { 3038 compatible = "qcom,fastrpc-compute-cb"; 3039 reg = <5>; 3040 3041 iommus = <&apps_smmu 0x1005 0x80>, 3042 <&apps_smmu 0x1045 0x20>; 3043 dma-coherent; 3044 }; 3045 3046 compute-cb@6 { 3047 compatible = "qcom,fastrpc-compute-cb"; 3048 reg = <6>; 3049 3050 iommus = <&apps_smmu 0x1006 0x80>, 3051 <&apps_smmu 0x1046 0x20>; 3052 dma-coherent; 3053 }; 3054 3055 compute-cb@7 { 3056 compatible = "qcom,fastrpc-compute-cb"; 3057 reg = <7>; 3058 3059 iommus = <&apps_smmu 0x1007 0x40>, 3060 <&apps_smmu 0x1067 0x0>, 3061 <&apps_smmu 0x1087 0x0>; 3062 dma-coherent; 3063 }; 3064 }; 3065 3066 gpr { 3067 compatible = "qcom,gpr"; 3068 qcom,glink-channels = "adsp_apps"; 3069 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 3070 qcom,intents = <512 20>; 3071 #address-cells = <1>; 3072 #size-cells = <0>; 3073 3074 q6apm: service@1 { 3075 compatible = "qcom,q6apm"; 3076 reg = <GPR_APM_MODULE_IID>; 3077 #sound-dai-cells = <0>; 3078 qcom,protection-domain = "avs/audio", 3079 "msm/adsp/audio_pd"; 3080 3081 q6apmbedai: bedais { 3082 compatible = "qcom,q6apm-lpass-dais"; 3083 #sound-dai-cells = <1>; 3084 }; 3085 3086 q6apmdai: dais { 3087 compatible = "qcom,q6apm-dais"; 3088 iommus = <&apps_smmu 0x1001 0x80>, 3089 <&apps_smmu 0x1061 0x0>; 3090 }; 3091 }; 3092 3093 q6prm: service@2 { 3094 compatible = "qcom,q6prm"; 3095 reg = <GPR_PRM_MODULE_IID>; 3096 qcom,protection-domain = "avs/audio", 3097 "msm/adsp/audio_pd"; 3098 3099 q6prmcc: clock-controller { 3100 compatible = "qcom,q6prm-lpass-clocks"; 3101 #clock-cells = <2>; 3102 }; 3103 }; 3104 }; 3105 }; 3106 }; 3107 3108 lpass_wsa2macro: codec@6aa0000 { 3109 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 3110 reg = <0 0x06aa0000 0 0x1000>; 3111 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3112 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3113 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3114 <&lpass_vamacro>; 3115 clock-names = "mclk", 3116 "macro", 3117 "dcodec", 3118 "fsgen"; 3119 3120 #clock-cells = <0>; 3121 clock-output-names = "wsa2-mclk"; 3122 #sound-dai-cells = <1>; 3123 }; 3124 3125 swr3: soundwire@6ab0000 { 3126 compatible = "qcom,soundwire-v2.0.0"; 3127 reg = <0 0x06ab0000 0 0x10000>; 3128 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 3129 clocks = <&lpass_wsa2macro>; 3130 clock-names = "iface"; 3131 label = "WSA2"; 3132 3133 pinctrl-0 = <&wsa2_swr_active>; 3134 pinctrl-names = "default"; 3135 3136 qcom,din-ports = <4>; 3137 qcom,dout-ports = <9>; 3138 3139 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 3140 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 3141 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3142 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3143 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3144 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 3145 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 3146 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3147 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3148 3149 #address-cells = <2>; 3150 #size-cells = <0>; 3151 #sound-dai-cells = <1>; 3152 status = "disabled"; 3153 }; 3154 3155 lpass_rxmacro: codec@6ac0000 { 3156 compatible = "qcom,sm8650-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 3157 reg = <0 0x06ac0000 0 0x1000>; 3158 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3159 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3160 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3161 <&lpass_vamacro>; 3162 clock-names = "mclk", 3163 "macro", 3164 "dcodec", 3165 "fsgen"; 3166 3167 #clock-cells = <0>; 3168 clock-output-names = "mclk"; 3169 #sound-dai-cells = <1>; 3170 }; 3171 3172 swr1: soundwire@6ad0000 { 3173 compatible = "qcom,soundwire-v2.0.0"; 3174 reg = <0 0x06ad0000 0 0x10000>; 3175 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 3176 clocks = <&lpass_rxmacro>; 3177 clock-names = "iface"; 3178 label = "RX"; 3179 3180 pinctrl-0 = <&rx_swr_active>; 3181 pinctrl-names = "default"; 3182 3183 qcom,din-ports = <0>; 3184 qcom,dout-ports = <11>; 3185 3186 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff>; 3187 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff>; 3188 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>; 3189 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff>; 3190 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff>; 3191 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff>; 3192 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff>; 3193 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff>; 3194 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>; 3195 3196 #address-cells = <2>; 3197 #size-cells = <0>; 3198 #sound-dai-cells = <1>; 3199 status = "disabled"; 3200 }; 3201 3202 lpass_txmacro: codec@6ae0000 { 3203 compatible = "qcom,sm8650-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 3204 reg = <0 0x06ae0000 0 0x1000>; 3205 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3206 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3207 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3208 <&lpass_vamacro>; 3209 clock-names = "mclk", 3210 "macro", 3211 "dcodec", 3212 "fsgen"; 3213 3214 #clock-cells = <0>; 3215 clock-output-names = "mclk"; 3216 #sound-dai-cells = <1>; 3217 }; 3218 3219 lpass_wsamacro: codec@6b00000 { 3220 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 3221 reg = <0 0x06b00000 0 0x1000>; 3222 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3223 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3224 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3225 <&lpass_vamacro>; 3226 clock-names = "mclk", 3227 "macro", 3228 "dcodec", 3229 "fsgen"; 3230 3231 #clock-cells = <0>; 3232 clock-output-names = "mclk"; 3233 #sound-dai-cells = <1>; 3234 }; 3235 3236 swr0: soundwire@6b10000 { 3237 compatible = "qcom,soundwire-v2.0.0"; 3238 reg = <0 0x06b10000 0 0x10000>; 3239 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 3240 clocks = <&lpass_wsamacro>; 3241 clock-names = "iface"; 3242 label = "WSA"; 3243 3244 pinctrl-0 = <&wsa_swr_active>; 3245 pinctrl-names = "default"; 3246 3247 qcom,din-ports = <4>; 3248 qcom,dout-ports = <9>; 3249 3250 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 3251 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 3252 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3253 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3254 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3255 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 3256 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 3257 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3258 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3259 3260 #address-cells = <2>; 3261 #size-cells = <0>; 3262 #sound-dai-cells = <1>; 3263 status = "disabled"; 3264 }; 3265 3266 swr2: soundwire@6d30000 { 3267 compatible = "qcom,soundwire-v2.0.0"; 3268 reg = <0 0x06d30000 0 0x10000>; 3269 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 3270 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 3271 interrupt-names = "core", "wakeup"; 3272 clocks = <&lpass_txmacro>; 3273 clock-names = "iface"; 3274 label = "TX"; 3275 3276 pinctrl-0 = <&tx_swr_active>; 3277 pinctrl-names = "default"; 3278 3279 qcom,din-ports = <4>; 3280 qcom,dout-ports = <0>; 3281 3282 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 3283 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 3284 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 3285 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 3286 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 3287 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 3288 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 3289 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 3290 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 3291 3292 #address-cells = <2>; 3293 #size-cells = <0>; 3294 #sound-dai-cells = <1>; 3295 status = "disabled"; 3296 }; 3297 3298 lpass_vamacro: codec@6d44000 { 3299 compatible = "qcom,sm8650-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 3300 reg = <0 0x06d44000 0 0x1000>; 3301 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3302 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3303 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3304 clock-names = "mclk", 3305 "macro", 3306 "dcodec"; 3307 3308 #clock-cells = <0>; 3309 clock-output-names = "fsgen"; 3310 #sound-dai-cells = <1>; 3311 }; 3312 3313 lpass_tlmm: pinctrl@6e80000 { 3314 compatible = "qcom,sm8650-lpass-lpi-pinctrl"; 3315 reg = <0 0x06e80000 0 0x20000>; 3316 3317 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3318 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3319 clock-names = "core", "audio"; 3320 3321 gpio-controller; 3322 #gpio-cells = <2>; 3323 gpio-ranges = <&lpass_tlmm 0 0 23>; 3324 3325 tx_swr_active: tx-swr-active-state { 3326 clk-pins { 3327 pins = "gpio0"; 3328 function = "swr_tx_clk"; 3329 drive-strength = <2>; 3330 slew-rate = <1>; 3331 bias-disable; 3332 }; 3333 3334 data-pins { 3335 pins = "gpio1", "gpio2", "gpio14"; 3336 function = "swr_tx_data"; 3337 drive-strength = <2>; 3338 slew-rate = <1>; 3339 bias-bus-hold; 3340 }; 3341 }; 3342 3343 rx_swr_active: rx-swr-active-state { 3344 clk-pins { 3345 pins = "gpio3"; 3346 function = "swr_rx_clk"; 3347 drive-strength = <2>; 3348 slew-rate = <1>; 3349 bias-disable; 3350 }; 3351 3352 data-pins { 3353 pins = "gpio4", "gpio5"; 3354 function = "swr_rx_data"; 3355 drive-strength = <2>; 3356 slew-rate = <1>; 3357 bias-bus-hold; 3358 }; 3359 }; 3360 3361 dmic01_default: dmic01-default-state { 3362 clk-pins { 3363 pins = "gpio6"; 3364 function = "dmic1_clk"; 3365 drive-strength = <8>; 3366 output-high; 3367 }; 3368 3369 data-pins { 3370 pins = "gpio7"; 3371 function = "dmic1_data"; 3372 drive-strength = <8>; 3373 input-enable; 3374 }; 3375 }; 3376 3377 dmic23_default: dmic23-default-state { 3378 clk-pins { 3379 pins = "gpio8"; 3380 function = "dmic2_clk"; 3381 drive-strength = <8>; 3382 output-high; 3383 }; 3384 3385 data-pins { 3386 pins = "gpio9"; 3387 function = "dmic2_data"; 3388 drive-strength = <8>; 3389 input-enable; 3390 }; 3391 }; 3392 3393 wsa_swr_active: wsa-swr-active-state { 3394 clk-pins { 3395 pins = "gpio10"; 3396 function = "wsa_swr_clk"; 3397 drive-strength = <2>; 3398 slew-rate = <1>; 3399 bias-disable; 3400 }; 3401 3402 data-pins { 3403 pins = "gpio11"; 3404 function = "wsa_swr_data"; 3405 drive-strength = <2>; 3406 slew-rate = <1>; 3407 bias-bus-hold; 3408 }; 3409 }; 3410 3411 wsa2_swr_active: wsa2-swr-active-state { 3412 clk-pins { 3413 pins = "gpio15"; 3414 function = "wsa2_swr_clk"; 3415 drive-strength = <2>; 3416 slew-rate = <1>; 3417 bias-disable; 3418 }; 3419 3420 data-pins { 3421 pins = "gpio16"; 3422 function = "wsa2_swr_data"; 3423 drive-strength = <2>; 3424 slew-rate = <1>; 3425 bias-bus-hold; 3426 }; 3427 }; 3428 }; 3429 3430 lpass_lpiaon_noc: interconnect@7400000 { 3431 compatible = "qcom,sm8650-lpass-lpiaon-noc"; 3432 reg = <0 0x07400000 0 0x19080>; 3433 3434 #interconnect-cells = <2>; 3435 3436 qcom,bcm-voters = <&apps_bcm_voter>; 3437 }; 3438 3439 lpass_lpicx_noc: interconnect@7430000 { 3440 compatible = "qcom,sm8650-lpass-lpicx-noc"; 3441 reg = <0 0x07430000 0 0x3a200>; 3442 3443 #interconnect-cells = <2>; 3444 3445 qcom,bcm-voters = <&apps_bcm_voter>; 3446 }; 3447 3448 lpass_ag_noc: interconnect@7e40000 { 3449 compatible = "qcom,sm8650-lpass-ag-noc"; 3450 reg = <0 0x07e40000 0 0xe080>; 3451 3452 #interconnect-cells = <2>; 3453 3454 qcom,bcm-voters = <&apps_bcm_voter>; 3455 }; 3456 3457 sdhc_2: mmc@8804000 { 3458 compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5"; 3459 reg = <0 0x08804000 0 0x1000>; 3460 3461 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3462 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3463 interrupt-names = "hc_irq", 3464 "pwr_irq"; 3465 3466 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3467 <&gcc GCC_SDCC2_APPS_CLK>, 3468 <&rpmhcc RPMH_CXO_CLK>; 3469 clock-names = "iface", 3470 "core", 3471 "xo"; 3472 3473 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 3474 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3475 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3476 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; 3477 interconnect-names = "sdhc-ddr", 3478 "cpu-sdhc"; 3479 3480 power-domains = <&rpmhpd RPMHPD_CX>; 3481 operating-points-v2 = <&sdhc2_opp_table>; 3482 3483 iommus = <&apps_smmu 0x540 0>; 3484 3485 bus-width = <4>; 3486 3487 /* Forbid SDR104/SDR50 - broken hw! */ 3488 sdhci-caps-mask = <0x3 0>; 3489 3490 qcom,dll-config = <0x0007642c>; 3491 qcom,ddr-config = <0x80040868>; 3492 3493 dma-coherent; 3494 3495 status = "disabled"; 3496 3497 sdhc2_opp_table: opp-table { 3498 compatible = "operating-points-v2"; 3499 3500 opp-19200000 { 3501 opp-hz = /bits/ 64 <19200000>; 3502 required-opps = <&rpmhpd_opp_min_svs>; 3503 }; 3504 3505 opp-50000000 { 3506 opp-hz = /bits/ 64 <50000000>; 3507 required-opps = <&rpmhpd_opp_low_svs>; 3508 }; 3509 3510 opp-100000000 { 3511 opp-hz = /bits/ 64 <100000000>; 3512 required-opps = <&rpmhpd_opp_svs>; 3513 }; 3514 3515 opp-202000000 { 3516 opp-hz = /bits/ 64 <202000000>; 3517 required-opps = <&rpmhpd_opp_svs_l1>; 3518 }; 3519 }; 3520 }; 3521 3522 videocc: clock-controller@aaf0000 { 3523 compatible = "qcom,sm8650-videocc"; 3524 reg = <0 0x0aaf0000 0 0x10000>; 3525 clocks = <&bi_tcxo_div2>, 3526 <&gcc GCC_VIDEO_AHB_CLK>; 3527 power-domains = <&rpmhpd RPMHPD_MMCX>; 3528 #clock-cells = <1>; 3529 #reset-cells = <1>; 3530 #power-domain-cells = <1>; 3531 }; 3532 3533 cci0: cci@ac15000 { 3534 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; 3535 reg = <0 0x0ac15000 0 0x1000>; 3536 interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>; 3537 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 3538 clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, 3539 <&camcc CAM_CC_CPAS_AHB_CLK>, 3540 <&camcc CAM_CC_CCI_0_CLK>; 3541 clock-names = "camnoc_axi", 3542 "cpas_ahb", 3543 "cci"; 3544 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 3545 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 3546 pinctrl-names = "default", "sleep"; 3547 status = "disabled"; 3548 #address-cells = <1>; 3549 #size-cells = <0>; 3550 3551 cci0_i2c0: i2c-bus@0 { 3552 reg = <0>; 3553 clock-frequency = <1000000>; 3554 #address-cells = <1>; 3555 #size-cells = <0>; 3556 }; 3557 3558 cci0_i2c1: i2c-bus@1 { 3559 reg = <1>; 3560 clock-frequency = <1000000>; 3561 #address-cells = <1>; 3562 #size-cells = <0>; 3563 }; 3564 }; 3565 3566 cci1: cci@ac16000 { 3567 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; 3568 reg = <0 0x0ac16000 0 0x1000>; 3569 interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>; 3570 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 3571 clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, 3572 <&camcc CAM_CC_CPAS_AHB_CLK>, 3573 <&camcc CAM_CC_CCI_1_CLK>; 3574 clock-names = "camnoc_axi", 3575 "cpas_ahb", 3576 "cci"; 3577 pinctrl-0 = <&cci1_0_default &cci1_1_default>; 3578 pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; 3579 pinctrl-names = "default", "sleep"; 3580 status = "disabled"; 3581 #address-cells = <1>; 3582 #size-cells = <0>; 3583 3584 cci1_i2c0: i2c-bus@0 { 3585 reg = <0>; 3586 clock-frequency = <1000000>; 3587 #address-cells = <1>; 3588 #size-cells = <0>; 3589 }; 3590 3591 cci1_i2c1: i2c-bus@1 { 3592 reg = <1>; 3593 clock-frequency = <1000000>; 3594 #address-cells = <1>; 3595 #size-cells = <0>; 3596 }; 3597 }; 3598 3599 cci2: cci@ac17000 { 3600 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; 3601 reg = <0 0x0ac17000 0 0x1000>; 3602 interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>; 3603 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 3604 clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, 3605 <&camcc CAM_CC_CPAS_AHB_CLK>, 3606 <&camcc CAM_CC_CCI_2_CLK>; 3607 clock-names = "camnoc_axi", 3608 "cpas_ahb", 3609 "cci"; 3610 pinctrl-0 = <&cci2_0_default &cci2_1_default>; 3611 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; 3612 pinctrl-names = "default", "sleep"; 3613 status = "disabled"; 3614 #address-cells = <1>; 3615 #size-cells = <0>; 3616 3617 cci2_i2c0: i2c-bus@0 { 3618 reg = <0>; 3619 clock-frequency = <1000000>; 3620 #address-cells = <1>; 3621 #size-cells = <0>; 3622 }; 3623 3624 cci2_i2c1: i2c-bus@1 { 3625 reg = <1>; 3626 clock-frequency = <1000000>; 3627 #address-cells = <1>; 3628 #size-cells = <0>; 3629 }; 3630 }; 3631 3632 camcc: clock-controller@ade0000 { 3633 compatible = "qcom,sm8650-camcc"; 3634 reg = <0 0x0ade0000 0 0x20000>; 3635 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3636 <&bi_tcxo_div2>, 3637 <&bi_tcxo_ao_div2>, 3638 <&sleep_clk>; 3639 power-domains = <&rpmhpd RPMHPD_MMCX>; 3640 #clock-cells = <1>; 3641 #reset-cells = <1>; 3642 #power-domain-cells = <1>; 3643 }; 3644 3645 mdss: display-subsystem@ae00000 { 3646 compatible = "qcom,sm8650-mdss"; 3647 reg = <0 0x0ae00000 0 0x1000>; 3648 reg-names = "mdss"; 3649 3650 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3651 3652 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3653 <&gcc GCC_DISP_HF_AXI_CLK>, 3654 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3655 3656 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 3657 3658 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 3659 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3660 interconnect-names = "mdp0-mem"; 3661 3662 power-domains = <&dispcc MDSS_GDSC>; 3663 3664 iommus = <&apps_smmu 0x1c00 0x2>; 3665 3666 interrupt-controller; 3667 #interrupt-cells = <1>; 3668 3669 #address-cells = <2>; 3670 #size-cells = <2>; 3671 ranges; 3672 3673 status = "disabled"; 3674 3675 mdss_mdp: display-controller@ae01000 { 3676 compatible = "qcom,sm8650-dpu"; 3677 reg = <0 0x0ae01000 0 0x8f000>, 3678 <0 0x0aeb0000 0 0x2008>; 3679 reg-names = "mdp", 3680 "vbif"; 3681 3682 interrupts-extended = <&mdss 0>; 3683 3684 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3685 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3686 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3687 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3688 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3689 clock-names = "nrt_bus", 3690 "iface", 3691 "lut", 3692 "core", 3693 "vsync"; 3694 3695 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3696 assigned-clock-rates = <19200000>; 3697 3698 operating-points-v2 = <&mdp_opp_table>; 3699 3700 power-domains = <&rpmhpd RPMHPD_MMCX>; 3701 3702 ports { 3703 #address-cells = <1>; 3704 #size-cells = <0>; 3705 3706 port@0 { 3707 reg = <0>; 3708 3709 dpu_intf1_out: endpoint { 3710 remote-endpoint = <&mdss_dsi0_in>; 3711 }; 3712 }; 3713 3714 port@1 { 3715 reg = <1>; 3716 3717 dpu_intf2_out: endpoint { 3718 remote-endpoint = <&mdss_dsi1_in>; 3719 }; 3720 }; 3721 3722 port@2 { 3723 reg = <2>; 3724 3725 dpu_intf0_out: endpoint { 3726 remote-endpoint = <&mdss_dp0_in>; 3727 }; 3728 }; 3729 }; 3730 3731 mdp_opp_table: opp-table { 3732 compatible = "operating-points-v2"; 3733 3734 opp-200000000 { 3735 opp-hz = /bits/ 64 <200000000>; 3736 required-opps = <&rpmhpd_opp_low_svs>; 3737 }; 3738 3739 opp-325000000 { 3740 opp-hz = /bits/ 64 <325000000>; 3741 required-opps = <&rpmhpd_opp_svs>; 3742 }; 3743 3744 opp-375000000 { 3745 opp-hz = /bits/ 64 <375000000>; 3746 required-opps = <&rpmhpd_opp_svs_l1>; 3747 }; 3748 3749 opp-514000000 { 3750 opp-hz = /bits/ 64 <514000000>; 3751 required-opps = <&rpmhpd_opp_nom>; 3752 }; 3753 }; 3754 }; 3755 3756 mdss_dsi0: dsi@ae94000 { 3757 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3758 reg = <0 0x0ae94000 0 0x400>; 3759 reg-names = "dsi_ctrl"; 3760 3761 interrupts-extended = <&mdss 4>; 3762 3763 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3764 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3765 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3766 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3767 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3768 <&gcc GCC_DISP_HF_AXI_CLK>; 3769 clock-names = "byte", 3770 "byte_intf", 3771 "pixel", 3772 "core", 3773 "iface", 3774 "bus"; 3775 3776 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3777 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3778 assigned-clock-parents = <&mdss_dsi0_phy 0>, 3779 <&mdss_dsi0_phy 1>; 3780 3781 operating-points-v2 = <&mdss_dsi_opp_table>; 3782 3783 power-domains = <&rpmhpd RPMHPD_MMCX>; 3784 3785 phys = <&mdss_dsi0_phy>; 3786 phy-names = "dsi"; 3787 3788 #address-cells = <1>; 3789 #size-cells = <0>; 3790 3791 status = "disabled"; 3792 3793 ports { 3794 #address-cells = <1>; 3795 #size-cells = <0>; 3796 3797 port@0 { 3798 reg = <0>; 3799 3800 mdss_dsi0_in: endpoint { 3801 remote-endpoint = <&dpu_intf1_out>; 3802 }; 3803 }; 3804 3805 port@1 { 3806 reg = <1>; 3807 3808 mdss_dsi0_out: endpoint { 3809 }; 3810 }; 3811 }; 3812 3813 mdss_dsi_opp_table: opp-table { 3814 compatible = "operating-points-v2"; 3815 3816 opp-187500000 { 3817 opp-hz = /bits/ 64 <187500000>; 3818 required-opps = <&rpmhpd_opp_low_svs>; 3819 }; 3820 3821 opp-300000000 { 3822 opp-hz = /bits/ 64 <300000000>; 3823 required-opps = <&rpmhpd_opp_svs>; 3824 }; 3825 3826 opp-358000000 { 3827 opp-hz = /bits/ 64 <358000000>; 3828 required-opps = <&rpmhpd_opp_svs_l1>; 3829 }; 3830 }; 3831 }; 3832 3833 mdss_dsi0_phy: phy@ae95000 { 3834 compatible = "qcom,sm8650-dsi-phy-4nm"; 3835 reg = <0 0x0ae95000 0 0x200>, 3836 <0 0x0ae95200 0 0x280>, 3837 <0 0x0ae95500 0 0x400>; 3838 reg-names = "dsi_phy", 3839 "dsi_phy_lane", 3840 "dsi_pll"; 3841 3842 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3843 <&rpmhcc RPMH_CXO_CLK>; 3844 clock-names = "iface", 3845 "ref"; 3846 3847 #clock-cells = <1>; 3848 #phy-cells = <0>; 3849 3850 status = "disabled"; 3851 }; 3852 3853 mdss_dsi1: dsi@ae96000 { 3854 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3855 reg = <0 0x0ae96000 0 0x400>; 3856 reg-names = "dsi_ctrl"; 3857 3858 interrupts-extended = <&mdss 5>; 3859 3860 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3861 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3862 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3863 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3864 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3865 <&gcc GCC_DISP_HF_AXI_CLK>; 3866 clock-names = "byte", 3867 "byte_intf", 3868 "pixel", 3869 "core", 3870 "iface", 3871 "bus"; 3872 3873 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3874 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3875 assigned-clock-parents = <&mdss_dsi1_phy 0>, 3876 <&mdss_dsi1_phy 1>; 3877 3878 operating-points-v2 = <&mdss_dsi_opp_table>; 3879 3880 power-domains = <&rpmhpd RPMHPD_MMCX>; 3881 3882 phys = <&mdss_dsi1_phy>; 3883 phy-names = "dsi"; 3884 3885 #address-cells = <1>; 3886 #size-cells = <0>; 3887 3888 status = "disabled"; 3889 3890 ports { 3891 #address-cells = <1>; 3892 #size-cells = <0>; 3893 3894 port@0 { 3895 reg = <0>; 3896 3897 mdss_dsi1_in: endpoint { 3898 remote-endpoint = <&dpu_intf2_out>; 3899 }; 3900 }; 3901 3902 port@1 { 3903 reg = <1>; 3904 3905 mdss_dsi1_out: endpoint { 3906 }; 3907 }; 3908 }; 3909 }; 3910 3911 mdss_dsi1_phy: phy@ae97000 { 3912 compatible = "qcom,sm8650-dsi-phy-4nm"; 3913 reg = <0 0x0ae97000 0 0x200>, 3914 <0 0x0ae97200 0 0x280>, 3915 <0 0x0ae97500 0 0x400>; 3916 reg-names = "dsi_phy", 3917 "dsi_phy_lane", 3918 "dsi_pll"; 3919 3920 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3921 <&rpmhcc RPMH_CXO_CLK>; 3922 clock-names = "iface", 3923 "ref"; 3924 3925 #clock-cells = <1>; 3926 #phy-cells = <0>; 3927 3928 status = "disabled"; 3929 }; 3930 3931 mdss_dp0: displayport-controller@af54000 { 3932 compatible = "qcom,sm8650-dp"; 3933 reg = <0 0xaf54000 0 0x104>, 3934 <0 0xaf54200 0 0xc0>, 3935 <0 0xaf55000 0 0x770>, 3936 <0 0xaf56000 0 0x9c>, 3937 <0 0xaf57000 0 0x9c>; 3938 3939 interrupts-extended = <&mdss 12>; 3940 3941 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3942 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 3943 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 3944 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3945 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3946 clock-names = "core_iface", 3947 "core_aux", 3948 "ctrl_link", 3949 "ctrl_link_iface", 3950 "stream_pixel"; 3951 3952 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3953 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3954 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3955 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3956 3957 operating-points-v2 = <&dp_opp_table>; 3958 3959 power-domains = <&rpmhpd RPMHPD_MMCX>; 3960 3961 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 3962 phy-names = "dp"; 3963 3964 #sound-dai-cells = <0>; 3965 3966 status = "disabled"; 3967 3968 dp_opp_table: opp-table { 3969 compatible = "operating-points-v2"; 3970 3971 opp-162000000 { 3972 opp-hz = /bits/ 64 <162000000>; 3973 required-opps = <&rpmhpd_opp_low_svs_d1>; 3974 }; 3975 3976 opp-270000000 { 3977 opp-hz = /bits/ 64 <270000000>; 3978 required-opps = <&rpmhpd_opp_low_svs>; 3979 }; 3980 3981 opp-540000000 { 3982 opp-hz = /bits/ 64 <540000000>; 3983 required-opps = <&rpmhpd_opp_svs_l1>; 3984 }; 3985 3986 opp-810000000 { 3987 opp-hz = /bits/ 64 <810000000>; 3988 required-opps = <&rpmhpd_opp_nom>; 3989 }; 3990 }; 3991 3992 ports { 3993 #address-cells = <1>; 3994 #size-cells = <0>; 3995 3996 port@0 { 3997 reg = <0>; 3998 3999 mdss_dp0_in: endpoint { 4000 remote-endpoint = <&dpu_intf0_out>; 4001 }; 4002 }; 4003 4004 port@1 { 4005 reg = <1>; 4006 4007 mdss_dp0_out: endpoint { 4008 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 4009 }; 4010 }; 4011 }; 4012 }; 4013 }; 4014 4015 dispcc: clock-controller@af00000 { 4016 compatible = "qcom,sm8650-dispcc"; 4017 reg = <0 0x0af00000 0 0x20000>; 4018 4019 clocks = <&bi_tcxo_div2>, 4020 <&bi_tcxo_ao_div2>, 4021 <&gcc GCC_DISP_AHB_CLK>, 4022 <&sleep_clk>, 4023 <&mdss_dsi0_phy 0>, 4024 <&mdss_dsi0_phy 1>, 4025 <&mdss_dsi1_phy 0>, 4026 <&mdss_dsi1_phy 1>, 4027 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4028 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4029 <0>, /* dp1 */ 4030 <0>, 4031 <0>, /* dp2 */ 4032 <0>, 4033 <0>, /* dp3 */ 4034 <0>; 4035 4036 power-domains = <&rpmhpd RPMHPD_MMCX>; 4037 required-opps = <&rpmhpd_opp_low_svs>; 4038 4039 #clock-cells = <1>; 4040 #reset-cells = <1>; 4041 #power-domain-cells = <1>; 4042 }; 4043 4044 usb_1_hsphy: phy@88e3000 { 4045 compatible = "qcom,sm8650-snps-eusb2-phy", 4046 "qcom,sm8550-snps-eusb2-phy"; 4047 reg = <0 0x088e3000 0 0x154>; 4048 4049 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 4050 clock-names = "ref"; 4051 4052 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 4053 4054 #phy-cells = <0>; 4055 4056 status = "disabled"; 4057 }; 4058 4059 usb_dp_qmpphy: phy@88e8000 { 4060 compatible = "qcom,sm8650-qmp-usb3-dp-phy"; 4061 reg = <0 0x088e8000 0 0x3000>; 4062 4063 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4064 <&rpmhcc RPMH_CXO_CLK>, 4065 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4066 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4067 clock-names = "aux", 4068 "ref", 4069 "com_aux", 4070 "usb3_pipe"; 4071 4072 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4073 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 4074 reset-names = "phy", 4075 "common"; 4076 4077 power-domains = <&gcc USB3_PHY_GDSC>; 4078 4079 #clock-cells = <1>; 4080 #phy-cells = <1>; 4081 4082 orientation-switch; 4083 4084 status = "disabled"; 4085 4086 ports { 4087 #address-cells = <1>; 4088 #size-cells = <0>; 4089 4090 port@0 { 4091 reg = <0>; 4092 4093 usb_dp_qmpphy_out: endpoint { 4094 }; 4095 }; 4096 4097 port@1 { 4098 reg = <1>; 4099 4100 usb_dp_qmpphy_usb_ss_in: endpoint { 4101 remote-endpoint = <&usb_1_dwc3_ss>; 4102 }; 4103 }; 4104 4105 port@2 { 4106 reg = <2>; 4107 4108 usb_dp_qmpphy_dp_in: endpoint { 4109 remote-endpoint = <&mdss_dp0_out>; 4110 }; 4111 }; 4112 }; 4113 }; 4114 4115 usb_1: usb@a6f8800 { 4116 compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; 4117 reg = <0 0x0a6f8800 0 0x400>; 4118 4119 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4120 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4121 <&pdc 14 IRQ_TYPE_EDGE_RISING>, 4122 <&pdc 15 IRQ_TYPE_EDGE_RISING>, 4123 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4124 interrupt-names = "pwr_event", 4125 "hs_phy_irq", 4126 "dp_hs_phy_irq", 4127 "dm_hs_phy_irq", 4128 "ss_phy_irq"; 4129 4130 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4131 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4132 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4133 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4134 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4135 <&tcsr TCSR_USB3_CLKREF_EN>; 4136 clock-names = "cfg_noc", 4137 "core", 4138 "iface", 4139 "sleep", 4140 "mock_utmi", 4141 "xo"; 4142 4143 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4144 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4145 assigned-clock-rates = <19200000>, <200000000>; 4146 4147 resets = <&gcc GCC_USB30_PRIM_BCR>; 4148 4149 power-domains = <&gcc USB30_PRIM_GDSC>; 4150 required-opps = <&rpmhpd_opp_nom>; 4151 4152 #address-cells = <2>; 4153 #size-cells = <2>; 4154 ranges; 4155 4156 status = "disabled"; 4157 4158 usb_1_dwc3: usb@a600000 { 4159 compatible = "snps,dwc3"; 4160 reg = <0 0x0a600000 0 0xcd00>; 4161 4162 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4163 4164 iommus = <&apps_smmu 0x40 0>; 4165 4166 phys = <&usb_1_hsphy>, 4167 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 4168 phy-names = "usb2-phy", 4169 "usb3-phy"; 4170 4171 snps,hird-threshold = /bits/ 8 <0x0>; 4172 snps,usb2-gadget-lpm-disable; 4173 snps,dis_u2_susphy_quirk; 4174 snps,dis_enblslpm_quirk; 4175 snps,dis-u1-entry-quirk; 4176 snps,dis-u2-entry-quirk; 4177 snps,is-utmi-l1-suspend; 4178 snps,usb3_lpm_capable; 4179 snps,usb2-lpm-disable; 4180 snps,has-lpm-erratum; 4181 tx-fifo-resize; 4182 4183 dma-coherent; 4184 4185 ports { 4186 #address-cells = <1>; 4187 #size-cells = <0>; 4188 4189 port@0 { 4190 reg = <0>; 4191 4192 usb_1_dwc3_hs: endpoint { 4193 }; 4194 }; 4195 4196 port@1 { 4197 reg = <1>; 4198 4199 usb_1_dwc3_ss: endpoint { 4200 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 4201 }; 4202 }; 4203 }; 4204 }; 4205 }; 4206 4207 pdc: interrupt-controller@b220000 { 4208 compatible = "qcom,sm8650-pdc", "qcom,pdc"; 4209 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 4210 4211 interrupt-parent = <&intc>; 4212 4213 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 4214 <125 63 1>, <126 716 12>, 4215 <138 251 5>, <143 244 4>; 4216 4217 #interrupt-cells = <2>; 4218 interrupt-controller; 4219 }; 4220 4221 tsens0: thermal-sensor@c228000 { 4222 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 4223 reg = <0 0x0c228000 0 0x1000>, /* TM */ 4224 <0 0x0c222000 0 0x1000>; /* SROT */ 4225 4226 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4227 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 4228 interrupt-names = "uplow", 4229 "critical"; 4230 4231 #qcom,sensors = <15>; 4232 4233 #thermal-sensor-cells = <1>; 4234 }; 4235 4236 tsens1: thermal-sensor@c229000 { 4237 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 4238 reg = <0 0x0c229000 0 0x1000>, /* TM */ 4239 <0 0x0c223000 0 0x1000>; /* SROT */ 4240 4241 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4242 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 4243 interrupt-names = "uplow", 4244 "critical"; 4245 4246 #qcom,sensors = <16>; 4247 4248 #thermal-sensor-cells = <1>; 4249 }; 4250 4251 tsens2: thermal-sensor@c22a000 { 4252 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 4253 reg = <0 0x0c22a000 0 0x1000>, /* TM */ 4254 <0 0x0c224000 0 0x1000>; /* SROT */ 4255 4256 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 4257 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 4258 interrupt-names = "uplow", 4259 "critical"; 4260 4261 #qcom,sensors = <13>; 4262 4263 #thermal-sensor-cells = <1>; 4264 }; 4265 4266 aoss_qmp: power-management@c300000 { 4267 compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp"; 4268 reg = <0 0x0c300000 0 0x400>; 4269 4270 interrupt-parent = <&ipcc>; 4271 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 4272 IRQ_TYPE_EDGE_RISING>; 4273 4274 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4275 4276 #clock-cells = <0>; 4277 }; 4278 4279 sram@c3f0000 { 4280 compatible = "qcom,rpmh-stats"; 4281 reg = <0 0x0c3f0000 0 0x400>; 4282 }; 4283 4284 spmi_bus: spmi@c400000 { 4285 compatible = "qcom,spmi-pmic-arb"; 4286 reg = <0 0x0c400000 0 0x3000>, 4287 <0 0x0c500000 0 0x400000>, 4288 <0 0x0c440000 0 0x80000>, 4289 <0 0x0c4c0000 0 0x20000>, 4290 <0 0x0c42d000 0 0x4000>; 4291 reg-names = "core", 4292 "chnls", 4293 "obsrvr", 4294 "intr", 4295 "cnfg"; 4296 4297 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4298 interrupt-names = "periph_irq"; 4299 4300 qcom,ee = <0>; 4301 qcom,channel = <0>; 4302 qcom,bus-id = <0>; 4303 4304 interrupt-controller; 4305 #interrupt-cells = <4>; 4306 4307 #address-cells = <2>; 4308 #size-cells = <0>; 4309 }; 4310 4311 tlmm: pinctrl@f100000 { 4312 compatible = "qcom,sm8650-tlmm"; 4313 reg = <0 0x0f100000 0 0x300000>; 4314 4315 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4316 4317 gpio-controller; 4318 #gpio-cells = <2>; 4319 4320 interrupt-controller; 4321 #interrupt-cells = <2>; 4322 4323 gpio-ranges = <&tlmm 0 0 211>; 4324 4325 wakeup-parent = <&pdc>; 4326 4327 cci0_0_default: cci0-0-default-state { 4328 sda-pins { 4329 pins = "gpio113"; 4330 function = "cci_i2c_sda"; 4331 drive-strength = <2>; 4332 bias-pull-up = <2200>; 4333 }; 4334 4335 scl-pins { 4336 pins = "gpio114"; 4337 function = "cci_i2c_scl"; 4338 drive-strength = <2>; 4339 bias-pull-up = <2200>; 4340 }; 4341 }; 4342 4343 cci0_0_sleep: cci0-0-sleep-state { 4344 sda-pins { 4345 pins = "gpio113"; 4346 function = "cci_i2c_sda"; 4347 drive-strength = <2>; 4348 bias-pull-down; 4349 }; 4350 4351 scl-pins { 4352 pins = "gpio114"; 4353 function = "cci_i2c_scl"; 4354 drive-strength = <2>; 4355 bias-pull-down; 4356 }; 4357 }; 4358 4359 cci0_1_default: cci0-1-default-state { 4360 sda-pins { 4361 pins = "gpio115"; 4362 function = "cci_i2c_sda"; 4363 drive-strength = <2>; 4364 bias-pull-up = <2200>; 4365 }; 4366 4367 scl-pins { 4368 pins = "gpio116"; 4369 function = "cci_i2c_scl"; 4370 drive-strength = <2>; 4371 bias-pull-up = <2200>; 4372 }; 4373 }; 4374 4375 cci0_1_sleep: cci0-1-sleep-state { 4376 sda-pins { 4377 pins = "gpio115"; 4378 function = "cci_i2c_sda"; 4379 drive-strength = <2>; 4380 bias-pull-down; 4381 }; 4382 4383 scl-pins { 4384 pins = "gpio116"; 4385 function = "cci_i2c_scl"; 4386 drive-strength = <2>; 4387 bias-pull-down; 4388 }; 4389 }; 4390 4391 cci1_0_default: cci1-0-default-state { 4392 sda-pins { 4393 pins = "gpio117"; 4394 function = "cci_i2c_sda"; 4395 drive-strength = <2>; 4396 bias-pull-up = <2200>; 4397 }; 4398 4399 scl-pins { 4400 pins = "gpio118"; 4401 function = "cci_i2c_scl"; 4402 drive-strength = <2>; 4403 bias-pull-up = <2200>; 4404 }; 4405 }; 4406 4407 cci1_0_sleep: cci1-0-sleep-state { 4408 sda-pins { 4409 pins = "gpio117"; 4410 function = "cci_i2c_sda"; 4411 drive-strength = <2>; 4412 bias-pull-down; 4413 }; 4414 4415 scl-pins { 4416 pins = "gpio118"; 4417 function = "cci_i2c_scl"; 4418 drive-strength = <2>; 4419 bias-pull-down; 4420 }; 4421 }; 4422 4423 cci1_1_default: cci1-1-default-state { 4424 sda-pins { 4425 pins = "gpio12"; 4426 function = "cci_i2c_sda"; 4427 drive-strength = <2>; 4428 bias-pull-up = <2200>; 4429 }; 4430 4431 scl-pins { 4432 pins = "gpio13"; 4433 function = "cci_i2c_scl"; 4434 drive-strength = <2>; 4435 bias-pull-up = <2200>; 4436 }; 4437 }; 4438 4439 cci1_1_sleep: cci1-1-sleep-state { 4440 sda-pins { 4441 pins = "gpio12"; 4442 function = "cci_i2c_sda"; 4443 drive-strength = <2>; 4444 bias-pull-down; 4445 }; 4446 4447 scl-pins { 4448 pins = "gpio13"; 4449 function = "cci_i2c_scl"; 4450 drive-strength = <2>; 4451 bias-pull-down; 4452 }; 4453 }; 4454 4455 cci2_0_default: cci2-0-default-state { 4456 sda-pins { 4457 pins = "gpio112"; 4458 function = "cci_i2c_sda"; 4459 drive-strength = <2>; 4460 bias-pull-up = <2200>; 4461 }; 4462 4463 scl-pins { 4464 pins = "gpio153"; 4465 function = "cci_i2c_scl"; 4466 drive-strength = <2>; 4467 bias-pull-up = <2200>; 4468 }; 4469 }; 4470 4471 cci2_0_sleep: cci2-0-sleep-state { 4472 sda-pins { 4473 pins = "gpio112"; 4474 function = "cci_i2c_sda"; 4475 drive-strength = <2>; 4476 bias-pull-down; 4477 }; 4478 4479 scl-pins { 4480 pins = "gpio153"; 4481 function = "cci_i2c_scl"; 4482 drive-strength = <2>; 4483 bias-pull-down; 4484 }; 4485 }; 4486 4487 cci2_1_default: cci2-1-default-state { 4488 sda-pins { 4489 pins = "gpio119"; 4490 function = "cci_i2c_sda"; 4491 drive-strength = <2>; 4492 bias-pull-up = <2200>; 4493 }; 4494 4495 scl-pins { 4496 pins = "gpio120"; 4497 function = "cci_i2c_scl"; 4498 drive-strength = <2>; 4499 bias-pull-up = <2200>; 4500 }; 4501 }; 4502 4503 cci2_1_sleep: cci2-1-sleep-state { 4504 sda-pins { 4505 pins = "gpio119"; 4506 function = "cci_i2c_sda"; 4507 drive-strength = <2>; 4508 bias-pull-down; 4509 }; 4510 4511 scl-pins { 4512 pins = "gpio120"; 4513 function = "cci_i2c_scl"; 4514 drive-strength = <2>; 4515 bias-pull-down; 4516 }; 4517 }; 4518 4519 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 4520 /* SDA, SCL */ 4521 pins = "gpio64", "gpio65"; 4522 function = "i2chub0_se0"; 4523 drive-strength = <2>; 4524 bias-pull-up; 4525 }; 4526 4527 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 4528 /* SDA, SCL */ 4529 pins = "gpio66", "gpio67"; 4530 function = "i2chub0_se1"; 4531 drive-strength = <2>; 4532 bias-pull-up; 4533 }; 4534 4535 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 4536 /* SDA, SCL */ 4537 pins = "gpio68", "gpio69"; 4538 function = "i2chub0_se2"; 4539 drive-strength = <2>; 4540 bias-pull-up; 4541 }; 4542 4543 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 4544 /* SDA, SCL */ 4545 pins = "gpio70", "gpio71"; 4546 function = "i2chub0_se3"; 4547 drive-strength = <2>; 4548 bias-pull-up; 4549 }; 4550 4551 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 4552 /* SDA, SCL */ 4553 pins = "gpio72", "gpio73"; 4554 function = "i2chub0_se4"; 4555 drive-strength = <2>; 4556 bias-pull-up; 4557 }; 4558 4559 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 4560 /* SDA, SCL */ 4561 pins = "gpio74", "gpio75"; 4562 function = "i2chub0_se5"; 4563 drive-strength = <2>; 4564 bias-pull-up; 4565 }; 4566 4567 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 4568 /* SDA, SCL */ 4569 pins = "gpio76", "gpio77"; 4570 function = "i2chub0_se6"; 4571 drive-strength = <2>; 4572 bias-pull-up; 4573 }; 4574 4575 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 4576 /* SDA, SCL */ 4577 pins = "gpio78", "gpio79"; 4578 function = "i2chub0_se7"; 4579 drive-strength = <2>; 4580 bias-pull-up; 4581 }; 4582 4583 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 4584 /* SDA, SCL */ 4585 pins = "gpio206", "gpio207"; 4586 function = "i2chub0_se8"; 4587 drive-strength = <2>; 4588 bias-pull-up; 4589 }; 4590 4591 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 4592 /* SDA, SCL */ 4593 pins = "gpio80", "gpio81"; 4594 function = "i2chub0_se9"; 4595 drive-strength = <2>; 4596 bias-pull-up; 4597 }; 4598 4599 pcie0_default_state: pcie0-default-state { 4600 perst-pins { 4601 pins = "gpio94"; 4602 function = "gpio"; 4603 drive-strength = <2>; 4604 bias-pull-down; 4605 }; 4606 4607 clkreq-pins { 4608 pins = "gpio95"; 4609 function = "pcie0_clk_req_n"; 4610 drive-strength = <2>; 4611 bias-pull-up; 4612 }; 4613 4614 wake-pins { 4615 pins = "gpio96"; 4616 function = "gpio"; 4617 drive-strength = <2>; 4618 bias-pull-up; 4619 }; 4620 }; 4621 4622 pcie1_default_state: pcie1-default-state { 4623 perst-pins { 4624 pins = "gpio97"; 4625 function = "gpio"; 4626 drive-strength = <2>; 4627 bias-pull-down; 4628 }; 4629 4630 clkreq-pins { 4631 pins = "gpio98"; 4632 function = "pcie1_clk_req_n"; 4633 drive-strength = <2>; 4634 bias-pull-up; 4635 }; 4636 4637 wake-pins { 4638 pins = "gpio99"; 4639 function = "gpio"; 4640 drive-strength = <2>; 4641 bias-pull-up; 4642 }; 4643 }; 4644 4645 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4646 /* SDA, SCL */ 4647 pins = "gpio32", "gpio33"; 4648 function = "qup1_se0"; 4649 drive-strength = <2>; 4650 bias-pull-up; 4651 }; 4652 4653 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4654 /* SDA, SCL */ 4655 pins = "gpio36", "gpio37"; 4656 function = "qup1_se1"; 4657 drive-strength = <2>; 4658 bias-pull-up; 4659 }; 4660 4661 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4662 /* SDA, SCL */ 4663 pins = "gpio40", "gpio41"; 4664 function = "qup1_se2"; 4665 drive-strength = <2>; 4666 bias-pull-up; 4667 }; 4668 4669 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4670 /* SDA, SCL */ 4671 pins = "gpio44", "gpio45"; 4672 function = "qup1_se3"; 4673 drive-strength = <2>; 4674 bias-pull-up; 4675 }; 4676 4677 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4678 /* SDA, SCL */ 4679 pins = "gpio48", "gpio49"; 4680 function = "qup1_se4"; 4681 drive-strength = <2>; 4682 bias-pull-up; 4683 }; 4684 4685 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4686 /* SDA, SCL */ 4687 pins = "gpio52", "gpio53"; 4688 function = "qup1_se5"; 4689 drive-strength = <2>; 4690 bias-pull-up; 4691 }; 4692 4693 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4694 /* SDA, SCL */ 4695 pins = "gpio56", "gpio57"; 4696 function = "qup1_se6"; 4697 drive-strength = <2>; 4698 bias-pull-up; 4699 }; 4700 4701 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4702 /* SDA, SCL */ 4703 pins = "gpio60", "gpio61"; 4704 function = "qup1_se7"; 4705 drive-strength = <2>; 4706 bias-pull-up; 4707 }; 4708 4709 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4710 /* SDA, SCL */ 4711 pins = "gpio0", "gpio1"; 4712 function = "qup2_se0"; 4713 drive-strength = <2>; 4714 bias-pull-up; 4715 }; 4716 4717 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4718 /* SDA, SCL */ 4719 pins = "gpio4", "gpio5"; 4720 function = "qup2_se1"; 4721 drive-strength = <2>; 4722 bias-pull-up; 4723 }; 4724 4725 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4726 /* SDA, SCL */ 4727 pins = "gpio8", "gpio9"; 4728 function = "qup2_se2"; 4729 drive-strength = <2>; 4730 bias-pull-up; 4731 }; 4732 4733 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4734 /* SDA, SCL */ 4735 pins = "gpio12", "gpio13"; 4736 function = "qup2_se3"; 4737 drive-strength = <2>; 4738 bias-pull-up; 4739 }; 4740 4741 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4742 /* SDA, SCL */ 4743 pins = "gpio16", "gpio17"; 4744 function = "qup2_se4"; 4745 drive-strength = <2>; 4746 bias-pull-up; 4747 }; 4748 4749 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4750 /* SDA, SCL */ 4751 pins = "gpio20", "gpio21"; 4752 function = "qup2_se5"; 4753 drive-strength = <2>; 4754 bias-pull-up; 4755 }; 4756 4757 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4758 /* SDA, SCL */ 4759 pins = "gpio24", "gpio25"; 4760 function = "qup2_se6"; 4761 drive-strength = <2>; 4762 bias-pull-up; 4763 }; 4764 4765 qup_spi0_cs: qup-spi0-cs-state { 4766 pins = "gpio35"; 4767 function = "qup1_se0"; 4768 drive-strength = <6>; 4769 bias-disable; 4770 }; 4771 4772 qup_spi0_data_clk: qup-spi0-data-clk-state { 4773 /* MISO, MOSI, CLK */ 4774 pins = "gpio32", "gpio33", "gpio34"; 4775 function = "qup1_se0"; 4776 drive-strength = <6>; 4777 bias-disable; 4778 }; 4779 4780 qup_spi1_cs: qup-spi1-cs-state { 4781 pins = "gpio39"; 4782 function = "qup1_se1"; 4783 drive-strength = <6>; 4784 bias-disable; 4785 }; 4786 4787 qup_spi1_data_clk: qup-spi1-data-clk-state { 4788 /* MISO, MOSI, CLK */ 4789 pins = "gpio36", "gpio37", "gpio38"; 4790 function = "qup1_se1"; 4791 drive-strength = <6>; 4792 bias-disable; 4793 }; 4794 4795 qup_spi2_cs: qup-spi2-cs-state { 4796 pins = "gpio43"; 4797 function = "qup1_se2"; 4798 drive-strength = <6>; 4799 bias-disable; 4800 }; 4801 4802 qup_spi2_data_clk: qup-spi2-data-clk-state { 4803 /* MISO, MOSI, CLK */ 4804 pins = "gpio40", "gpio41", "gpio42"; 4805 function = "qup1_se2"; 4806 drive-strength = <6>; 4807 bias-disable; 4808 }; 4809 4810 qup_spi3_cs: qup-spi3-cs-state { 4811 pins = "gpio47"; 4812 function = "qup1_se3"; 4813 drive-strength = <6>; 4814 bias-disable; 4815 }; 4816 4817 qup_spi3_data_clk: qup-spi3-data-clk-state { 4818 /* MISO, MOSI, CLK */ 4819 pins = "gpio44", "gpio45", "gpio46"; 4820 function = "qup1_se3"; 4821 drive-strength = <6>; 4822 bias-disable; 4823 }; 4824 4825 qup_spi4_cs: qup-spi4-cs-state { 4826 pins = "gpio51"; 4827 function = "qup1_se4"; 4828 drive-strength = <6>; 4829 bias-disable; 4830 }; 4831 4832 qup_spi4_data_clk: qup-spi4-data-clk-state { 4833 /* MISO, MOSI, CLK */ 4834 pins = "gpio48", "gpio49", "gpio50"; 4835 function = "qup1_se4"; 4836 drive-strength = <6>; 4837 bias-disable; 4838 }; 4839 4840 qup_spi5_cs: qup-spi5-cs-state { 4841 pins = "gpio55"; 4842 function = "qup1_se5"; 4843 drive-strength = <6>; 4844 bias-disable; 4845 }; 4846 4847 qup_spi5_data_clk: qup-spi5-data-clk-state { 4848 /* MISO, MOSI, CLK */ 4849 pins = "gpio52", "gpio53", "gpio54"; 4850 function = "qup1_se5"; 4851 drive-strength = <6>; 4852 bias-disable; 4853 }; 4854 4855 qup_spi6_cs: qup-spi6-cs-state { 4856 pins = "gpio59"; 4857 function = "qup1_se6"; 4858 drive-strength = <6>; 4859 bias-disable; 4860 }; 4861 4862 qup_spi6_data_clk: qup-spi6-data-clk-state { 4863 /* MISO, MOSI, CLK */ 4864 pins = "gpio56", "gpio57", "gpio58"; 4865 function = "qup1_se6"; 4866 drive-strength = <6>; 4867 bias-disable; 4868 }; 4869 4870 qup_spi7_cs: qup-spi7-cs-state { 4871 pins = "gpio63"; 4872 function = "qup1_se7"; 4873 drive-strength = <6>; 4874 bias-disable; 4875 }; 4876 4877 qup_spi7_data_clk: qup-spi7-data-clk-state { 4878 /* MISO, MOSI, CLK */ 4879 pins = "gpio60", "gpio61", "gpio62"; 4880 function = "qup1_se7"; 4881 drive-strength = <6>; 4882 bias-disable; 4883 }; 4884 4885 qup_spi8_cs: qup-spi8-cs-state { 4886 pins = "gpio3"; 4887 function = "qup2_se0"; 4888 drive-strength = <6>; 4889 bias-disable; 4890 }; 4891 4892 qup_spi8_data_clk: qup-spi8-data-clk-state { 4893 /* MISO, MOSI, CLK */ 4894 pins = "gpio0", "gpio1", "gpio2"; 4895 function = "qup2_se0"; 4896 drive-strength = <6>; 4897 bias-disable; 4898 }; 4899 4900 qup_spi9_cs: qup-spi9-cs-state { 4901 pins = "gpio7"; 4902 function = "qup2_se1"; 4903 drive-strength = <6>; 4904 bias-disable; 4905 }; 4906 4907 qup_spi9_data_clk: qup-spi9-data-clk-state { 4908 /* MISO, MOSI, CLK */ 4909 pins = "gpio4", "gpio5", "gpio6"; 4910 function = "qup2_se1"; 4911 drive-strength = <6>; 4912 bias-disable; 4913 }; 4914 4915 qup_spi10_cs: qup-spi10-cs-state { 4916 pins = "gpio11"; 4917 function = "qup2_se2"; 4918 drive-strength = <6>; 4919 bias-disable; 4920 }; 4921 4922 qup_spi10_data_clk: qup-spi10-data-clk-state { 4923 /* MISO, MOSI, CLK */ 4924 pins = "gpio8", "gpio9", "gpio10"; 4925 function = "qup2_se2"; 4926 drive-strength = <6>; 4927 bias-disable; 4928 }; 4929 4930 qup_spi11_cs: qup-spi11-cs-state { 4931 pins = "gpio15"; 4932 function = "qup2_se3"; 4933 drive-strength = <6>; 4934 bias-disable; 4935 }; 4936 4937 qup_spi11_data_clk: qup-spi11-data-clk-state { 4938 /* MISO, MOSI, CLK */ 4939 pins = "gpio12", "gpio13", "gpio14"; 4940 function = "qup2_se3"; 4941 drive-strength = <6>; 4942 bias-disable; 4943 }; 4944 4945 qup_spi12_cs: qup-spi12-cs-state { 4946 pins = "gpio19"; 4947 function = "qup2_se4"; 4948 drive-strength = <6>; 4949 bias-disable; 4950 }; 4951 4952 qup_spi12_data_clk: qup-spi12-data-clk-state { 4953 /* MISO, MOSI, CLK */ 4954 pins = "gpio16", "gpio17", "gpio18"; 4955 function = "qup2_se4"; 4956 drive-strength = <6>; 4957 bias-disable; 4958 }; 4959 4960 qup_spi13_cs: qup-spi13-cs-state { 4961 pins = "gpio23"; 4962 function = "qup2_se5"; 4963 drive-strength = <6>; 4964 bias-disable; 4965 }; 4966 4967 qup_spi13_data_clk: qup-spi13-data-clk-state { 4968 /* MISO, MOSI, CLK */ 4969 pins = "gpio20", "gpio21", "gpio22"; 4970 function = "qup2_se5"; 4971 drive-strength = <6>; 4972 bias-disable; 4973 }; 4974 4975 qup_spi14_cs: qup-spi14-cs-state { 4976 pins = "gpio27"; 4977 function = "qup2_se6"; 4978 drive-strength = <6>; 4979 bias-disable; 4980 }; 4981 4982 qup_spi14_data_clk: qup-spi14-data-clk-state { 4983 /* MISO, MOSI, CLK */ 4984 pins = "gpio24", "gpio25", "gpio26"; 4985 function = "qup2_se6"; 4986 drive-strength = <6>; 4987 bias-disable; 4988 }; 4989 4990 qup_uart14_default: qup-uart14-default-state { 4991 /* TX, RX */ 4992 pins = "gpio26", "gpio27"; 4993 function = "qup2_se6"; 4994 drive-strength = <2>; 4995 bias-pull-up; 4996 }; 4997 4998 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 4999 /* CTS, RTS */ 5000 pins = "gpio24", "gpio25"; 5001 function = "qup2_se6"; 5002 drive-strength = <2>; 5003 bias-pull-down; 5004 }; 5005 5006 qup_uart15_default: qup-uart15-default-state { 5007 /* TX, RX */ 5008 pins = "gpio30", "gpio31"; 5009 function = "qup2_se7"; 5010 drive-strength = <2>; 5011 bias-disable; 5012 }; 5013 5014 sdc2_sleep: sdc2-sleep-state { 5015 clk-pins { 5016 pins = "sdc2_clk"; 5017 drive-strength = <2>; 5018 bias-disable; 5019 }; 5020 5021 cmd-pins { 5022 pins = "sdc2_cmd"; 5023 drive-strength = <2>; 5024 bias-pull-up; 5025 }; 5026 5027 data-pins { 5028 pins = "sdc2_data"; 5029 drive-strength = <2>; 5030 bias-pull-up; 5031 }; 5032 }; 5033 5034 sdc2_default: sdc2-default-state { 5035 clk-pins { 5036 pins = "sdc2_clk"; 5037 drive-strength = <16>; 5038 bias-disable; 5039 }; 5040 5041 cmd-pins { 5042 pins = "sdc2_cmd"; 5043 drive-strength = <10>; 5044 bias-pull-up; 5045 }; 5046 5047 data-pins { 5048 pins = "sdc2_data"; 5049 drive-strength = <10>; 5050 bias-pull-up; 5051 }; 5052 }; 5053 }; 5054 5055 funnel@10042000 { 5056 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 5057 5058 reg = <0x0 0x10042000 0x0 0x1000>; 5059 5060 clocks = <&aoss_qmp>; 5061 clock-names = "apb_pclk"; 5062 5063 in-ports { 5064 #address-cells = <1>; 5065 #size-cells = <0>; 5066 5067 port@4 { 5068 reg = <4>; 5069 5070 funnel_in1_in_funnel_apss: endpoint { 5071 remote-endpoint = <&funnel_apss_out_funnel_in1>; 5072 }; 5073 }; 5074 }; 5075 5076 out-ports { 5077 port { 5078 funnel_in1_out_funnel_qdss: endpoint { 5079 remote-endpoint = <&funnel_qdss_in_funnel_in1>; 5080 }; 5081 }; 5082 }; 5083 }; 5084 5085 funnel@10045000 { 5086 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 5087 5088 reg = <0x0 0x10045000 0x0 0x1000>; 5089 5090 clocks = <&aoss_qmp>; 5091 clock-names = "apb_pclk"; 5092 5093 in-ports { 5094 #address-cells = <1>; 5095 #size-cells = <0>; 5096 5097 port@1 { 5098 reg = <1>; 5099 5100 funnel_qdss_in_funnel_in1: endpoint { 5101 remote-endpoint = <&funnel_in1_out_funnel_qdss>; 5102 }; 5103 }; 5104 }; 5105 5106 out-ports { 5107 port { 5108 funnel_qdss_out_funnel_aoss: endpoint { 5109 remote-endpoint = <&funnel_aoss_in_funnel_qdss>; 5110 }; 5111 }; 5112 }; 5113 }; 5114 5115 funnel@10b04000 { 5116 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 5117 5118 reg = <0x0 0x10b04000 0x0 0x1000>; 5119 5120 clocks = <&aoss_qmp>; 5121 clock-names = "apb_pclk"; 5122 5123 in-ports { 5124 #address-cells = <1>; 5125 #size-cells = <0>; 5126 5127 port@7 { 5128 reg = <7>; 5129 5130 funnel_aoss_in_funnel_qdss: endpoint { 5131 remote-endpoint = <&funnel_qdss_out_funnel_aoss>; 5132 }; 5133 }; 5134 }; 5135 5136 out-ports { 5137 port { 5138 funnel_aoss_out_tmc_etf: endpoint { 5139 remote-endpoint = <&tmc_etf_in_funnel_aoss>; 5140 }; 5141 }; 5142 }; 5143 }; 5144 5145 tmc@10b05000 { 5146 compatible = "arm,coresight-tmc", "arm,primecell"; 5147 5148 reg = <0x0 0x10b05000 0x0 0x1000>; 5149 5150 clocks = <&aoss_qmp>; 5151 clock-names = "apb_pclk"; 5152 5153 in-ports { 5154 port { 5155 tmc_etf_in_funnel_aoss: endpoint { 5156 remote-endpoint = <&funnel_aoss_out_tmc_etf>; 5157 }; 5158 }; 5159 }; 5160 }; 5161 5162 funnel@13810000 { 5163 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 5164 5165 reg = <0x0 0x13810000 0x0 0x1000>; 5166 5167 clocks = <&aoss_qmp>; 5168 clock-names = "apb_pclk"; 5169 5170 in-ports { 5171 port { 5172 funnel_apss_in_funnel_ete: endpoint { 5173 remote-endpoint = <&funnel_ete_out_funnel_apss>; 5174 }; 5175 }; 5176 }; 5177 5178 out-ports { 5179 port { 5180 funnel_apss_out_funnel_in1: endpoint { 5181 remote-endpoint = <&funnel_in1_in_funnel_apss>; 5182 }; 5183 }; 5184 }; 5185 }; 5186 5187 apps_smmu: iommu@15000000 { 5188 compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5189 reg = <0 0x15000000 0 0x100000>; 5190 5191 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5192 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5193 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5194 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5195 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5196 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5197 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5198 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5199 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5200 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5201 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5202 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5203 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5204 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5205 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5206 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5207 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5208 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5209 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5210 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5211 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5212 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5213 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5214 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5215 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5216 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5217 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5218 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5219 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5220 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5221 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5222 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5223 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5224 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5225 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5226 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5227 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5228 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5229 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5230 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5231 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5232 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5233 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5234 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5235 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5236 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5237 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5238 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5239 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5240 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5241 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5242 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5243 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5244 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5245 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5246 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5247 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5248 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5249 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5250 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5251 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5252 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5253 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5254 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5255 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5256 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5257 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5258 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5259 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5260 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5261 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5262 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5263 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5264 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5265 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5266 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5267 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5268 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5269 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5270 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5271 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5272 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5273 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5274 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5275 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5276 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 5277 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5278 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5279 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5280 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 5281 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5282 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5283 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5284 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5285 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5286 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5287 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 5288 5289 #iommu-cells = <2>; 5290 #global-interrupts = <1>; 5291 5292 dma-coherent; 5293 }; 5294 5295 intc: interrupt-controller@17100000 { 5296 compatible = "arm,gic-v3"; 5297 reg = <0 0x17100000 0 0x10000>, /* GICD */ 5298 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 5299 5300 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5301 5302 #interrupt-cells = <3>; 5303 interrupt-controller; 5304 5305 #redistributor-regions = <1>; 5306 redistributor-stride = <0 0x40000>; 5307 5308 #address-cells = <2>; 5309 #size-cells = <2>; 5310 ranges; 5311 5312 gic_its: msi-controller@17140000 { 5313 compatible = "arm,gic-v3-its"; 5314 reg = <0 0x17140000 0 0x20000>; 5315 5316 msi-controller; 5317 #msi-cells = <1>; 5318 }; 5319 }; 5320 5321 timer@17420000 { 5322 compatible = "arm,armv7-timer-mem"; 5323 reg = <0 0x17420000 0 0x1000>; 5324 5325 ranges = <0 0 0 0x20000000>; 5326 #address-cells = <1>; 5327 #size-cells = <1>; 5328 5329 frame@17421000 { 5330 reg = <0x17421000 0x1000>, 5331 <0x17422000 0x1000>; 5332 5333 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5334 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5335 5336 frame-number = <0>; 5337 }; 5338 5339 frame@17423000 { 5340 reg = <0x17423000 0x1000>; 5341 5342 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5343 5344 frame-number = <1>; 5345 5346 status = "disabled"; 5347 }; 5348 5349 frame@17425000 { 5350 reg = <0x17425000 0x1000>; 5351 5352 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5353 5354 frame-number = <2>; 5355 5356 status = "disabled"; 5357 }; 5358 5359 frame@17427000 { 5360 reg = <0x17427000 0x1000>; 5361 5362 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5363 5364 frame-number = <3>; 5365 5366 status = "disabled"; 5367 }; 5368 5369 frame@17429000 { 5370 reg = <0x17429000 0x1000>; 5371 5372 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5373 5374 frame-number = <4>; 5375 5376 status = "disabled"; 5377 }; 5378 5379 frame@1742b000 { 5380 reg = <0x1742b000 0x1000>; 5381 5382 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5383 5384 frame-number = <5>; 5385 5386 status = "disabled"; 5387 }; 5388 5389 frame@1742d000 { 5390 reg = <0x1742d000 0x1000>; 5391 5392 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5393 5394 frame-number = <6>; 5395 5396 status = "disabled"; 5397 }; 5398 }; 5399 5400 apps_rsc: rsc@17a00000 { 5401 compatible = "qcom,rpmh-rsc"; 5402 reg = <0 0x17a00000 0 0x10000>, 5403 <0 0x17a10000 0 0x10000>, 5404 <0 0x17a20000 0 0x10000>, 5405 <0 0x17a30000 0 0x10000>; 5406 reg-names = "drv-0", 5407 "drv-1", 5408 "drv-2"; 5409 5410 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5411 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5412 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5413 5414 power-domains = <&cluster_pd>; 5415 5416 qcom,tcs-offset = <0xd00>; 5417 qcom,drv-id = <2>; 5418 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 5419 <WAKE_TCS 2>, <CONTROL_TCS 0>; 5420 5421 label = "apps_rsc"; 5422 5423 apps_bcm_voter: bcm-voter { 5424 compatible = "qcom,bcm-voter"; 5425 }; 5426 5427 rpmhcc: clock-controller { 5428 compatible = "qcom,sm8650-rpmh-clk"; 5429 5430 clocks = <&xo_board>; 5431 clock-names = "xo"; 5432 5433 #clock-cells = <1>; 5434 }; 5435 5436 rpmhpd: power-controller { 5437 compatible = "qcom,sm8650-rpmhpd"; 5438 5439 operating-points-v2 = <&rpmhpd_opp_table>; 5440 5441 #power-domain-cells = <1>; 5442 5443 rpmhpd_opp_table: opp-table { 5444 compatible = "operating-points-v2"; 5445 5446 rpmhpd_opp_ret: opp-16 { 5447 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5448 }; 5449 5450 rpmhpd_opp_min_svs: opp-48 { 5451 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5452 }; 5453 5454 rpmhpd_opp_low_svs_d2: opp-52 { 5455 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 5456 }; 5457 5458 rpmhpd_opp_low_svs_d1: opp-56 { 5459 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 5460 }; 5461 5462 rpmhpd_opp_low_svs_d0: opp-60 { 5463 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 5464 }; 5465 5466 rpmhpd_opp_low_svs: opp-64 { 5467 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5468 }; 5469 5470 rpmhpd_opp_low_svs_l1: opp-80 { 5471 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 5472 }; 5473 5474 rpmhpd_opp_svs: opp-128 { 5475 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5476 }; 5477 5478 rpmhpd_opp_svs_l0: opp-144 { 5479 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 5480 }; 5481 5482 rpmhpd_opp_svs_l1: opp-192 { 5483 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5484 }; 5485 5486 rpmhpd_opp_nom: opp-256 { 5487 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5488 }; 5489 5490 rpmhpd_opp_nom_l1: opp-320 { 5491 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5492 }; 5493 5494 rpmhpd_opp_nom_l2: opp-336 { 5495 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5496 }; 5497 5498 rpmhpd_opp_turbo: opp-384 { 5499 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5500 }; 5501 5502 rpmhpd_opp_turbo_l1: opp-416 { 5503 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5504 }; 5505 }; 5506 }; 5507 }; 5508 5509 cpufreq_hw: cpufreq@17d91000 { 5510 compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss"; 5511 reg = <0 0x17d91000 0 0x1000>, 5512 <0 0x17d92000 0 0x1000>, 5513 <0 0x17d93000 0 0x1000>, 5514 <0 0x17d94000 0 0x1000>; 5515 reg-names = "freq-domain0", 5516 "freq-domain1", 5517 "freq-domain2", 5518 "freq-domain3"; 5519 5520 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5521 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5522 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 5523 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 5524 interrupt-names = "dcvsh-irq-0", 5525 "dcvsh-irq-1", 5526 "dcvsh-irq-2", 5527 "dcvsh-irq-3"; 5528 5529 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 5530 clock-names = "xo", "alternate"; 5531 5532 #freq-domain-cells = <1>; 5533 #clock-cells = <1>; 5534 }; 5535 5536 pmu@24091000 { 5537 compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 5538 reg = <0 0x24091000 0 0x1000>; 5539 5540 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 5541 5542 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 5543 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5544 5545 operating-points-v2 = <&llcc_bwmon_opp_table>; 5546 5547 llcc_bwmon_opp_table: opp-table { 5548 compatible = "operating-points-v2"; 5549 5550 opp-0 { 5551 opp-peak-kBps = <2086000>; 5552 }; 5553 5554 opp-1 { 5555 opp-peak-kBps = <2929000>; 5556 }; 5557 5558 opp-2 { 5559 opp-peak-kBps = <5931000>; 5560 }; 5561 5562 opp-3 { 5563 opp-peak-kBps = <6515000>; 5564 }; 5565 5566 opp-4 { 5567 opp-peak-kBps = <7980000>; 5568 }; 5569 5570 opp-5 { 5571 opp-peak-kBps = <10437000>; 5572 }; 5573 5574 opp-6 { 5575 opp-peak-kBps = <12157000>; 5576 }; 5577 5578 opp-7 { 5579 opp-peak-kBps = <14060000>; 5580 }; 5581 5582 opp-8 { 5583 opp-peak-kBps = <16113000>; 5584 }; 5585 }; 5586 }; 5587 5588 pmu@240b7400 { 5589 compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon"; 5590 reg = <0 0x240b7400 0 0x600>; 5591 5592 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 5593 5594 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5595 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 5596 5597 operating-points-v2 = <&cpu_bwmon_opp_table>; 5598 5599 cpu_bwmon_opp_table: opp-table { 5600 compatible = "operating-points-v2"; 5601 5602 opp-0 { 5603 opp-peak-kBps = <4577000>; 5604 }; 5605 5606 opp-1 { 5607 opp-peak-kBps = <7110000>; 5608 }; 5609 5610 opp-2 { 5611 opp-peak-kBps = <9155000>; 5612 }; 5613 5614 opp-3 { 5615 opp-peak-kBps = <12298000>; 5616 }; 5617 5618 opp-4 { 5619 opp-peak-kBps = <14236000>; 5620 }; 5621 5622 opp-5 { 5623 opp-peak-kBps = <16265000>; 5624 }; 5625 }; 5626 }; 5627 5628 gem_noc: interconnect@24100000 { 5629 compatible = "qcom,sm8650-gem-noc"; 5630 reg = <0 0x24100000 0 0xc5080>; 5631 5632 qcom,bcm-voters = <&apps_bcm_voter>; 5633 5634 #interconnect-cells = <2>; 5635 }; 5636 5637 system-cache-controller@25000000 { 5638 compatible = "qcom,sm8650-llcc"; 5639 reg = <0 0x25000000 0 0x200000>, 5640 <0 0x25400000 0 0x200000>, 5641 <0 0x25200000 0 0x200000>, 5642 <0 0x25600000 0 0x200000>, 5643 <0 0x25800000 0 0x200000>, 5644 <0 0x25a00000 0 0x200000>; 5645 reg-names = "llcc0_base", 5646 "llcc1_base", 5647 "llcc2_base", 5648 "llcc3_base", 5649 "llcc_broadcast_base", 5650 "llcc_broadcast_and_base"; 5651 5652 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 5653 }; 5654 5655 nsp_noc: interconnect@320c0000 { 5656 compatible = "qcom,sm8650-nsp-noc"; 5657 reg = <0 0x320c0000 0 0xf080>; 5658 5659 qcom,bcm-voters = <&apps_bcm_voter>; 5660 5661 #interconnect-cells = <2>; 5662 }; 5663 5664 remoteproc_cdsp: remoteproc@32300000 { 5665 compatible = "qcom,sm8650-cdsp-pas"; 5666 reg = <0x0 0x32300000 0x0 0x10000>; 5667 5668 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 5669 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 5670 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 5671 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 5672 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 5673 interrupt-names = "wdog", 5674 "fatal", 5675 "ready", 5676 "handover", 5677 "stop-ack"; 5678 5679 clocks = <&rpmhcc RPMH_CXO_CLK>; 5680 clock-names = "xo"; 5681 5682 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 5683 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5684 5685 power-domains = <&rpmhpd RPMHPD_CX>, 5686 <&rpmhpd RPMHPD_MXC>, 5687 <&rpmhpd RPMHPD_NSP>; 5688 power-domain-names = "cx", 5689 "mxc", 5690 "nsp"; 5691 5692 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>; 5693 5694 qcom,qmp = <&aoss_qmp>; 5695 5696 qcom,smem-states = <&smp2p_cdsp_out 0>; 5697 qcom,smem-state-names = "stop"; 5698 5699 status = "disabled"; 5700 5701 glink-edge { 5702 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 5703 IPCC_MPROC_SIGNAL_GLINK_QMP 5704 IRQ_TYPE_EDGE_RISING>; 5705 5706 mboxes = <&ipcc IPCC_CLIENT_CDSP 5707 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5708 5709 qcom,remote-pid = <5>; 5710 5711 label = "cdsp"; 5712 5713 fastrpc { 5714 compatible = "qcom,fastrpc"; 5715 5716 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5717 5718 label = "cdsp"; 5719 5720 qcom,non-secure-domain; 5721 5722 #address-cells = <1>; 5723 #size-cells = <0>; 5724 5725 compute-cb@1 { 5726 compatible = "qcom,fastrpc-compute-cb"; 5727 reg = <1>; 5728 5729 iommus = <&apps_smmu 0x1961 0x0>, 5730 <&apps_smmu 0x0c01 0x20>, 5731 <&apps_smmu 0x19c1 0x0>; 5732 dma-coherent; 5733 }; 5734 5735 compute-cb@2 { 5736 compatible = "qcom,fastrpc-compute-cb"; 5737 reg = <2>; 5738 5739 iommus = <&apps_smmu 0x1962 0x0>, 5740 <&apps_smmu 0x0c02 0x20>, 5741 <&apps_smmu 0x19c2 0x0>; 5742 dma-coherent; 5743 }; 5744 5745 compute-cb@3 { 5746 compatible = "qcom,fastrpc-compute-cb"; 5747 reg = <3>; 5748 5749 iommus = <&apps_smmu 0x1963 0x0>, 5750 <&apps_smmu 0x0c03 0x20>, 5751 <&apps_smmu 0x19c3 0x0>; 5752 dma-coherent; 5753 }; 5754 5755 compute-cb@4 { 5756 compatible = "qcom,fastrpc-compute-cb"; 5757 reg = <4>; 5758 5759 iommus = <&apps_smmu 0x1964 0x0>, 5760 <&apps_smmu 0x0c04 0x20>, 5761 <&apps_smmu 0x19c4 0x0>; 5762 dma-coherent; 5763 }; 5764 5765 compute-cb@5 { 5766 compatible = "qcom,fastrpc-compute-cb"; 5767 reg = <5>; 5768 5769 iommus = <&apps_smmu 0x1965 0x0>, 5770 <&apps_smmu 0x0c05 0x20>, 5771 <&apps_smmu 0x19c5 0x0>; 5772 dma-coherent; 5773 }; 5774 5775 compute-cb@6 { 5776 compatible = "qcom,fastrpc-compute-cb"; 5777 reg = <6>; 5778 5779 iommus = <&apps_smmu 0x1966 0x0>, 5780 <&apps_smmu 0x0c06 0x20>, 5781 <&apps_smmu 0x19c6 0x0>; 5782 dma-coherent; 5783 }; 5784 5785 compute-cb@7 { 5786 compatible = "qcom,fastrpc-compute-cb"; 5787 reg = <7>; 5788 5789 iommus = <&apps_smmu 0x1967 0x0>, 5790 <&apps_smmu 0x0c07 0x20>, 5791 <&apps_smmu 0x19c7 0x0>; 5792 dma-coherent; 5793 }; 5794 5795 compute-cb@8 { 5796 compatible = "qcom,fastrpc-compute-cb"; 5797 reg = <8>; 5798 5799 iommus = <&apps_smmu 0x1968 0x0>, 5800 <&apps_smmu 0x0c08 0x20>, 5801 <&apps_smmu 0x19c8 0x0>; 5802 dma-coherent; 5803 }; 5804 5805 /* note: secure cb9 in downstream */ 5806 5807 compute-cb@12 { 5808 compatible = "qcom,fastrpc-compute-cb"; 5809 reg = <12>; 5810 5811 iommus = <&apps_smmu 0x196c 0x0>, 5812 <&apps_smmu 0x0c0c 0x20>, 5813 <&apps_smmu 0x19cc 0x0>; 5814 dma-coherent; 5815 }; 5816 5817 compute-cb@13 { 5818 compatible = "qcom,fastrpc-compute-cb"; 5819 reg = <13>; 5820 5821 iommus = <&apps_smmu 0x196d 0x0>, 5822 <&apps_smmu 0x0c0d 0x20>, 5823 <&apps_smmu 0x19cd 0x0>; 5824 dma-coherent; 5825 }; 5826 5827 compute-cb@14 { 5828 compatible = "qcom,fastrpc-compute-cb"; 5829 reg = <14>; 5830 5831 iommus = <&apps_smmu 0x196e 0x0>, 5832 <&apps_smmu 0x0c0e 0x20>, 5833 <&apps_smmu 0x19ce 0x0>; 5834 dma-coherent; 5835 }; 5836 }; 5837 }; 5838 }; 5839 }; 5840 5841 thermal-zones { 5842 aoss0-thermal { 5843 thermal-sensors = <&tsens0 0>; 5844 5845 trips { 5846 trip-point0 { 5847 temperature = <90000>; 5848 hysteresis = <2000>; 5849 type = "hot"; 5850 }; 5851 5852 aoss0-critical { 5853 temperature = <110000>; 5854 hysteresis = <0>; 5855 type = "critical"; 5856 }; 5857 }; 5858 }; 5859 5860 cpuss0-thermal { 5861 thermal-sensors = <&tsens0 1>; 5862 5863 trips { 5864 trip-point0 { 5865 temperature = <90000>; 5866 hysteresis = <2000>; 5867 type = "hot"; 5868 }; 5869 5870 cpuss0-critical { 5871 temperature = <110000>; 5872 hysteresis = <0>; 5873 type = "critical"; 5874 }; 5875 }; 5876 }; 5877 5878 cpuss1-thermal { 5879 thermal-sensors = <&tsens0 2>; 5880 5881 trips { 5882 trip-point0 { 5883 temperature = <90000>; 5884 hysteresis = <2000>; 5885 type = "hot"; 5886 }; 5887 5888 cpuss1-critical { 5889 temperature = <110000>; 5890 hysteresis = <0>; 5891 type = "critical"; 5892 }; 5893 }; 5894 }; 5895 5896 cpuss2-thermal { 5897 thermal-sensors = <&tsens0 3>; 5898 5899 trips { 5900 trip-point0 { 5901 temperature = <90000>; 5902 hysteresis = <2000>; 5903 type = "hot"; 5904 }; 5905 5906 cpuss2-critical { 5907 temperature = <110000>; 5908 hysteresis = <0>; 5909 type = "critical"; 5910 }; 5911 }; 5912 }; 5913 5914 cpuss3-thermal { 5915 thermal-sensors = <&tsens0 4>; 5916 5917 trips { 5918 trip-point0 { 5919 temperature = <90000>; 5920 hysteresis = <2000>; 5921 type = "hot"; 5922 }; 5923 5924 cpuss3-critical { 5925 temperature = <110000>; 5926 hysteresis = <0>; 5927 type = "critical"; 5928 }; 5929 }; 5930 }; 5931 5932 cpu2-top-thermal { 5933 thermal-sensors = <&tsens0 5>; 5934 5935 trips { 5936 trip-point0 { 5937 temperature = <90000>; 5938 hysteresis = <2000>; 5939 type = "passive"; 5940 }; 5941 5942 trip-point1 { 5943 temperature = <95000>; 5944 hysteresis = <2000>; 5945 type = "passive"; 5946 }; 5947 5948 cpu2-critical { 5949 temperature = <110000>; 5950 hysteresis = <1000>; 5951 type = "critical"; 5952 }; 5953 }; 5954 }; 5955 5956 cpu2-bottom-thermal { 5957 thermal-sensors = <&tsens0 6>; 5958 5959 trips { 5960 trip-point0 { 5961 temperature = <90000>; 5962 hysteresis = <2000>; 5963 type = "passive"; 5964 }; 5965 5966 trip-point1 { 5967 temperature = <95000>; 5968 hysteresis = <2000>; 5969 type = "passive"; 5970 }; 5971 5972 cpu2-critical { 5973 temperature = <110000>; 5974 hysteresis = <1000>; 5975 type = "critical"; 5976 }; 5977 }; 5978 }; 5979 5980 cpu3-top-thermal { 5981 thermal-sensors = <&tsens0 7>; 5982 5983 trips { 5984 trip-point0 { 5985 temperature = <90000>; 5986 hysteresis = <2000>; 5987 type = "passive"; 5988 }; 5989 5990 trip-point1 { 5991 temperature = <95000>; 5992 hysteresis = <2000>; 5993 type = "passive"; 5994 }; 5995 5996 cpu3-critical { 5997 temperature = <110000>; 5998 hysteresis = <1000>; 5999 type = "critical"; 6000 }; 6001 }; 6002 }; 6003 6004 cpu3-bottom-thermal { 6005 thermal-sensors = <&tsens0 8>; 6006 6007 trips { 6008 trip-point0 { 6009 temperature = <90000>; 6010 hysteresis = <2000>; 6011 type = "passive"; 6012 }; 6013 6014 trip-point1 { 6015 temperature = <95000>; 6016 hysteresis = <2000>; 6017 type = "passive"; 6018 }; 6019 6020 cpu3-critical { 6021 temperature = <110000>; 6022 hysteresis = <1000>; 6023 type = "critical"; 6024 }; 6025 }; 6026 }; 6027 6028 cpu4-top-thermal { 6029 thermal-sensors = <&tsens0 9>; 6030 6031 trips { 6032 trip-point0 { 6033 temperature = <90000>; 6034 hysteresis = <2000>; 6035 type = "passive"; 6036 }; 6037 6038 trip-point1 { 6039 temperature = <95000>; 6040 hysteresis = <2000>; 6041 type = "passive"; 6042 }; 6043 6044 cpu4-critical { 6045 temperature = <110000>; 6046 hysteresis = <1000>; 6047 type = "critical"; 6048 }; 6049 }; 6050 }; 6051 6052 cpu4-bottom-thermal { 6053 thermal-sensors = <&tsens0 10>; 6054 6055 trips { 6056 trip-point0 { 6057 temperature = <90000>; 6058 hysteresis = <2000>; 6059 type = "passive"; 6060 }; 6061 6062 trip-point1 { 6063 temperature = <95000>; 6064 hysteresis = <2000>; 6065 type = "passive"; 6066 }; 6067 6068 cpu4-critical { 6069 temperature = <110000>; 6070 hysteresis = <1000>; 6071 type = "critical"; 6072 }; 6073 }; 6074 }; 6075 6076 cpu5-top-thermal { 6077 thermal-sensors = <&tsens0 11>; 6078 6079 trips { 6080 trip-point0 { 6081 temperature = <90000>; 6082 hysteresis = <2000>; 6083 type = "passive"; 6084 }; 6085 6086 trip-point1 { 6087 temperature = <95000>; 6088 hysteresis = <2000>; 6089 type = "passive"; 6090 }; 6091 6092 cpu5-critical { 6093 temperature = <110000>; 6094 hysteresis = <1000>; 6095 type = "critical"; 6096 }; 6097 }; 6098 }; 6099 6100 cpu5-bottom-thermal { 6101 thermal-sensors = <&tsens0 12>; 6102 6103 trips { 6104 trip-point0 { 6105 temperature = <90000>; 6106 hysteresis = <2000>; 6107 type = "passive"; 6108 }; 6109 6110 trip-point1 { 6111 temperature = <95000>; 6112 hysteresis = <2000>; 6113 type = "passive"; 6114 }; 6115 6116 cpu5-critical { 6117 temperature = <110000>; 6118 hysteresis = <1000>; 6119 type = "critical"; 6120 }; 6121 }; 6122 }; 6123 6124 cpu6-top-thermal { 6125 thermal-sensors = <&tsens0 13>; 6126 6127 trips { 6128 trip-point0 { 6129 temperature = <90000>; 6130 hysteresis = <2000>; 6131 type = "passive"; 6132 }; 6133 6134 trip-point1 { 6135 temperature = <95000>; 6136 hysteresis = <2000>; 6137 type = "passive"; 6138 }; 6139 6140 cpu6-critical { 6141 temperature = <110000>; 6142 hysteresis = <1000>; 6143 type = "critical"; 6144 }; 6145 }; 6146 }; 6147 6148 cpu6-bottom-thermal { 6149 thermal-sensors = <&tsens0 14>; 6150 6151 trips { 6152 trip-point0 { 6153 temperature = <90000>; 6154 hysteresis = <2000>; 6155 type = "passive"; 6156 }; 6157 6158 trip-point1 { 6159 temperature = <95000>; 6160 hysteresis = <2000>; 6161 type = "passive"; 6162 }; 6163 6164 cpu6-critical { 6165 temperature = <110000>; 6166 hysteresis = <1000>; 6167 type = "critical"; 6168 }; 6169 }; 6170 }; 6171 6172 aoss1-thermal { 6173 thermal-sensors = <&tsens1 0>; 6174 6175 trips { 6176 trip-point0 { 6177 temperature = <90000>; 6178 hysteresis = <2000>; 6179 type = "hot"; 6180 }; 6181 6182 aoss1-critical { 6183 temperature = <110000>; 6184 hysteresis = <0>; 6185 type = "critical"; 6186 }; 6187 }; 6188 }; 6189 6190 cpu7-top-thermal { 6191 thermal-sensors = <&tsens1 1>; 6192 6193 trips { 6194 trip-point0 { 6195 temperature = <90000>; 6196 hysteresis = <2000>; 6197 type = "passive"; 6198 }; 6199 6200 trip-point1 { 6201 temperature = <95000>; 6202 hysteresis = <2000>; 6203 type = "passive"; 6204 }; 6205 6206 cpu7-critical { 6207 temperature = <110000>; 6208 hysteresis = <1000>; 6209 type = "critical"; 6210 }; 6211 }; 6212 }; 6213 6214 cpu7-middle-thermal { 6215 thermal-sensors = <&tsens1 2>; 6216 6217 trips { 6218 trip-point0 { 6219 temperature = <90000>; 6220 hysteresis = <2000>; 6221 type = "passive"; 6222 }; 6223 6224 trip-point1 { 6225 temperature = <95000>; 6226 hysteresis = <2000>; 6227 type = "passive"; 6228 }; 6229 6230 cpu7-critical { 6231 temperature = <110000>; 6232 hysteresis = <1000>; 6233 type = "critical"; 6234 }; 6235 }; 6236 }; 6237 6238 cpu7-bottom-thermal { 6239 thermal-sensors = <&tsens1 3>; 6240 6241 trips { 6242 trip-point0 { 6243 temperature = <90000>; 6244 hysteresis = <2000>; 6245 type = "passive"; 6246 }; 6247 6248 trip-point1 { 6249 temperature = <95000>; 6250 hysteresis = <2000>; 6251 type = "passive"; 6252 }; 6253 6254 cpu7-critical { 6255 temperature = <110000>; 6256 hysteresis = <1000>; 6257 type = "critical"; 6258 }; 6259 }; 6260 }; 6261 6262 cpu0-thermal { 6263 thermal-sensors = <&tsens1 4>; 6264 6265 trips { 6266 trip-point0 { 6267 temperature = <90000>; 6268 hysteresis = <2000>; 6269 type = "passive"; 6270 }; 6271 6272 trip-point1 { 6273 temperature = <95000>; 6274 hysteresis = <2000>; 6275 type = "passive"; 6276 }; 6277 6278 cpu0-critical { 6279 temperature = <110000>; 6280 hysteresis = <1000>; 6281 type = "critical"; 6282 }; 6283 }; 6284 }; 6285 6286 cpu1-thermal { 6287 thermal-sensors = <&tsens1 5>; 6288 6289 trips { 6290 trip-point0 { 6291 temperature = <90000>; 6292 hysteresis = <2000>; 6293 type = "passive"; 6294 }; 6295 6296 trip-point1 { 6297 temperature = <95000>; 6298 hysteresis = <2000>; 6299 type = "passive"; 6300 }; 6301 6302 cpu1-critical { 6303 temperature = <110000>; 6304 hysteresis = <1000>; 6305 type = "critical"; 6306 }; 6307 }; 6308 }; 6309 6310 nsphvx0-thermal { 6311 polling-delay-passive = <10>; 6312 6313 thermal-sensors = <&tsens2 6>; 6314 6315 trips { 6316 trip-point0 { 6317 temperature = <90000>; 6318 hysteresis = <2000>; 6319 type = "hot"; 6320 }; 6321 6322 nsphvx1-critical { 6323 temperature = <110000>; 6324 hysteresis = <0>; 6325 type = "critical"; 6326 }; 6327 }; 6328 }; 6329 6330 nsphvx1-thermal { 6331 polling-delay-passive = <10>; 6332 6333 thermal-sensors = <&tsens2 7>; 6334 6335 trips { 6336 trip-point0 { 6337 temperature = <90000>; 6338 hysteresis = <2000>; 6339 type = "hot"; 6340 }; 6341 6342 nsphvx1-critical { 6343 temperature = <110000>; 6344 hysteresis = <0>; 6345 type = "critical"; 6346 }; 6347 }; 6348 }; 6349 6350 nsphmx0-thermal { 6351 polling-delay-passive = <10>; 6352 6353 thermal-sensors = <&tsens2 8>; 6354 6355 trips { 6356 trip-point0 { 6357 temperature = <90000>; 6358 hysteresis = <2000>; 6359 type = "hot"; 6360 }; 6361 6362 nsphmx0-critical { 6363 temperature = <110000>; 6364 hysteresis = <0>; 6365 type = "critical"; 6366 }; 6367 }; 6368 }; 6369 6370 nsphmx1-thermal { 6371 polling-delay-passive = <10>; 6372 6373 thermal-sensors = <&tsens2 9>; 6374 6375 trips { 6376 trip-point0 { 6377 temperature = <90000>; 6378 hysteresis = <2000>; 6379 type = "hot"; 6380 }; 6381 6382 nsphmx1-critical { 6383 temperature = <110000>; 6384 hysteresis = <0>; 6385 type = "critical"; 6386 }; 6387 }; 6388 }; 6389 6390 nsphmx2-thermal { 6391 polling-delay-passive = <10>; 6392 6393 thermal-sensors = <&tsens2 10>; 6394 6395 trips { 6396 trip-point0 { 6397 temperature = <90000>; 6398 hysteresis = <2000>; 6399 type = "hot"; 6400 }; 6401 6402 nsphmx2-critical { 6403 temperature = <110000>; 6404 hysteresis = <0>; 6405 type = "critical"; 6406 }; 6407 }; 6408 }; 6409 6410 nsphmx3-thermal { 6411 polling-delay-passive = <10>; 6412 6413 thermal-sensors = <&tsens2 11>; 6414 6415 trips { 6416 trip-point0 { 6417 temperature = <90000>; 6418 hysteresis = <2000>; 6419 type = "hot"; 6420 }; 6421 6422 nsphmx3-critical { 6423 temperature = <110000>; 6424 hysteresis = <0>; 6425 type = "critical"; 6426 }; 6427 }; 6428 }; 6429 6430 video-thermal { 6431 polling-delay-passive = <10>; 6432 6433 thermal-sensors = <&tsens1 12>; 6434 6435 trips { 6436 trip-point0 { 6437 temperature = <90000>; 6438 hysteresis = <2000>; 6439 type = "hot"; 6440 }; 6441 6442 video-critical { 6443 temperature = <110000>; 6444 hysteresis = <0>; 6445 type = "critical"; 6446 }; 6447 }; 6448 }; 6449 6450 ddr-thermal { 6451 polling-delay-passive = <10>; 6452 6453 thermal-sensors = <&tsens1 13>; 6454 6455 trips { 6456 trip-point0 { 6457 temperature = <90000>; 6458 hysteresis = <2000>; 6459 type = "hot"; 6460 }; 6461 6462 ddr-critical { 6463 temperature = <110000>; 6464 hysteresis = <0>; 6465 type = "critical"; 6466 }; 6467 }; 6468 }; 6469 6470 camera0-thermal { 6471 thermal-sensors = <&tsens1 14>; 6472 6473 trips { 6474 trip-point0 { 6475 temperature = <90000>; 6476 hysteresis = <2000>; 6477 type = "hot"; 6478 }; 6479 6480 camera0-critical { 6481 temperature = <110000>; 6482 hysteresis = <0>; 6483 type = "critical"; 6484 }; 6485 }; 6486 }; 6487 6488 camera1-thermal { 6489 thermal-sensors = <&tsens1 15>; 6490 6491 trips { 6492 trip-point0 { 6493 temperature = <90000>; 6494 hysteresis = <2000>; 6495 type = "hot"; 6496 }; 6497 6498 camera1-critical { 6499 temperature = <110000>; 6500 hysteresis = <0>; 6501 type = "critical"; 6502 }; 6503 }; 6504 }; 6505 6506 aoss2-thermal { 6507 thermal-sensors = <&tsens2 0>; 6508 6509 trips { 6510 trip-point0 { 6511 temperature = <90000>; 6512 hysteresis = <2000>; 6513 type = "hot"; 6514 }; 6515 6516 aoss2-critical { 6517 temperature = <110000>; 6518 hysteresis = <0>; 6519 type = "critical"; 6520 }; 6521 }; 6522 }; 6523 6524 gpuss0-thermal { 6525 polling-delay-passive = <10>; 6526 6527 thermal-sensors = <&tsens2 1>; 6528 6529 cooling-maps { 6530 map0 { 6531 trip = <&gpu0_alert0>; 6532 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6533 }; 6534 }; 6535 6536 trips { 6537 gpu0_alert0: trip-point0 { 6538 temperature = <85000>; 6539 hysteresis = <1000>; 6540 type = "passive"; 6541 }; 6542 6543 trip-point1 { 6544 temperature = <90000>; 6545 hysteresis = <1000>; 6546 type = "hot"; 6547 }; 6548 6549 trip-point2 { 6550 temperature = <110000>; 6551 hysteresis = <1000>; 6552 type = "critical"; 6553 }; 6554 }; 6555 }; 6556 6557 gpuss1-thermal { 6558 polling-delay-passive = <10>; 6559 6560 thermal-sensors = <&tsens2 2>; 6561 6562 cooling-maps { 6563 map0 { 6564 trip = <&gpu1_alert0>; 6565 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6566 }; 6567 }; 6568 6569 trips { 6570 gpu1_alert0: trip-point0 { 6571 temperature = <85000>; 6572 hysteresis = <1000>; 6573 type = "passive"; 6574 }; 6575 6576 trip-point1 { 6577 temperature = <90000>; 6578 hysteresis = <1000>; 6579 type = "hot"; 6580 }; 6581 6582 trip-point2 { 6583 temperature = <110000>; 6584 hysteresis = <1000>; 6585 type = "critical"; 6586 }; 6587 }; 6588 }; 6589 6590 gpuss2-thermal { 6591 polling-delay-passive = <10>; 6592 6593 thermal-sensors = <&tsens2 3>; 6594 6595 cooling-maps { 6596 map0 { 6597 trip = <&gpu2_alert0>; 6598 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6599 }; 6600 }; 6601 6602 trips { 6603 gpu2_alert0: trip-point0 { 6604 temperature = <85000>; 6605 hysteresis = <1000>; 6606 type = "passive"; 6607 }; 6608 6609 trip-point1 { 6610 temperature = <90000>; 6611 hysteresis = <1000>; 6612 type = "hot"; 6613 }; 6614 6615 trip-point2 { 6616 temperature = <110000>; 6617 hysteresis = <1000>; 6618 type = "critical"; 6619 }; 6620 }; 6621 }; 6622 6623 gpuss3-thermal { 6624 polling-delay-passive = <10>; 6625 6626 thermal-sensors = <&tsens2 4>; 6627 6628 cooling-maps { 6629 map0 { 6630 trip = <&gpu3_alert0>; 6631 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6632 }; 6633 }; 6634 6635 trips { 6636 gpu3_alert0: trip-point0 { 6637 temperature = <85000>; 6638 hysteresis = <1000>; 6639 type = "passive"; 6640 }; 6641 6642 trip-point1 { 6643 temperature = <90000>; 6644 hysteresis = <1000>; 6645 type = "hot"; 6646 }; 6647 6648 trip-point2 { 6649 temperature = <110000>; 6650 hysteresis = <1000>; 6651 type = "critical"; 6652 }; 6653 }; 6654 }; 6655 6656 gpuss4-thermal { 6657 polling-delay-passive = <10>; 6658 6659 thermal-sensors = <&tsens2 5>; 6660 6661 cooling-maps { 6662 map0 { 6663 trip = <&gpu4_alert0>; 6664 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6665 }; 6666 }; 6667 6668 trips { 6669 gpu4_alert0: trip-point0 { 6670 temperature = <85000>; 6671 hysteresis = <1000>; 6672 type = "passive"; 6673 }; 6674 6675 trip-point1 { 6676 temperature = <90000>; 6677 hysteresis = <1000>; 6678 type = "hot"; 6679 }; 6680 6681 trip-point2 { 6682 temperature = <110000>; 6683 hysteresis = <1000>; 6684 type = "critical"; 6685 }; 6686 }; 6687 }; 6688 6689 gpuss5-thermal { 6690 polling-delay-passive = <10>; 6691 6692 thermal-sensors = <&tsens2 6>; 6693 6694 cooling-maps { 6695 map0 { 6696 trip = <&gpu5_alert0>; 6697 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6698 }; 6699 }; 6700 6701 trips { 6702 gpu5_alert0: trip-point0 { 6703 temperature = <85000>; 6704 hysteresis = <1000>; 6705 type = "passive"; 6706 }; 6707 6708 trip-point1 { 6709 temperature = <90000>; 6710 hysteresis = <1000>; 6711 type = "hot"; 6712 }; 6713 6714 trip-point2 { 6715 temperature = <110000>; 6716 hysteresis = <1000>; 6717 type = "critical"; 6718 }; 6719 }; 6720 }; 6721 6722 gpuss6-thermal { 6723 polling-delay-passive = <10>; 6724 6725 thermal-sensors = <&tsens2 7>; 6726 6727 cooling-maps { 6728 map0 { 6729 trip = <&gpu6_alert0>; 6730 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6731 }; 6732 }; 6733 6734 trips { 6735 gpu6_alert0: trip-point0 { 6736 temperature = <85000>; 6737 hysteresis = <1000>; 6738 type = "passive"; 6739 }; 6740 6741 trip-point1 { 6742 temperature = <90000>; 6743 hysteresis = <1000>; 6744 type = "hot"; 6745 }; 6746 6747 trip-point2 { 6748 temperature = <110000>; 6749 hysteresis = <1000>; 6750 type = "critical"; 6751 }; 6752 }; 6753 }; 6754 6755 gpuss7-thermal { 6756 polling-delay-passive = <10>; 6757 6758 thermal-sensors = <&tsens2 8>; 6759 6760 cooling-maps { 6761 map0 { 6762 trip = <&gpu7_alert0>; 6763 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6764 }; 6765 }; 6766 6767 trips { 6768 gpu7_alert0: trip-point0 { 6769 temperature = <85000>; 6770 hysteresis = <1000>; 6771 type = "passive"; 6772 }; 6773 6774 trip-point1 { 6775 temperature = <90000>; 6776 hysteresis = <1000>; 6777 type = "hot"; 6778 }; 6779 6780 trip-point2 { 6781 temperature = <110000>; 6782 hysteresis = <1000>; 6783 type = "critical"; 6784 }; 6785 }; 6786 }; 6787 6788 modem0-thermal { 6789 thermal-sensors = <&tsens2 9>; 6790 6791 trips { 6792 trip-point0 { 6793 temperature = <90000>; 6794 hysteresis = <2000>; 6795 type = "hot"; 6796 }; 6797 6798 modem0-critical { 6799 temperature = <110000>; 6800 hysteresis = <0>; 6801 type = "critical"; 6802 }; 6803 }; 6804 }; 6805 6806 modem1-thermal { 6807 thermal-sensors = <&tsens2 10>; 6808 6809 trips { 6810 trip-point0 { 6811 temperature = <90000>; 6812 hysteresis = <2000>; 6813 type = "hot"; 6814 }; 6815 6816 modem1-critical { 6817 temperature = <110000>; 6818 hysteresis = <0>; 6819 type = "critical"; 6820 }; 6821 }; 6822 }; 6823 6824 modem2-thermal { 6825 thermal-sensors = <&tsens2 11>; 6826 6827 trips { 6828 trip-point0 { 6829 temperature = <90000>; 6830 hysteresis = <2000>; 6831 type = "hot"; 6832 }; 6833 6834 modem2-critical { 6835 temperature = <110000>; 6836 hysteresis = <0>; 6837 type = "critical"; 6838 }; 6839 }; 6840 }; 6841 6842 modem3-thermal { 6843 thermal-sensors = <&tsens2 12>; 6844 6845 trips { 6846 trip-point0 { 6847 temperature = <90000>; 6848 hysteresis = <2000>; 6849 type = "hot"; 6850 }; 6851 6852 modem3-critical { 6853 temperature = <110000>; 6854 hysteresis = <0>; 6855 type = "critical"; 6856 }; 6857 }; 6858 }; 6859 }; 6860 6861 timer { 6862 compatible = "arm,armv8-timer"; 6863 6864 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6865 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6866 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6867 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6868 }; 6869}; 6870