1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP)
8
9maintainers:
10  - Vinod Koul <[email protected]>
11
12description:
13  The QMP PHY controller supports physical layer functionality for a number of
14  controllers on Qualcomm chipsets, such as, PCIe, UFS and USB.
15
16properties:
17  compatible:
18    enum:
19      - qcom,sar2130p-qmp-usb3-dp-phy
20      - qcom,sc7180-qmp-usb3-dp-phy
21      - qcom,sc7280-qmp-usb3-dp-phy
22      - qcom,sc8180x-qmp-usb3-dp-phy
23      - qcom,sc8280xp-qmp-usb43dp-phy
24      - qcom,sdm845-qmp-usb3-dp-phy
25      - qcom,sm6350-qmp-usb3-dp-phy
26      - qcom,sm8150-qmp-usb3-dp-phy
27      - qcom,sm8250-qmp-usb3-dp-phy
28      - qcom,sm8350-qmp-usb3-dp-phy
29      - qcom,sm8450-qmp-usb3-dp-phy
30      - qcom,sm8550-qmp-usb3-dp-phy
31      - qcom,sm8650-qmp-usb3-dp-phy
32      - qcom,x1e80100-qmp-usb3-dp-phy
33
34  reg:
35    maxItems: 1
36
37  clocks:
38    minItems: 4
39    maxItems: 5
40
41  clock-names:
42    minItems: 4
43    items:
44      - const: aux
45      - const: ref
46      - const: com_aux
47      - const: usb3_pipe
48      - const: cfg_ahb
49
50  power-domains:
51    maxItems: 1
52
53  resets:
54    maxItems: 2
55
56  reset-names:
57    items:
58      - const: phy
59      - const: common
60
61  vdda-phy-supply: true
62
63  vdda-pll-supply: true
64
65  "#clock-cells":
66    const: 1
67    description:
68      See include/dt-bindings/phy/phy-qcom-qmp.h
69
70  "#phy-cells":
71    const: 1
72    description:
73      See include/dt-bindings/phy/phy-qcom-qmp.h
74
75  orientation-switch:
76    description:
77      Flag the PHY as possible handler of USB Type-C orientation switching
78    type: boolean
79
80  ports:
81    $ref: /schemas/graph.yaml#/properties/ports
82    properties:
83      port@0:
84        $ref: /schemas/graph.yaml#/properties/port
85        description: Output endpoint of the PHY
86
87      port@1:
88        $ref: /schemas/graph.yaml#/properties/port
89        description: Incoming endpoint from the USB controller
90
91      port@2:
92        $ref: /schemas/graph.yaml#/properties/port
93        description: Incoming endpoint from the DisplayPort controller
94
95required:
96  - compatible
97  - reg
98  - clocks
99  - clock-names
100  - resets
101  - reset-names
102  - vdda-phy-supply
103  - vdda-pll-supply
104  - "#clock-cells"
105  - "#phy-cells"
106
107allOf:
108  - if:
109      properties:
110        compatible:
111          enum:
112            - qcom,sc7180-qmp-usb3-dp-phy
113            - qcom,sdm845-qmp-usb3-dp-phy
114    then:
115      properties:
116        clocks:
117          maxItems: 5
118        clock-names:
119          maxItems: 5
120    else:
121      properties:
122        clocks:
123          maxItems: 4
124        clock-names:
125          maxItems: 4
126
127  - if:
128      properties:
129        compatible:
130          enum:
131            - qcom,sar2130p-qmp-usb3-dp-phy
132            - qcom,sc8280xp-qmp-usb43dp-phy
133            - qcom,sm6350-qmp-usb3-dp-phy
134            - qcom,sm8550-qmp-usb3-dp-phy
135            - qcom,sm8650-qmp-usb3-dp-phy
136            - qcom,x1e80100-qmp-usb3-dp-phy
137    then:
138      required:
139        - power-domains
140    else:
141      properties:
142        power-domains: false
143
144additionalProperties: false
145
146examples:
147  - |
148    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
149
150    phy@88eb000 {
151      compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
152      reg = <0x088eb000 0x4000>;
153
154      clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
155               <&gcc GCC_USB4_EUD_CLKREF_CLK>,
156               <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
157               <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
158      clock-names = "aux", "ref", "com_aux", "usb3_pipe";
159
160      power-domains = <&gcc USB30_PRIM_GDSC>;
161
162      resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
163               <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
164      reset-names = "phy", "common";
165
166      vdda-phy-supply = <&vreg_l9d>;
167      vdda-pll-supply = <&vreg_l4d>;
168
169      orientation-switch;
170
171      #clock-cells = <1>;
172      #phy-cells = <1>;
173
174      ports {
175          #address-cells = <1>;
176          #size-cells = <0>;
177
178          port@0 {
179              reg = <0>;
180
181              endpoint {
182                  remote-endpoint = <&typec_connector_ss>;
183              };
184          };
185
186          port@1 {
187              reg = <1>;
188
189              endpoint {
190                  remote-endpoint = <&dwc3_ss_out>;
191              };
192          };
193
194          port@2 {
195              reg = <2>;
196
197              endpoint {
198                  remote-endpoint = <&mdss_dp_out>;
199              };
200          };
201      };
202    };
203