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/linux-6.14.4/Documentation/devicetree/bindings/riscv/
Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <[email protected]>
11 - Palmer Dabbelt <[email protected]>
12 - Conor Dooley <[email protected]>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
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Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <[email protected]>
11 - Palmer Dabbelt <[email protected]>
12 - Conor Dooley <[email protected]>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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/linux-6.14.4/Documentation/arch/riscv/
Dhwprobe.rst1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Hardware Probing Interface
4 ---------------------------------
6 The RISC-V hardware probing interface is based around a single syscall, which
18 The arguments are split into three groups: an array of key-value pairs, a CPU
19 set, and some flags. The key-value pairs are supplied with a count. Userspace
22 will be cleared to -1, and its value set to 0. The CPU set is defined by
23 CPU_SET(3) with size ``cpusetsize`` bytes. For value-like keys (eg. vendor,
25 have the same value. Otherwise -1 will be returned. For boolean-like keys, the
33 by sys_riscv_hwprobe() to only those which match each of the key-value pairs.
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Duabi.rst1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Linux User ABI
6 ISA string ordering in /proc/cpuinfo
7 ------------------------------------
9 The canonical order of ISA extension names in the ISA string is defined in
14 #. Single-letter extensions come first, in canonical order.
17 #. All multi-letter extensions will be separated from other extensions by an
20 #. Additional standard extensions (starting with 'Z') will be sorted after
21 single-letter extensions and before any higher-privileged extensions.
23 #. For additional standard extensions, the first letter following the 'Z'
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/linux-6.14.4/arch/riscv/boot/dts/sophgo/
Dsg2042-cpus.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #address-cells = <1>;
9 #size-cells = <0>;
10 timebase-frequency = <50000000>;
12 cpu-map {
259 riscv,isa = "rv64imafdc";
260 riscv,isa-base = "rv64i";
261 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
265 i-cache-block-size = <64>;
266 i-cache-size = <65536>;
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/linux-6.14.4/arch/riscv/kernel/
Dcpufeature.c1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <asm/text-patching.h>
32 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
38 /* Host ISA bitmap */
41 /* Per-cpu ISA extensions. */
47 * riscv_isa_extension_base() - Get base extension word
49 * @isa_bitmap: ISA bitmap to use
52 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
63 * __riscv_isa_extension_available() - Check whether given extension
66 * @isa_bitmap: ISA bitmap to use
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Dcpu.c1 // SPDX-License-Identifier: GPL-2.0-only
27 * Returns the hart ID of the given device tree node, or -ENODEV if the node
28 * isn't an enabled and valid RISC-V hart node.
37 return -ENODEV; in riscv_of_processor_hartid()
45 return -ENODEV; in riscv_of_processor_hartid()
52 const char *isa; in riscv_early_of_processor_hartid() local
56 return -ENODEV; in riscv_early_of_processor_hartid()
62 return -ENODEV; in riscv_early_of_processor_hartid()
67 return -ENODEV; in riscv_early_of_processor_hartid()
70 if (of_property_read_string(node, "riscv,isa-base", &isa)) in riscv_early_of_processor_hartid()
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/linux-6.14.4/arch/riscv/boot/dts/spacemit/
Dk1.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <24000000>;
18 cpu-map {
54 …riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_z…
55 riscv,isa-base = "rv64i";
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/linux-6.14.4/arch/riscv/kernel/pi/
Dfdt_early.c1 // SPDX-License-Identifier: GPL-2.0-only
19 prop = fdt_getprop_w((void *)dtb_pa, node, "kaslr-seed", &len); in get_kaslr_seed()
29 * fdt_device_is_available - check if a device is available for use
78 * isa_string_contains - check if isa string contains an extension
80 * @isa_str: isa string to search
83 * Returns true if the extension is in the given isa string,
97 /* Search for single chars between rv32/64 and multi-letter extensions */ in isa_string_contains()
105 /* Skip to start of multi-letter extensions */ in isa_string_contains()
114 /* Multi-letter extensions must be split from other multi-letter in isa_string_contains()
115 * extensions with an "_", the end of a multi-letter extension will in isa_string_contains()
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/linux-6.14.4/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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Dfu740-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
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/linux-6.14.4/arch/riscv/include/asm/
Dcpufeature.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright 2022-2024 Rivos, Inc
13 #include <linux/percpu-defs.h>
16 #include <asm/cpufeature-macros.h>
29 DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
34 /* Per-cpu ISA extensions. */
60 /* Used to declare extensions that are a superset of other extensions (Zvbb for instance) */
126 return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); in riscv_cpu_has_extension_likely()
137 return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); in riscv_cpu_has_extension_unlikely()
Dhwcap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #define RISCV_ISA_EXT_a ('a' - 'a')
14 #define RISCV_ISA_EXT_c ('c' - 'a')
15 #define RISCV_ISA_EXT_d ('d' - 'a')
16 #define RISCV_ISA_EXT_f ('f' - 'a')
17 #define RISCV_ISA_EXT_h ('h' - 'a')
18 #define RISCV_ISA_EXT_i ('i' - 'a')
19 #define RISCV_ISA_EXT_m ('m' - 'a')
20 #define RISCV_ISA_EXT_q ('q' - 'a')
21 #define RISCV_ISA_EXT_v ('v' - 'a')
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/linux-6.14.4/arch/riscv/kvm/
Dvcpu_onereg.c1 // SPDX-License-Identifier: GPL-2.0
26 /* Mapping between KVM ISA Extension ID & Host ISA extension ID */
28 /* Single letter extensions (alphabetically sorted) */
37 /* Multi letter extensions (alphabetically sorted) */
123 * The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero. in kvm_riscv_vcpu_isa_enable_allowed()
139 /* Extensions which don't have any mechanism to disable */ in kvm_riscv_vcpu_isa_disable_allowed()
200 /* Extensions which can be disabled using Smstateen */ in kvm_riscv_vcpu_isa_disable_allowed()
205 * The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero. in kvm_riscv_vcpu_isa_disable_allowed()
224 set_bit(host_isa, vcpu->arch.isa); in kvm_riscv_vcpu_setup_isa()
232 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_get_reg_config()
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/linux-6.14.4/arch/riscv/boot/dts/microchip/
Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
21 i-cache-block-size = <64>;
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/linux-6.14.4/arch/riscv/kernel/vendor_extensions/
Dthead.c1 // SPDX-License-Identifier: GPL-2.0-only
11 /* All T-Head vendor extensions supported in Linux */
26 …t(RISCV_ISA_VENDOR_EXT_XTHEADVECTOR, riscv_isa_vendor_ext_list_thead.per_hart_isa_bitmap[cpu].isa); in disable_xtheadvector()
28 …r_bit(RISCV_ISA_VENDOR_EXT_XTHEADVECTOR, riscv_isa_vendor_ext_list_thead.all_harts_isa_bitmap.isa); in disable_xtheadvector()
/linux-6.14.4/arch/arm/crypto/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
14 - NEON (Advanced SIMD) extensions
17 tristate "Hash functions: GHASH (PMULL/NEON/ARMv8 Crypto Extensions)"
25 GCM GHASH function (NIST SP800-38D)
28 - PMULL (Polynomial Multiply Long) instructions
29 - NEON (Advanced SIMD) extensions
30 - ARMv8 Crypto Extensions
34 that is part of the ARMv8 Crypto Extensions, or a slower variant that
35 uses the vmull.p8 instruction that is part of the basic NEON ISA.
45 - NEON (Advanced SIMD) extensions
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/linux-6.14.4/arch/riscv/boot/dts/thead/
Dth1520.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <3000000>;
23 riscv,isa = "rv64imafdc";
24 riscv,isa-base = "rv64i";
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/linux-6.14.4/arch/riscv/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
66 # LLD >= 14: https://github.com/llvm/llvm-project/issues/50505
222 # -Zsanitizer=shadow-call-stack flag.
232 depends on $(cc-option,-fpatchable-function-entry=8)
235 def_bool $(cc-option,-fsanitize=shadow-call-stack)
236 …# https://github.com/riscv-non-isa/riscv-elf-psabi-doc/commit/a484e843e6eeb51f0cb7b8819e50da6d2444…
237 depends on $(ld-option,--no-relax-gp)
241 # https://github.com/llvm/llvm-project/commit/6611d58f5bbcbec77262d392e2923e1d680f6985
244 # https://github.com/llvm/llvm-project/commit/bbc0f99f3bc96f1db16f649fc21dd18e5b0918f6
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/linux-6.14.4/arch/powerpc/platforms/
DKconfig.cputype1 # SPDX-License-Identifier: GPL-2.0
7 bool "64-bit kernel"
10 This option selects whether a 32-bit or a 64-bit kernel
272 default "-mtune=power10" if $(cc-option,-mtune=power10)
273 default "-mtune=power9" if $(cc-option,-mtune=power9)
274 default "-mtune=power8" if $(cc-option,-mtune=power8)
351 This option enables kernel support for larger than 32-bit physical
356 is platform-dependent.
365 This option enables kernel support for the Altivec extensions to the
372 any affect on a non-altivec cpu (it does, however add code to the
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/linux-6.14.4/arch/riscv/boot/dts/starfive/
Djh7100.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
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Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/linux-6.14.4/arch/riscv/boot/dts/allwinner/
Dsun20i-d1s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <[email protected]>
6 #include "sunxi-d1s-t113.dtsi"
10 timebase-frequency = <24000000>;
11 #address-cells = <1>;
12 #size-cells = <0>;
19 d-cache-block-size = <64>;
20 d-cache-sets = <256>;
21 d-cache-size = <32768>;
22 i-cache-block-size = <64>;
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/linux-6.14.4/arch/riscv/include/asm/vendor_extensions/
Dvendor_hwprobe.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 if (__riscv_isa_extension_available(isainfo->isa, RISCV_ISA_VENDOR_EXT_##ext)) \
14 pair->value |= RISCV_HWPROBE_VENDOR_EXT_##ext; \
20 * Loop through and record extensions that 1) anyone has, and 2) anyone
23 * _extension_checks is an arbitrary C block to set the values of pair->value
34 (pair)->value &= ~missing; \
/linux-6.14.4/arch/riscv/boot/dts/renesas/
Dr9a07g043f.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <12000000>;
23 #cooling-cells = <2>;
26 riscv,isa = "rv64imafdc";
27 riscv,isa-base = "rv64i";
28 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
31 mmu-type = "riscv,sv39";
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