1 // SPDX-License-Identifier: GPL-2.0
26 /* Mapping between KVM ISA Extension ID & Host ISA extension ID */
28 	/* Single letter extensions (alphabetically sorted) */
37 	/* Multi letter extensions (alphabetically sorted) */
123 		 * The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero.  in kvm_riscv_vcpu_isa_enable_allowed()
139 	/* Extensions which don't have any mechanism to disable */  in kvm_riscv_vcpu_isa_disable_allowed()
200 	/* Extensions which can be disabled using Smstateen */  in kvm_riscv_vcpu_isa_disable_allowed()
205 		 * The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero.  in kvm_riscv_vcpu_isa_disable_allowed()
224 			set_bit(host_isa, vcpu->arch.isa);  in kvm_riscv_vcpu_setup_isa()
232 			(unsigned long __user *)(unsigned long)reg->addr;  in kvm_riscv_vcpu_get_reg_config()
233 	unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |  in kvm_riscv_vcpu_get_reg_config()
238 	if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))  in kvm_riscv_vcpu_get_reg_config()
239 		return -EINVAL;  in kvm_riscv_vcpu_get_reg_config()
242 	case KVM_REG_RISCV_CONFIG_REG(isa):  in kvm_riscv_vcpu_get_reg_config()
243 		reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK;  in kvm_riscv_vcpu_get_reg_config()
246 		if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM))  in kvm_riscv_vcpu_get_reg_config()
247 			return -ENOENT;  in kvm_riscv_vcpu_get_reg_config()
251 		if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ))  in kvm_riscv_vcpu_get_reg_config()
252 			return -ENOENT;  in kvm_riscv_vcpu_get_reg_config()
256 		reg_val = vcpu->arch.mvendorid;  in kvm_riscv_vcpu_get_reg_config()
259 		reg_val = vcpu->arch.marchid;  in kvm_riscv_vcpu_get_reg_config()
262 		reg_val = vcpu->arch.mimpid;  in kvm_riscv_vcpu_get_reg_config()
268 		return -ENOENT;  in kvm_riscv_vcpu_get_reg_config()
271 	if (copy_to_user(uaddr, &reg_val, KVM_REG_SIZE(reg->id)))  in kvm_riscv_vcpu_get_reg_config()
272 		return -EFAULT;  in kvm_riscv_vcpu_get_reg_config()
281 			(unsigned long __user *)(unsigned long)reg->addr;  in kvm_riscv_vcpu_set_reg_config()
282 	unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |  in kvm_riscv_vcpu_set_reg_config()
287 	if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))  in kvm_riscv_vcpu_set_reg_config()
288 		return -EINVAL;  in kvm_riscv_vcpu_set_reg_config()
290 	if (copy_from_user(&reg_val, uaddr, KVM_REG_SIZE(reg->id)))  in kvm_riscv_vcpu_set_reg_config()
291 		return -EFAULT;  in kvm_riscv_vcpu_set_reg_config()
294 	case KVM_REG_RISCV_CONFIG_REG(isa):  in kvm_riscv_vcpu_set_reg_config()
297 		 * single letter extensions.  in kvm_riscv_vcpu_set_reg_config()
300 			return -EINVAL;  in kvm_riscv_vcpu_set_reg_config()
306 		if (reg_val == (vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK))  in kvm_riscv_vcpu_set_reg_config()
309 		if (!vcpu->arch.ran_atleast_once) {  in kvm_riscv_vcpu_set_reg_config()
310 			/* Ignore the enable/disable request for certain extensions */  in kvm_riscv_vcpu_set_reg_config()
325 			/* Do not modify anything beyond single letter extensions */  in kvm_riscv_vcpu_set_reg_config()
326 			reg_val = (vcpu->arch.isa[0] & ~KVM_RISCV_BASE_ISA_MASK) |  in kvm_riscv_vcpu_set_reg_config()
328 			vcpu->arch.isa[0] = reg_val;  in kvm_riscv_vcpu_set_reg_config()
331 			return -EBUSY;  in kvm_riscv_vcpu_set_reg_config()
335 		if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM))  in kvm_riscv_vcpu_set_reg_config()
336 			return -ENOENT;  in kvm_riscv_vcpu_set_reg_config()
338 			return -EINVAL;  in kvm_riscv_vcpu_set_reg_config()
341 		if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ))  in kvm_riscv_vcpu_set_reg_config()
342 			return -ENOENT;  in kvm_riscv_vcpu_set_reg_config()
344 			return -EINVAL;  in kvm_riscv_vcpu_set_reg_config()
347 		if (reg_val == vcpu->arch.mvendorid)  in kvm_riscv_vcpu_set_reg_config()
349 		if (!vcpu->arch.ran_atleast_once)  in kvm_riscv_vcpu_set_reg_config()
350 			vcpu->arch.mvendorid = reg_val;  in kvm_riscv_vcpu_set_reg_config()
352 			return -EBUSY;  in kvm_riscv_vcpu_set_reg_config()
355 		if (reg_val == vcpu->arch.marchid)  in kvm_riscv_vcpu_set_reg_config()
357 		if (!vcpu->arch.ran_atleast_once)  in kvm_riscv_vcpu_set_reg_config()
358 			vcpu->arch.marchid = reg_val;  in kvm_riscv_vcpu_set_reg_config()
360 			return -EBUSY;  in kvm_riscv_vcpu_set_reg_config()
363 		if (reg_val == vcpu->arch.mimpid)  in kvm_riscv_vcpu_set_reg_config()
365 		if (!vcpu->arch.ran_atleast_once)  in kvm_riscv_vcpu_set_reg_config()
366 			vcpu->arch.mimpid = reg_val;  in kvm_riscv_vcpu_set_reg_config()
368 			return -EBUSY;  in kvm_riscv_vcpu_set_reg_config()
372 			return -EINVAL;  in kvm_riscv_vcpu_set_reg_config()
375 		return -ENOENT;  in kvm_riscv_vcpu_set_reg_config()
384 	struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;  in kvm_riscv_vcpu_get_reg_core()
386 			(unsigned long __user *)(unsigned long)reg->addr;  in kvm_riscv_vcpu_get_reg_core()
387 	unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |  in kvm_riscv_vcpu_get_reg_core()
392 	if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))  in kvm_riscv_vcpu_get_reg_core()
393 		return -EINVAL;  in kvm_riscv_vcpu_get_reg_core()
395 		return -ENOENT;  in kvm_riscv_vcpu_get_reg_core()
398 		reg_val = cntx->sepc;  in kvm_riscv_vcpu_get_reg_core()
403 		reg_val = (cntx->sstatus & SR_SPP) ?  in kvm_riscv_vcpu_get_reg_core()
406 		return -ENOENT;  in kvm_riscv_vcpu_get_reg_core()
408 	if (copy_to_user(uaddr, &reg_val, KVM_REG_SIZE(reg->id)))  in kvm_riscv_vcpu_get_reg_core()
409 		return -EFAULT;  in kvm_riscv_vcpu_get_reg_core()
417 	struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;  in kvm_riscv_vcpu_set_reg_core()
419 			(unsigned long __user *)(unsigned long)reg->addr;  in kvm_riscv_vcpu_set_reg_core()
420 	unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |  in kvm_riscv_vcpu_set_reg_core()
425 	if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))  in kvm_riscv_vcpu_set_reg_core()
426 		return -EINVAL;  in kvm_riscv_vcpu_set_reg_core()
428 		return -ENOENT;  in kvm_riscv_vcpu_set_reg_core()
430 	if (copy_from_user(&reg_val, uaddr, KVM_REG_SIZE(reg->id)))  in kvm_riscv_vcpu_set_reg_core()
431 		return -EFAULT;  in kvm_riscv_vcpu_set_reg_core()
434 		cntx->sepc = reg_val;  in kvm_riscv_vcpu_set_reg_core()
440 			cntx->sstatus |= SR_SPP;  in kvm_riscv_vcpu_set_reg_core()
442 			cntx->sstatus &= ~SR_SPP;  in kvm_riscv_vcpu_set_reg_core()
444 		return -ENOENT;  in kvm_riscv_vcpu_set_reg_core()
453 	struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;  in kvm_riscv_vcpu_general_get_csr()
456 		return -ENOENT;  in kvm_riscv_vcpu_general_get_csr()
460 		*out_val = (csr->hvip >> VSIP_TO_HVIP_SHIFT) & VSIP_VALID_MASK;  in kvm_riscv_vcpu_general_get_csr()
461 		*out_val |= csr->hvip & ~IRQ_LOCAL_MASK;  in kvm_riscv_vcpu_general_get_csr()
472 	struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;  in kvm_riscv_vcpu_general_set_csr()
475 		return -ENOENT;  in kvm_riscv_vcpu_general_set_csr()
485 		WRITE_ONCE(vcpu->arch.irqs_pending_mask[0], 0);  in kvm_riscv_vcpu_general_set_csr()
494 	struct kvm_vcpu_smstateen_csr *csr = &vcpu->arch.smstateen_csr;  in kvm_riscv_vcpu_smstateen_set_csr()
498 		return -EINVAL;  in kvm_riscv_vcpu_smstateen_set_csr()
508 	struct kvm_vcpu_smstateen_csr *csr = &vcpu->arch.smstateen_csr;  in kvm_riscv_vcpu_smstateen_get_csr()
512 		return -EINVAL;  in kvm_riscv_vcpu_smstateen_get_csr()
523 			(unsigned long __user *)(unsigned long)reg->addr;  in kvm_riscv_vcpu_get_reg_csr()
524 	unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |  in kvm_riscv_vcpu_get_reg_csr()
529 	if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))  in kvm_riscv_vcpu_get_reg_csr()
530 		return -EINVAL;  in kvm_riscv_vcpu_get_reg_csr()
542 		rc = -EINVAL;  in kvm_riscv_vcpu_get_reg_csr()
548 		rc = -ENOENT;  in kvm_riscv_vcpu_get_reg_csr()
554 	if (copy_to_user(uaddr, &reg_val, KVM_REG_SIZE(reg->id)))  in kvm_riscv_vcpu_get_reg_csr()
555 		return -EFAULT;  in kvm_riscv_vcpu_get_reg_csr()
565 			(unsigned long __user *)(unsigned long)reg->addr;  in kvm_riscv_vcpu_set_reg_csr()
566 	unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |  in kvm_riscv_vcpu_set_reg_csr()
571 	if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))  in kvm_riscv_vcpu_set_reg_csr()
572 		return -EINVAL;  in kvm_riscv_vcpu_set_reg_csr()
574 	if (copy_from_user(&reg_val, uaddr, KVM_REG_SIZE(reg->id)))  in kvm_riscv_vcpu_set_reg_csr()
575 		return -EFAULT;  in kvm_riscv_vcpu_set_reg_csr()
587 		rc = -EINVAL;  in kvm_riscv_vcpu_set_reg_csr()
593 		rc = -ENOENT;  in kvm_riscv_vcpu_set_reg_csr()
610 		return -ENOENT;  in riscv_vcpu_get_isa_ext_single()
614 		return -ENOENT;  in riscv_vcpu_get_isa_ext_single()
617 	if (__riscv_isa_extension_available(vcpu->arch.isa, host_isa_ext))  in riscv_vcpu_get_isa_ext_single()
631 		return -ENOENT;  in riscv_vcpu_set_isa_ext_single()
635 		return -ENOENT;  in riscv_vcpu_set_isa_ext_single()
637 	if (reg_val == test_bit(host_isa_ext, vcpu->arch.isa))  in riscv_vcpu_set_isa_ext_single()
640 	if (!vcpu->arch.ran_atleast_once) {  in riscv_vcpu_set_isa_ext_single()
642 		 * All multi-letter extension and a few single letter  in riscv_vcpu_set_isa_ext_single()
647 			set_bit(host_isa_ext, vcpu->arch.isa);  in riscv_vcpu_set_isa_ext_single()
650 			clear_bit(host_isa_ext, vcpu->arch.isa);  in riscv_vcpu_set_isa_ext_single()
652 			return -EINVAL;  in riscv_vcpu_set_isa_ext_single()
655 		return -EBUSY;  in riscv_vcpu_set_isa_ext_single()
668 		return -ENOENT;  in riscv_vcpu_get_isa_ext_multi()
691 		return -ENOENT;  in riscv_vcpu_set_isa_ext_multi()
709 			(unsigned long __user *)(unsigned long)reg->addr;  in kvm_riscv_vcpu_get_reg_isa_ext()
710 	unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |  in kvm_riscv_vcpu_get_reg_isa_ext()
715 	if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))  in kvm_riscv_vcpu_get_reg_isa_ext()
716 		return -EINVAL;  in kvm_riscv_vcpu_get_reg_isa_ext()
733 		rc = -ENOENT;  in kvm_riscv_vcpu_get_reg_isa_ext()
738 	if (copy_to_user(uaddr, &reg_val, KVM_REG_SIZE(reg->id)))  in kvm_riscv_vcpu_get_reg_isa_ext()
739 		return -EFAULT;  in kvm_riscv_vcpu_get_reg_isa_ext()
748 			(unsigned long __user *)(unsigned long)reg->addr;  in kvm_riscv_vcpu_set_reg_isa_ext()
749 	unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |  in kvm_riscv_vcpu_set_reg_isa_ext()
754 	if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))  in kvm_riscv_vcpu_set_reg_isa_ext()
755 		return -EINVAL;  in kvm_riscv_vcpu_set_reg_isa_ext()
760 	if (copy_from_user(&reg_val, uaddr, KVM_REG_SIZE(reg->id)))  in kvm_riscv_vcpu_set_reg_isa_ext()
761 		return -EFAULT;  in kvm_riscv_vcpu_set_reg_isa_ext()
771 		return -ENOENT;  in kvm_riscv_vcpu_set_reg_isa_ext()
792 			!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM))  in copy_config_reg_indices()
795 			!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ))  in copy_config_reg_indices()
803 				return -EFAULT;  in copy_config_reg_indices()
834 				return -EFAULT;  in copy_core_reg_indices()
846 	if (riscv_isa_extension_available(vcpu->arch.isa, SSAIA))  in num_csr_regs()
848 	if (riscv_isa_extension_available(vcpu->arch.isa, SMSTATEEN))  in num_csr_regs()
869 				return -EFAULT;  in copy_csr_reg_indices()
875 	if (riscv_isa_extension_available(vcpu->arch.isa, SSAIA)) {  in copy_csr_reg_indices()
886 					return -EFAULT;  in copy_csr_reg_indices()
893 	if (riscv_isa_extension_available(vcpu->arch.isa, SMSTATEEN)) {  in copy_csr_reg_indices()
904 					return -EFAULT;  in copy_csr_reg_indices()
928 				return -EFAULT;  in copy_timer_reg_indices()
938 	const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;  in num_fp_f_regs()
940 	if (riscv_isa_extension_available(vcpu->arch.isa, f))  in num_fp_f_regs()
941 		return sizeof(cntx->fp.f) / sizeof(u32);  in num_fp_f_regs()
957 				return -EFAULT;  in copy_fp_f_reg_indices()
967 	const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;  in num_fp_d_regs()
969 	if (riscv_isa_extension_available(vcpu->arch.isa, d))  in num_fp_d_regs()
970 		return sizeof(cntx->fp.d.f) / sizeof(u64) + 1;  in num_fp_d_regs()
983 	for (i = 0; i < n-1; i++) {  in copy_fp_d_reg_indices()
989 				return -EFAULT;  in copy_fp_d_reg_indices()
998 			return -EFAULT;  in copy_fp_d_reg_indices()
1022 				return -EFAULT;  in copy_isa_ext_reg_indices()
1052 				return -EFAULT;  in copy_sbi_ext_reg_indices()
1069 	struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context;  in copy_sbi_reg_indices()
1072 	if (scontext->ext_status[KVM_RISCV_SBI_EXT_STA] == KVM_RISCV_SBI_EXT_STATUS_ENABLED) {  in copy_sbi_reg_indices()
1083 					return -EFAULT;  in copy_sbi_reg_indices()
1101 	if (!riscv_isa_extension_available(vcpu->arch.isa, v))  in num_vector_regs()
1111 	const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;  in copy_vector_reg_indices()
1126 				return -EFAULT;  in copy_vector_reg_indices()
1132 	size = __builtin_ctzl(cntx->vector.vlenb);  in copy_vector_reg_indices()
1140 				return -EFAULT;  in copy_vector_reg_indices()
1149  * kvm_riscv_vcpu_num_regs - how many registers do we present via KVM_GET/SET_ONE_REG
1172  * kvm_riscv_vcpu_copy_reg_indices - get indices of all registers.
1235 	switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {  in kvm_riscv_vcpu_set_reg()
1262 	return -ENOENT;  in kvm_riscv_vcpu_set_reg()
1268 	switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {  in kvm_riscv_vcpu_get_reg()
1295 	return -ENOENT;  in kvm_riscv_vcpu_get_reg()