1# SPDX-License-Identifier: (GPL-2.0 OR MIT)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/riscv/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: RISC-V CPUs
8
9maintainers:
10  - Paul Walmsley <[email protected]>
11  - Palmer Dabbelt <[email protected]>
12  - Conor Dooley <[email protected]>
13
14description: |
15  This document uses some terminology common to the RISC-V community
16  that is not widely used, the definitions of which are listed here:
17
18  hart: A hardware execution context, which contains all the state
19  mandated by the RISC-V ISA: a PC and some registers.  This
20  terminology is designed to disambiguate software's view of execution
21  contexts from any particular microarchitectural implementation
22  strategy.  For example, an Intel laptop containing one socket with
23  two cores, each of which has two hyperthreads, could be described as
24  having four harts.
25
26allOf:
27  - $ref: /schemas/cpu.yaml#
28  - $ref: extensions.yaml
29  - if:
30      not:
31        properties:
32          compatible:
33            contains:
34              enum:
35                - thead,c906
36                - thead,c910
37                - thead,c920
38    then:
39      properties:
40        thead,vlenb: false
41
42properties:
43  compatible:
44    oneOf:
45      - items:
46          - enum:
47              - amd,mbv32
48              - andestech,ax45mp
49              - canaan,k210
50              - sifive,bullet0
51              - sifive,e5
52              - sifive,e7
53              - sifive,e71
54              - sifive,rocket0
55              - sifive,s7
56              - sifive,u5
57              - sifive,u54
58              - sifive,u7
59              - sifive,u74
60              - sifive,u74-mc
61              - spacemit,x60
62              - thead,c906
63              - thead,c908
64              - thead,c910
65              - thead,c920
66          - const: riscv
67      - items:
68          - enum:
69              - sifive,e51
70              - sifive,u54-mc
71          - const: sifive,rocket0
72          - const: riscv
73      - const: riscv    # Simulator only
74    description:
75      Identifies that the hart uses the RISC-V instruction set
76      and identifies the type of the hart.
77
78  mmu-type:
79    description:
80      Identifies the largest MMU address translation mode supported by
81      this hart.  These values originate from the RISC-V Privileged
82      Specification document, available from
83      https://riscv.org/specifications/
84    $ref: /schemas/types.yaml#/definitions/string
85    enum:
86      - riscv,sv32
87      - riscv,sv39
88      - riscv,sv48
89      - riscv,sv57
90      - riscv,none
91
92  reg:
93    description:
94      The hart ID of this CPU node.
95
96  riscv,cbom-block-size:
97    $ref: /schemas/types.yaml#/definitions/uint32
98    description:
99      The blocksize in bytes for the Zicbom cache operations.
100
101  riscv,cbop-block-size:
102    $ref: /schemas/types.yaml#/definitions/uint32
103    description:
104      The blocksize in bytes for the Zicbop cache operations.
105
106  riscv,cboz-block-size:
107    $ref: /schemas/types.yaml#/definitions/uint32
108    description:
109      The blocksize in bytes for the Zicboz cache operations.
110
111  thead,vlenb:
112    $ref: /schemas/types.yaml#/definitions/uint32
113    description:
114      VLEN/8, the vector register length in bytes. This property is required on
115      thead systems where the vector register length is not identical on all harts, or
116      the vlenb CSR is not available.
117
118  # RISC-V has multiple properties for cache op block sizes as the sizes
119  # differ between individual CBO extensions
120  cache-op-block-size: false
121  # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
122  timebase-frequency: false
123
124  interrupt-controller:
125    type: object
126    $ref: /schemas/interrupt-controller/riscv,cpu-intc.yaml#
127
128  cpu-idle-states:
129    $ref: /schemas/types.yaml#/definitions/phandle-array
130    items:
131      maxItems: 1
132    description: |
133      List of phandles to idle state nodes supported
134      by this hart (see ./idle-states.yaml).
135
136  capacity-dmips-mhz:
137    description:
138      u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
139      DMIPS/MHz, relative to highest capacity-dmips-mhz
140      in the system.
141
142anyOf:
143  - required:
144      - riscv,isa
145  - required:
146      - riscv,isa-base
147
148dependencies:
149  riscv,isa-base: [ "riscv,isa-extensions" ]
150  riscv,isa-extensions: [ "riscv,isa-base" ]
151
152required:
153  - interrupt-controller
154
155unevaluatedProperties: false
156
157examples:
158  - |
159    // Example 1: SiFive Freedom U540G Development Kit
160    cpus {
161        #address-cells = <1>;
162        #size-cells = <0>;
163        timebase-frequency = <1000000>;
164        cpu@0 {
165                clock-frequency = <0>;
166                compatible = "sifive,rocket0", "riscv";
167                device_type = "cpu";
168                i-cache-block-size = <64>;
169                i-cache-sets = <128>;
170                i-cache-size = <16384>;
171                reg = <0>;
172                riscv,isa-base = "rv64i";
173                riscv,isa-extensions = "i", "m", "a", "c";
174
175                cpu_intc0: interrupt-controller {
176                        #interrupt-cells = <1>;
177                        compatible = "riscv,cpu-intc";
178                        interrupt-controller;
179                };
180        };
181        cpu@1 {
182                clock-frequency = <0>;
183                compatible = "sifive,rocket0", "riscv";
184                d-cache-block-size = <64>;
185                d-cache-sets = <64>;
186                d-cache-size = <32768>;
187                d-tlb-sets = <1>;
188                d-tlb-size = <32>;
189                device_type = "cpu";
190                i-cache-block-size = <64>;
191                i-cache-sets = <64>;
192                i-cache-size = <32768>;
193                i-tlb-sets = <1>;
194                i-tlb-size = <32>;
195                mmu-type = "riscv,sv39";
196                reg = <1>;
197                tlb-split;
198                riscv,isa-base = "rv64i";
199                riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
200
201                cpu_intc1: interrupt-controller {
202                        #interrupt-cells = <1>;
203                        compatible = "riscv,cpu-intc";
204                        interrupt-controller;
205                };
206        };
207    };
208
209  - |
210    // Example 2: Spike ISA Simulator with 1 Hart
211    cpus {
212        #address-cells = <1>;
213        #size-cells = <0>;
214        cpu@0 {
215                device_type = "cpu";
216                reg = <0>;
217                compatible = "riscv";
218                mmu-type = "riscv,sv48";
219                riscv,isa-base = "rv64i";
220                riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
221
222                interrupt-controller {
223                        #interrupt-cells = <1>;
224                        interrupt-controller;
225                        compatible = "riscv,cpu-intc";
226                };
227        };
228    };
229...
230