Lines Matching +full:isa +full:- +full:extensions
1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <[email protected]>
11 - Palmer Dabbelt <[email protected]>
12 - Conor Dooley <[email protected]>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
17 are "vendor" extensions.
23 The properties for standard extensions therefore map to their originally
24 ratified states, with the exception of the I, Zicntr & Zihpm extensions.
34 riscv,isa:
36 Identifies the specific RISC-V instruction set architecture
37 supported by the hart. These are documented in the RISC-V
38 User-Level ISA document, available from
41 Due to revisions of the ISA specification, some deviations
43 Notably, riscv,isa was defined prior to the creation of the
44 Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i"
47 While the isa strings in ISA specification are case
48 insensitive, letters in the riscv,isa string must be all
51 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$
54 riscv,isa-base:
56 The base ISA implemented by this hart, as described by the 20191213
57 version of the unprivileged ISA specification.
59 - rv32i
60 - rv64i
62 riscv,isa-extensions:
63 $ref: /schemas/types.yaml#/definitions/string-array
65 description: Extensions supported by the hart.
68 # single letter extensions, in canonical order
69 - const: i
72 version of the unprivileged ISA specification.
75 the Zicntr and Zihpm extensions after the ratification of the
78 - const: m
81 ratified in the 20191213 version of the unprivileged ISA
84 - const: a
87 20191213 version of the unprivileged ISA specification.
89 - const: f
91 The standard F extension for single-precision floating point, as
92 ratified in the 20191213 version of the unprivileged ISA
95 - const: d
97 The standard D extension for double-precision floating-point, as
98 ratified in the 20191213 version of the unprivileged ISA
101 - const: q
103 The standard Q extension for quad-precision floating-point, as
104 ratified in the 20191213 version of the unprivileged ISA
107 - const: c
110 the 20191213 version of the unprivileged ISA specification.
112 - const: v
115 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f
116 encoding") of the riscv-v-spec.
118 - const: h
121 version of the privileged ISA specification.
123 # multi-letter extensions, sorted alphanumerically
124 - const: smaia
126 The standard Smaia supervisor-level extension for the advanced
127 interrupt architecture for machine-mode-visible csr and behavioural
129 request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
131 - const: smmpm
133 The standard Smmpm extension for M-mode pointer masking as
135 of riscv-j-extension.
137 - const: smnpm
139 The standard Smnpm extension for next-mode pointer masking as
141 of riscv-j-extension.
143 - const: smstateen
146 added by other RISC-V extensions in H/S/VS/U/VU modes and as
147 ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
149 - const: ssaia
151 The standard Ssaia supervisor-level extension for the advanced
152 interrupt architecture for supervisor-mode-visible csr and
154 ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
156 - const: sscofpmf
158 The standard Sscofpmf supervisor-level extension for count overflow
159 and mode-based filtering as ratified at commit 01d1df0 ("Add ability
160 to manually trigger workflow. (#2)") of riscv-count-overflow.
162 - const: ssnpm
164 The standard Ssnpm extension for next-mode pointer masking as
166 of riscv-j-extension.
168 - const: sstc
170 The standard Sstc supervisor-level extension for time compare as
172 workflow. (#2)") of riscv-time-compare.
174 - const: svade
176 The standard Svade supervisor-level extension for SW-managed PTE A/D
178 ISA specification.
180 Both Svade and Svadu extensions control the hardware behavior when
182 possible combinations of these extensions in the device tree are:
192 Svadu turned-off at boot time. To use Svadu, supervisor must
195 - const: svadu
197 The standard Svadu supervisor-level extension for hardware updating
199 privileged ISA specification. Please refer to Svade dt-binding
202 - const: svinval
204 The standard Svinval supervisor-level extension for fine-grained
205 address-translation cache invalidation as ratified in the 20191213
206 version of the privileged ISA specification.
208 - const: svnapot
210 The standard Svnapot supervisor-level extensions for napot
212 privileged ISA specification.
214 - const: svpbmt
216 The standard Svpbmt supervisor-level extensions for page-based
218 ISA specification.
220 - const: svvptc
222 The standard Svvptc supervisor-level extension for
223 address-translation cache behaviour with respect to invalid entries
225 riscv-svvptc.
227 - const: zabha
231 riscv-zabha.
233 - const: zacas
235 The Zacas extension for Atomic Compare-and-Swap (CAS) instructions
237 ratified") of the riscv-zacas.
239 - const: zawrs
241 The Zawrs extension for entering a low-power state or for trapping
244 riscv/zawrs") of riscv-isa-manual.
246 - const: zba
248 The standard Zba bit-manipulation extension for address generation
250 request #158 from hirooih/clmul-fix-loop-end-condition") of
251 riscv-bitmanip.
253 - const: zbb
255 The standard Zbb bit-manipulation extension for basic bit-manipulation
257 hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
259 - const: zbc
261 The standard Zbc bit-manipulation extension for carry-less
263 #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
265 - const: zbkb
268 in version 1.0 of RISC-V Cryptography Extensions Volume I
271 - const: zbkc
273 The standard Zbkc carry-less multiply instructions as ratified
274 in version 1.0 of RISC-V Cryptography Extensions Volume I
277 - const: zbkx
280 in version 1.0 of RISC-V Cryptography Extensions Volume I
283 - const: zbs
285 The standard Zbs bit-manipulation extension for single-bit
287 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
289 - const: zca
291 The Zca extension part of Zc* standard extensions for code size
293 RV64 as it contains no instructions") of riscv-code-size-reduction,
294 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
297 - const: zcb
299 The Zcb extension part of Zc* standard extensions for code size
301 RV64 as it contains no instructions") of riscv-code-size-reduction,
302 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
305 - const: zcd
307 The Zcd extension part of Zc* standard extensions for code size
309 RV64 as it contains no instructions") of riscv-code-size-reduction,
310 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
313 - const: zcf
315 The Zcf extension part of Zc* standard extensions for code size
317 RV64 as it contains no instructions") of riscv-code-size-reduction,
318 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
321 - const: zcmop
324 c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual.
326 - const: zfa
330 riscv-isa-manual.
332 - const: zfh
334 The standard Zfh extension for 16-bit half-precision binary
335 floating-point instructions, as ratified in commit 64074bc ("Update
336 version numbers for Zfh/Zfinx") of riscv-isa-manual.
338 - const: zfhmin
341 16-bit half-precision binary floating-point instructions, as ratified
343 riscv-isa-manual.
345 - const: ziccrse
351 - const: zk
354 in version 1.0 of RISC-V Cryptography Extensions Volume I
357 - const: zkn
359 The standard Zkn NIST algorithm suite extensions as ratified in
360 version 1.0 of RISC-V Cryptography Extensions Volume I
363 - const: zknd
366 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
369 - const: zkne
372 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
375 - const: zknh
378 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
381 - const: zkr
384 1.0 of RISC-V Cryptography Extensions Volume I specification.
387 device-tree has been provided.
389 - const: zks
391 The standard Zks ShangMi algorithm suite extensions as ratified in
392 version 1.0 of RISC-V Cryptography Extensions Volume I
395 - const: zksed
398 as ratified in version 1.0 of RISC-V Cryptography Extensions
401 - const: zksh
404 as ratified in version 1.0 of RISC-V Cryptography Extensions
407 - const: zkt
410 in version 1.0 of RISC-V Cryptography Extensions Volume I
413 - const: zicbom
416 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
418 - const: zicbop
420 The standard Zicbop extension for cache-block prefetch instructions
421 as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of
422 riscv-CMOs.
424 - const: zicboz
426 The standard Zicboz extension for cache-block zeroing as ratified
427 in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
429 - const: zicntr
432 ratified in the 20191213 version of the unprivileged ISA
435 - const: zicond
438 conditional-select/move operations as ratified in commit 95cf1f9
439 ("Add changes requested by Ved during signoff") of riscv-zicond.
441 - const: zicsr
445 unprivileged ISA specification.
448 special case read-only CSRs, that were moved into the Zicntr and
449 Zihpm extensions after the ratification of the 20191213 version of
452 - const: zifencei
454 The standard Zifencei extension for instruction-fetch fence, as
455 ratified in the 20191213 version of the unprivileged ISA
458 - const: zihintpause
461 commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
463 - const: zihintntl
465 The standard Zihintntl extension for non-temporal locality hints, as
467 riscv-isa-manual.
469 - const: zihpm
472 ratified in the 20191213 version of the unprivileged ISA
475 - const: zimop
478 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual.
480 - const: ztso
484 riscv-isa-manual.
486 - const: zvbb
488 The standard Zvbb extension for vectored basic bit-manipulation
490 riscv-crypto-spec-vector.adoc") of riscv-crypto.
492 - const: zvbc
496 riscv-crypto-spec-vector.adoc") of riscv-crypto.
498 - const: zve32f
501 in commit 6f702a2 ("Vector extensions are now ratified") of
502 riscv-v-spec.
504 - const: zve32x
507 in commit 6f702a2 ("Vector extensions are now ratified") of
508 riscv-v-spec.
510 - const: zve64d
513 in commit 6f702a2 ("Vector extensions are now ratified") of
514 riscv-v-spec.
516 - const: zve64f
519 in commit 6f702a2 ("Vector extensions are now ratified") of
520 riscv-v-spec.
522 - const: zve64x
525 in commit 6f702a2 ("Vector extensions are now ratified") of
526 riscv-v-spec.
528 - const: zvfh
530 The standard Zvfh extension for vectored half-precision
531 floating-point instructions, as ratified in commit e2ccd05
532 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
534 - const: zvfhmin
536 The standard Zvfhmin extension for vectored minimal half-precision
537 floating-point instructions, as ratified in commit e2ccd05
538 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
540 - const: zvkb
542 The standard Zvkb extension for vector cryptography bit-manipulation
544 riscv-crypto-spec-vector.adoc") of riscv-crypto.
546 - const: zvkg
549 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
550 of riscv-crypto.
552 - const: zvkn
555 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
556 of riscv-crypto.
558 - const: zvknc
562 riscv-crypto-spec-vector.adoc") of riscv-crypto.
564 - const: zvkned
568 riscv-crypto-spec-vector.adoc") of riscv-crypto.
570 - const: zvkng
574 riscv-crypto-spec-vector.adoc") of riscv-crypto.
576 - const: zvknha
578 The standard Zvknha extension for NIST suite: vector SHA-2 secure,
579 hash (SHA-256 only) instructions, as ratified in commit
580 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
582 - const: zvknhb
584 The standard Zvknhb extension for NIST suite: vector SHA-2 secure,
585 hash (SHA-256 and SHA-512) instructions, as ratified in commit
586 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
588 - const: zvks
592 riscv-crypto-spec-vector.adoc") of riscv-crypto.
594 - const: zvksc
598 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
600 - const: zvksed
604 riscv-crypto-spec-vector.adoc") of riscv-crypto.
606 - const: zvksh
610 riscv-crypto-spec-vector.adoc") of riscv-crypto.
612 - const: zvksg
616 riscv-crypto-spec-vector.adoc") of riscv-crypto.
618 - const: zvkt
620 The standard Zvkt extension for vector data-independent execution
622 riscv-crypto-spec-vector.adoc") of riscv-crypto.
624 # vendor extensions, each extension sorted alphanumerically under the
628 - const: xandespmu
633 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
635 # T-HEAD
636 - const: xtheadvector
638 The T-HEAD specific 0.7.1 vector implementation as written in
639 …https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/…
643 - if:
650 - if:
655 - contains:
657 - contains:
660 - if:
665 - contains:
667 - contains:
670 - if:
679 - if:
681 riscv,isa-extensions:
684 riscv,isa-base:
689 riscv,isa-extensions: