1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright (C) 2024 Yangyu Chen <[email protected]> 4 */ 5 6/dts-v1/; 7/ { 8 #address-cells = <2>; 9 #size-cells = <2>; 10 model = "SpacemiT K1"; 11 compatible = "spacemit,k1"; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 timebase-frequency = <24000000>; 17 18 cpu-map { 19 cluster0 { 20 core0 { 21 cpu = <&cpu_0>; 22 }; 23 core1 { 24 cpu = <&cpu_1>; 25 }; 26 core2 { 27 cpu = <&cpu_2>; 28 }; 29 core3 { 30 cpu = <&cpu_3>; 31 }; 32 }; 33 34 cluster1 { 35 core0 { 36 cpu = <&cpu_4>; 37 }; 38 core1 { 39 cpu = <&cpu_5>; 40 }; 41 core2 { 42 cpu = <&cpu_6>; 43 }; 44 core3 { 45 cpu = <&cpu_7>; 46 }; 47 }; 48 }; 49 50 cpu_0: cpu@0 { 51 compatible = "spacemit,x60", "riscv"; 52 device_type = "cpu"; 53 reg = <0>; 54 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 55 riscv,isa-base = "rv64i"; 56 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 57 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 58 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 59 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 60 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 61 riscv,cbom-block-size = <64>; 62 riscv,cbop-block-size = <64>; 63 riscv,cboz-block-size = <64>; 64 i-cache-block-size = <64>; 65 i-cache-size = <32768>; 66 i-cache-sets = <128>; 67 d-cache-block-size = <64>; 68 d-cache-size = <32768>; 69 d-cache-sets = <128>; 70 next-level-cache = <&cluster0_l2_cache>; 71 mmu-type = "riscv,sv39"; 72 73 cpu0_intc: interrupt-controller { 74 compatible = "riscv,cpu-intc"; 75 interrupt-controller; 76 #interrupt-cells = <1>; 77 }; 78 }; 79 80 cpu_1: cpu@1 { 81 compatible = "spacemit,x60", "riscv"; 82 device_type = "cpu"; 83 reg = <1>; 84 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 85 riscv,isa-base = "rv64i"; 86 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 87 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 88 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 89 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 90 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 91 riscv,cbom-block-size = <64>; 92 riscv,cbop-block-size = <64>; 93 riscv,cboz-block-size = <64>; 94 i-cache-block-size = <64>; 95 i-cache-size = <32768>; 96 i-cache-sets = <128>; 97 d-cache-block-size = <64>; 98 d-cache-size = <32768>; 99 d-cache-sets = <128>; 100 next-level-cache = <&cluster0_l2_cache>; 101 mmu-type = "riscv,sv39"; 102 103 cpu1_intc: interrupt-controller { 104 compatible = "riscv,cpu-intc"; 105 interrupt-controller; 106 #interrupt-cells = <1>; 107 }; 108 }; 109 110 cpu_2: cpu@2 { 111 compatible = "spacemit,x60", "riscv"; 112 device_type = "cpu"; 113 reg = <2>; 114 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 115 riscv,isa-base = "rv64i"; 116 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 117 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 118 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 119 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 120 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 121 riscv,cbom-block-size = <64>; 122 riscv,cbop-block-size = <64>; 123 riscv,cboz-block-size = <64>; 124 i-cache-block-size = <64>; 125 i-cache-size = <32768>; 126 i-cache-sets = <128>; 127 d-cache-block-size = <64>; 128 d-cache-size = <32768>; 129 d-cache-sets = <128>; 130 next-level-cache = <&cluster0_l2_cache>; 131 mmu-type = "riscv,sv39"; 132 133 cpu2_intc: interrupt-controller { 134 compatible = "riscv,cpu-intc"; 135 interrupt-controller; 136 #interrupt-cells = <1>; 137 }; 138 }; 139 140 cpu_3: cpu@3 { 141 compatible = "spacemit,x60", "riscv"; 142 device_type = "cpu"; 143 reg = <3>; 144 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 145 riscv,isa-base = "rv64i"; 146 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 147 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 148 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 149 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 150 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 151 riscv,cbom-block-size = <64>; 152 riscv,cbop-block-size = <64>; 153 riscv,cboz-block-size = <64>; 154 i-cache-block-size = <64>; 155 i-cache-size = <32768>; 156 i-cache-sets = <128>; 157 d-cache-block-size = <64>; 158 d-cache-size = <32768>; 159 d-cache-sets = <128>; 160 next-level-cache = <&cluster0_l2_cache>; 161 mmu-type = "riscv,sv39"; 162 163 cpu3_intc: interrupt-controller { 164 compatible = "riscv,cpu-intc"; 165 interrupt-controller; 166 #interrupt-cells = <1>; 167 }; 168 }; 169 170 cpu_4: cpu@4 { 171 compatible = "spacemit,x60", "riscv"; 172 device_type = "cpu"; 173 reg = <4>; 174 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 175 riscv,isa-base = "rv64i"; 176 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 177 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 178 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 179 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 180 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 181 riscv,cbom-block-size = <64>; 182 riscv,cbop-block-size = <64>; 183 riscv,cboz-block-size = <64>; 184 i-cache-block-size = <64>; 185 i-cache-size = <32768>; 186 i-cache-sets = <128>; 187 d-cache-block-size = <64>; 188 d-cache-size = <32768>; 189 d-cache-sets = <128>; 190 next-level-cache = <&cluster1_l2_cache>; 191 mmu-type = "riscv,sv39"; 192 193 cpu4_intc: interrupt-controller { 194 compatible = "riscv,cpu-intc"; 195 interrupt-controller; 196 #interrupt-cells = <1>; 197 }; 198 }; 199 200 cpu_5: cpu@5 { 201 compatible = "spacemit,x60", "riscv"; 202 device_type = "cpu"; 203 reg = <5>; 204 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 205 riscv,isa-base = "rv64i"; 206 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 207 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 208 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 209 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 210 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 211 riscv,cbom-block-size = <64>; 212 riscv,cbop-block-size = <64>; 213 riscv,cboz-block-size = <64>; 214 i-cache-block-size = <64>; 215 i-cache-size = <32768>; 216 i-cache-sets = <128>; 217 d-cache-block-size = <64>; 218 d-cache-size = <32768>; 219 d-cache-sets = <128>; 220 next-level-cache = <&cluster1_l2_cache>; 221 mmu-type = "riscv,sv39"; 222 223 cpu5_intc: interrupt-controller { 224 compatible = "riscv,cpu-intc"; 225 interrupt-controller; 226 #interrupt-cells = <1>; 227 }; 228 }; 229 230 cpu_6: cpu@6 { 231 compatible = "spacemit,x60", "riscv"; 232 device_type = "cpu"; 233 reg = <6>; 234 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 235 riscv,isa-base = "rv64i"; 236 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 237 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 238 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 239 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 240 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 241 riscv,cbom-block-size = <64>; 242 riscv,cbop-block-size = <64>; 243 riscv,cboz-block-size = <64>; 244 i-cache-block-size = <64>; 245 i-cache-size = <32768>; 246 i-cache-sets = <128>; 247 d-cache-block-size = <64>; 248 d-cache-size = <32768>; 249 d-cache-sets = <128>; 250 next-level-cache = <&cluster1_l2_cache>; 251 mmu-type = "riscv,sv39"; 252 253 cpu6_intc: interrupt-controller { 254 compatible = "riscv,cpu-intc"; 255 interrupt-controller; 256 #interrupt-cells = <1>; 257 }; 258 }; 259 260 cpu_7: cpu@7 { 261 compatible = "spacemit,x60", "riscv"; 262 device_type = "cpu"; 263 reg = <7>; 264 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 265 riscv,isa-base = "rv64i"; 266 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 267 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 268 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 269 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 270 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 271 riscv,cbom-block-size = <64>; 272 riscv,cbop-block-size = <64>; 273 riscv,cboz-block-size = <64>; 274 i-cache-block-size = <64>; 275 i-cache-size = <32768>; 276 i-cache-sets = <128>; 277 d-cache-block-size = <64>; 278 d-cache-size = <32768>; 279 d-cache-sets = <128>; 280 next-level-cache = <&cluster1_l2_cache>; 281 mmu-type = "riscv,sv39"; 282 283 cpu7_intc: interrupt-controller { 284 compatible = "riscv,cpu-intc"; 285 interrupt-controller; 286 #interrupt-cells = <1>; 287 }; 288 }; 289 290 cluster0_l2_cache: l2-cache0 { 291 compatible = "cache"; 292 cache-block-size = <64>; 293 cache-level = <2>; 294 cache-size = <524288>; 295 cache-sets = <512>; 296 cache-unified; 297 }; 298 299 cluster1_l2_cache: l2-cache1 { 300 compatible = "cache"; 301 cache-block-size = <64>; 302 cache-level = <2>; 303 cache-size = <524288>; 304 cache-sets = <512>; 305 cache-unified; 306 }; 307 }; 308 309 soc { 310 compatible = "simple-bus"; 311 interrupt-parent = <&plic>; 312 #address-cells = <2>; 313 #size-cells = <2>; 314 dma-noncoherent; 315 ranges; 316 317 uart0: serial@d4017000 { 318 compatible = "spacemit,k1-uart", "intel,xscale-uart"; 319 reg = <0x0 0xd4017000 0x0 0x100>; 320 interrupts = <42>; 321 clock-frequency = <14857000>; 322 reg-shift = <2>; 323 reg-io-width = <4>; 324 status = "disabled"; 325 }; 326 327 uart2: serial@d4017100 { 328 compatible = "spacemit,k1-uart", "intel,xscale-uart"; 329 reg = <0x0 0xd4017100 0x0 0x100>; 330 interrupts = <44>; 331 clock-frequency = <14857000>; 332 reg-shift = <2>; 333 reg-io-width = <4>; 334 status = "disabled"; 335 }; 336 337 uart3: serial@d4017200 { 338 compatible = "spacemit,k1-uart", "intel,xscale-uart"; 339 reg = <0x0 0xd4017200 0x0 0x100>; 340 interrupts = <45>; 341 clock-frequency = <14857000>; 342 reg-shift = <2>; 343 reg-io-width = <4>; 344 status = "disabled"; 345 }; 346 347 uart4: serial@d4017300 { 348 compatible = "spacemit,k1-uart", "intel,xscale-uart"; 349 reg = <0x0 0xd4017300 0x0 0x100>; 350 interrupts = <46>; 351 clock-frequency = <14857000>; 352 reg-shift = <2>; 353 reg-io-width = <4>; 354 status = "disabled"; 355 }; 356 357 uart5: serial@d4017400 { 358 compatible = "spacemit,k1-uart", "intel,xscale-uart"; 359 reg = <0x0 0xd4017400 0x0 0x100>; 360 interrupts = <47>; 361 clock-frequency = <14857000>; 362 reg-shift = <2>; 363 reg-io-width = <4>; 364 status = "disabled"; 365 }; 366 367 uart6: serial@d4017500 { 368 compatible = "spacemit,k1-uart", "intel,xscale-uart"; 369 reg = <0x0 0xd4017500 0x0 0x100>; 370 interrupts = <48>; 371 clock-frequency = <14857000>; 372 reg-shift = <2>; 373 reg-io-width = <4>; 374 status = "disabled"; 375 }; 376 377 uart7: serial@d4017600 { 378 compatible = "spacemit,k1-uart", "intel,xscale-uart"; 379 reg = <0x0 0xd4017600 0x0 0x100>; 380 interrupts = <49>; 381 clock-frequency = <14857000>; 382 reg-shift = <2>; 383 reg-io-width = <4>; 384 status = "disabled"; 385 }; 386 387 uart8: serial@d4017700 { 388 compatible = "spacemit,k1-uart", "intel,xscale-uart"; 389 reg = <0x0 0xd4017700 0x0 0x100>; 390 interrupts = <50>; 391 clock-frequency = <14857000>; 392 reg-shift = <2>; 393 reg-io-width = <4>; 394 status = "disabled"; 395 }; 396 397 uart9: serial@d4017800 { 398 compatible = "spacemit,k1-uart", "intel,xscale-uart"; 399 reg = <0x0 0xd4017800 0x0 0x100>; 400 interrupts = <51>; 401 clock-frequency = <14857000>; 402 reg-shift = <2>; 403 reg-io-width = <4>; 404 status = "disabled"; 405 }; 406 407 pinctrl: pinctrl@d401e000 { 408 compatible = "spacemit,k1-pinctrl"; 409 reg = <0x0 0xd401e000 0x0 0x400>; 410 }; 411 412 plic: interrupt-controller@e0000000 { 413 compatible = "spacemit,k1-plic", "sifive,plic-1.0.0"; 414 reg = <0x0 0xe0000000 0x0 0x4000000>; 415 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, 416 <&cpu1_intc 11>, <&cpu1_intc 9>, 417 <&cpu2_intc 11>, <&cpu2_intc 9>, 418 <&cpu3_intc 11>, <&cpu3_intc 9>, 419 <&cpu4_intc 11>, <&cpu4_intc 9>, 420 <&cpu5_intc 11>, <&cpu5_intc 9>, 421 <&cpu6_intc 11>, <&cpu6_intc 9>, 422 <&cpu7_intc 11>, <&cpu7_intc 9>; 423 interrupt-controller; 424 #address-cells = <0>; 425 #interrupt-cells = <1>; 426 riscv,ndev = <159>; 427 }; 428 429 clint: timer@e4000000 { 430 compatible = "spacemit,k1-clint", "sifive,clint0"; 431 reg = <0x0 0xe4000000 0x0 0x10000>; 432 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 433 <&cpu1_intc 3>, <&cpu1_intc 7>, 434 <&cpu2_intc 3>, <&cpu2_intc 7>, 435 <&cpu3_intc 3>, <&cpu3_intc 7>, 436 <&cpu4_intc 3>, <&cpu4_intc 7>, 437 <&cpu5_intc 3>, <&cpu5_intc 7>, 438 <&cpu6_intc 3>, <&cpu6_intc 7>, 439 <&cpu7_intc 3>, <&cpu7_intc 7>; 440 }; 441 442 sec_uart1: serial@f0612000 { 443 compatible = "spacemit,k1-uart", "intel,xscale-uart"; 444 reg = <0x0 0xf0612000 0x0 0x100>; 445 interrupts = <43>; 446 clock-frequency = <14857000>; 447 reg-shift = <2>; 448 reg-io-width = <4>; 449 status = "reserved"; /* for TEE usage */ 450 }; 451 }; 452}; 453