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/nrf52832-nimble/nordic/cmsis/include/
H A Dcmsis_armcc.h54 \details Returns the content of the Control Register.
66 \details Writes the given value to the Control Register.
78 \details Returns the content of the IPSR Register.
90 \details Returns the content of the APSR Register.
102 \details Returns the content of the xPSR Register.
114 \details Returns the current value of the Process Stack Pointer (PSP).
126 \details Assigns the given value to the Process Stack Pointer (PSP).
138 \details Returns the current value of the Main Stack Pointer (MSP).
150 \details Assigns the given value to the Main Stack Pointer (MSP).
162 \details Returns the current state of the priority mask bit from the Priority Mask Register.
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H A Dcmsis_armcc_V6.h47 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
58 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
69 \details Returns the content of the Control Register.
84 \details Returns the content of the non-secure Control Register when in secure mode.
99 \details Writes the given value to the Control Register.
111 \details Writes the given value to the non-secure Control Register when in secure state.
123 \details Returns the content of the IPSR Register.
138 \details Returns the content of the non-secure IPSR Register when in secure state.
153 \details Returns the content of the APSR Register.
168 \details Returns the content of the non-secure APSR Register when in secure state.
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H A Dcmsis_gcc.h55 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
66 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
77 \details Returns the content of the Control Register.
91 \details Writes the given value to the Control Register.
102 \details Returns the content of the IPSR Register.
116 \details Returns the content of the APSR Register.
130 \details Returns the content of the xPSR Register.
145 \details Returns the current value of the Process Stack Pointer (PSP).
159 \details Assigns the given value to the Process Stack Pointer (PSP).
170 \details Returns the current value of the Main Stack Pointer (MSP).
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H A Dcore_cm7.h1797 \details Sets the priority grouping field using the required unlock sequence.
1820 \details Reads the priority grouping field from the NVIC Interrupt Controller.
1831 \details Enables a device-specific interrupt in the NVIC interrupt controller.
1842 \details Disables a device-specific interrupt in the NVIC interrupt controller.
1853 …\details Reads the pending register in the NVIC and returns the pending bit for the specified inte…
1866 \details Sets the pending bit of an external interrupt.
1877 \details Clears the pending bit of an external interrupt.
1888 \details Reads the active register in NVIC and returns the active bit.
1901 \details Sets the priority of an interrupt.
1921 \details Reads the priority of an interrupt.
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H A Dcore_cm0.h626 \details Enables a device-specific interrupt in the NVIC interrupt controller.
637 \details Disables a device-specific interrupt in the NVIC interrupt controller.
648 …\details Reads the pending register in the NVIC and returns the pending bit for the specified inte…
661 \details Sets the pending bit of an external interrupt.
672 \details Clears the pending bit of an external interrupt.
683 \details Sets the priority of an interrupt.
705 \details Reads the priority of an interrupt.
728 \details Initiates a system reset request to reset the MCU.
760 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
H A Dcore_sc300.h1397 \details Sets the priority grouping field using the required unlock sequence.
1420 \details Reads the priority grouping field from the NVIC Interrupt Controller.
1431 \details Enables a device-specific interrupt in the NVIC interrupt controller.
1442 \details Disables a device-specific interrupt in the NVIC interrupt controller.
1453 …\details Reads the pending register in the NVIC and returns the pending bit for the specified inte…
1466 \details Sets the pending bit of an external interrupt.
1477 \details Clears the pending bit of an external interrupt.
1488 \details Reads the active register in NVIC and returns the active bit.
1501 \details Sets the priority of an interrupt.
1521 \details Reads the priority of an interrupt.
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H A Dcore_cm0plus.h742 \details Enables a device-specific interrupt in the NVIC interrupt controller.
753 \details Disables a device-specific interrupt in the NVIC interrupt controller.
764 …\details Reads the pending register in the NVIC and returns the pending bit for the specified inte…
777 \details Sets the pending bit of an external interrupt.
788 \details Clears the pending bit of an external interrupt.
799 \details Sets the priority of an interrupt.
821 \details Reads the priority of an interrupt.
844 \details Initiates a system reset request to reset the MCU.
876 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
H A Dcore_sc000.h754 \details Enables a device-specific interrupt in the NVIC interrupt controller.
765 \details Disables a device-specific interrupt in the NVIC interrupt controller.
776 …\details Reads the pending register in the NVIC and returns the pending bit for the specified inte…
789 \details Sets the pending bit of an external interrupt.
800 \details Clears the pending bit of an external interrupt.
811 \details Sets the priority of an interrupt.
833 \details Reads the priority of an interrupt.
856 \details Initiates a system reset request to reset the MCU.
888 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
/nrf52832-nimble/rt-thread/libcpu/c-sky/common/
H A Dcsi_core.h45 \details Enables a device-specific interrupt in the NVIC interrupt controller.
51 \details Disables a device-specific interrupt in the NVIC interrupt controller.
58 …\details Reads the pending register in the NVIC and returns the pending bit for the specified inte…
67 \details Sets the pending bit of an external interrupt.
74 \details Clears the pending bit of an external interrupt.
81 …\details Reads the active register in the NVIC and returns the active bit for the device specific …
91 \details Sets the priority of an interrupt.
99 \details Reads the priority of an interrupt.
115 \details Turns on I-Cache
121 \details Turns off I-Cache
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H A Dcsi_reg.h31 \details Enables IRQ interrupts by setting the IE-bit in the PSR.
43 \details Disables IRQ interrupts by clearing the IE-bit in the PSR.
53 \details Returns the content of the PSR Register.
66 \details Writes the given value to the PSR Register.
76 \details Returns the content of the SP Register.
89 \details Writes the given value to the SP Register.
100 \details Returns the content of the VBR Register.
113 \details Writes the given value to the VBR Register.
123 \details Returns the content of the EPC Register.
136 \details Writes the given value to the EPC Register.
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H A Dcsi_instr.h33 \details No Operation does nothing. This instruction can be used for code alignment purposes.
43 …\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of…
52 …\details Wait For Interrupt is a hint instruction that suspends execution until one interrupt occu…
61 …\details Doze For Interrupt is a hint instruction that suspends execution until one interrupt occu…
70 …\details Stop For Interrupt is a hint instruction that suspends execution until one interrupt occu…
79 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
91 \details Acts as a special kind of Data Memory Barrier.
102 \details Ensures the apparent order of the explicit memory operations before
113 \details Reverses the byte order in integer value.
125 \details Reverses the byte order in two unsigned short values.
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H A Dcsi_simd.h30 \details Combine a halfword from one register with a halfword from another register.
48 \details Combine a halfword from one register with a halfword from another register.
65 \details This function saturates a signed value.
86 …\details This function enables you to saturate two signed 16-bit values to a selected unsigned ran…
107 \details This function enables you to perform four 8-bit integer additions,
136 \details This function enables you to perform four unsigned 8-bit integer additions,
165 \details This function performs four 8-bit signed integer additions.
192 \details This function performs four unsigned 8-bit integer additions.
219 \details This function enables you to perform four 8-bit integer subtractions,
248 \details This function enables you to perform four unsigned 8-bit integer subtractions,
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/nrf52832-nimble/rt-thread/libcpu/c-sky/ck802/
H A Dcore_ck802.c14 * GNU General Public License for more details.
77 \details Enables a device-specific interrupt in the NVIC interrupt controller.
90 \details Disables a device-specific interrupt in the NVIC interrupt controller.
100 \details Enables a secure device-specific interrupt in the NVIC interrupt controller.
110 …\details Reads the pending register in the NVIC and returns the pending bit for the specified inte…
122 \details Sets the pending bit of an external interrupt.
132 \details Clears the pending bit of an external interrupt.
142 …\details Reads the wake up register in the NVIC and returns the pending bit for the specified inte…
154 \details Sets the wake up bit of an external interrupt.
164 \details Clears the wake up bit of an external interrupt.
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/nrf52832-nimble/nordic/nrfx/drivers/include/
H A Dnrfx_gpiote.h61 * @details Set hi_accu to true to use IN_EVENT. */
71 * @details Set hi_accu to true to use IN_EVENT. */
81 * @details Set hi_accu to true to use IN_EVENT.*/
91 * @details Set hi_accu to true to use IN_EVENT.
103 * @details Set hi_accu to true to use IN_EVENT.
115 * @details Set hi_accu to true to use IN_EVENT.
143 * @details The task will clear the pin. Therefore, the pin is set initially. */
152 * @details The task will set the pin. Therefore, the pin is cleared initially. */
161 * @details The initial pin state must be provided. */
183 * @details Only static configuration is supported to prevent the shared
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H A Dnrfx_dppi.h54 * @details This function allocates the first unused DPPI channel.
65 * @details This function also disables the chosen channel.
96 * @details This function allocates the first unused DPPI group.
107 * @details This function also disables the chosen group.
H A Dnrfx_ppi.h76 * @details This function allocates the first unused PPI channel.
87 * @details This function also disables the chosen channel.
145 * @details This function allocates the first unused PPI group.
156 * @details This function also disables the chosen group.
H A Dnrfx_nfct.h68 * @details These states are substates of the @ref NRFX_NFCT_STATE_ACTIVATED state.
307 * @details As defined by the NFC Forum Digital Protocol Technical Specification (and ISO 14443-3),
316 * @details See also details in @ref nrfx_nfct_autocolres_enable.
/nrf52832-nimble/nordic/nrfx/hal/
H A Dnrf_nfct.h78 …, /**< NFC error reported. The ERRORSTATUS register contains details on the source of …
79 … /**< NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of …
165 * @details Shows the sleep state during automatic collision resolution
429 * @details The returned value is the last state before the autimatic collision resolution started.
447 * @details This is the minimum value for Frame Delay Timer. It controls the shortest time between
458 * @details This is the minimum value for Frame Delay Timer. It controls the shortest time between
468 * @details This is the maximum value for Frame Delay Timer. It controls the longest time between
480 * @details This is the maximum value for Frame Delay Timer. It controls the longest time between
555 * @details Set the number of TX bits excluding CRC, parity, SoF, and EoF.
620 * @details The automatic collision resolution mechanism as defined in ISO 14443-3 and NFC Forum
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H A Dnrf_ppi.h156 * @details This function enables only one channel.
166 * @details This function disables only one channel.
175 * @details This function checks only one channel.
267 * @details This function adds only one channel to the group.
280 * @details This function adds all specified channels to the group.
293 * @details This function removes only one channel from the group.
305 * @details This function removes all specified channels from the group.
H A Dnrf_clock.h74 * @details Used by LFCLKSRC, LFCLKSTAT, and LFCLKSRCCOPY registers.
127 * @details Used by LFCLKRUN and HFCLKRUN registers.
151 …* @details The NRF_CLOCK_TASK_LFCLKSTOP task cannot be set when the low-frequency clock is not run…
206 * @details This function can be used by the PPI module.
223 * @details This function can be used by the PPI module.
250 * @details This function cannot be called when the low-frequency clock is running.
/nrf52832-nimble/rt-thread/documentation/doxygen/
H A Dmainpage.h41 * For more details, please refer to @ref Kernel
48 * For more details, please refer to @ref SystemInit
/nrf52832-nimble/packages/NimBLE-latest/
H A DLICENSE204 license. For details, see porting/nimble/include/os/queue.h
207 "3-clause BSD" license. For details, see:
216 license. For details, and bundled files see:
/nrf52832-nimble/rt-thread/tools/kconfig-frontends/
H A DINSTALL101 for details on some of the pertinent environment variables.
109 *Note Defining Variables::, for more details.
355 for more details, including other options available for fine-tuning
364 `configure --help' for more details.
/nrf52832-nimble/packages/NimBLE-latest/ext/tinycrypt/include/tinycrypt/
H A Daes.h75 * AES-256 key schedule -- see FIPS 197 for details
106 * schedule -- see FIPS 197 for details
/nrf52832-nimble/rt-thread/components/net/lwip-1.4.1/doc/
H A Dsnmp_agent.txt143 4 The Gory Details
181 /** @todo more gory details */

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