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/aosp_15_r20/external/mesa3d/src/gallium/drivers/iris/
H A Diris_program.c82 const struct brw_wm_prog_data *brw) in iris_apply_brw_wm_prog_data() argument
87 STATIC_ASSERT(ARRAY_SIZE(iris->urb_setup) == ARRAY_SIZE(brw->urb_setup)); in iris_apply_brw_wm_prog_data()
88 STATIC_ASSERT(ARRAY_SIZE(iris->urb_setup_attribs) == ARRAY_SIZE(brw->urb_setup_attribs)); in iris_apply_brw_wm_prog_data()
89 memcpy(iris->urb_setup, brw->urb_setup, sizeof(iris->urb_setup)); in iris_apply_brw_wm_prog_data()
90 memcpy(iris->urb_setup_attribs, brw->urb_setup_attribs, brw->urb_setup_attribs_count); in iris_apply_brw_wm_prog_data()
91 iris->urb_setup_attribs_count = brw->urb_setup_attribs_count; in iris_apply_brw_wm_prog_data()
93 iris->num_varying_inputs = brw->num_varying_inputs; in iris_apply_brw_wm_prog_data()
94 iris->msaa_flags_param = brw->msaa_flags_param; in iris_apply_brw_wm_prog_data()
95 iris->flat_inputs = brw->flat_inputs; in iris_apply_brw_wm_prog_data()
96 iris->inputs = brw->inputs; in iris_apply_brw_wm_prog_data()
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H A Diris_disk_cache.c91 const struct brw_stage_prog_data *brw = shader->brw_prog_data; in iris_disk_cache_store() local
93 assert((brw == NULL) != (elk == NULL)); in iris_disk_cache_store()
120 if (brw) { in iris_disk_cache_store()
143 if (brw) { in iris_disk_cache_store()
144 blob_write_bytes(&blob, brw->relocs, in iris_disk_cache_store()
145 brw->num_relocs * sizeof(struct brw_shader_reloc)); in iris_disk_cache_store()
146 blob_write_bytes(&blob, brw->param, in iris_disk_cache_store()
147 brw->nr_params * sizeof(uint32_t)); in iris_disk_cache_store()
207 const uint32_t prog_data_size = screen->brw ? brw_prog_data_size(stage) in iris_disk_cache_retrieve()
217 struct brw_stage_prog_data *brw = screen->brw ? prog_data : NULL; in iris_disk_cache_retrieve() local
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H A Diris_program_cache.c175 if (screen->brw) { in iris_upload_shader()
186 brw_write_shader_relocs(&screen->brw->isa, shader->map, in iris_upload_shader()
234 *((void **) prog_data_out) = screen->brw ? (void *)shader->brw_prog_data in iris_blorp_lookup_shader()
265 if (screen->brw) { in iris_blorp_upload_shader()
281 *((void **) prog_data_out) = screen->brw ? (void *)shader->brw_prog_data in iris_blorp_upload_shader()
361 screen->brw ? screen->brw->nir_options[MESA_SHADER_COMPUTE] in iris_ensure_indirect_generation_shader()
386 if (screen->brw) { in iris_ensure_indirect_generation_shader()
388 brw_preprocess_nir(screen->brw, nir, &opts); in iris_ensure_indirect_generation_shader()
432 if (screen->brw) { in iris_ensure_indirect_generation_shader()
440 brw_nir_analyze_ubo_ranges(screen->brw, nir, prog_data->base.ubo_ranges); in iris_ensure_indirect_generation_shader()
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/aosp_15_r20/external/mesa3d/docs/relnotes/
H A D24.1.0.rst947 - intel/compiler: Merge intel_disasm.[ch] into corresponding brw files
950 - intel/blorp: Remove brw\_ prefix when not applicable
956 - intel/blorp: Avoid brw types in blorp_priv.h
964 - intel: Remove brw\_ prefix from process debug function
996 - intel/blorp: Move brw specific code to a separate file
1003 - iris: Rename screen->compiler to screen->brw
1010 - intel: Use _brw suffix for genX headers that rely on brw
1017 - intel/brw: Remove assembler tests for Gfx8-
1018 - intel/brw: Remove EU compaction tests for Gfx8-
1019 - intel/brw: Remove EU validation tests for Gfx8-
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H A D24.2.0.rst107 - intel/brw: scoreboarding regression
616 - intel/brw: Don't print IP as part of the dump
617 - intel/brw: Hide register pressure information in dumps
618 - intel/brw: Use \`vNN` instead of \`vgrfNN` when printing instructions
619 - intel/brw: Fix commas when dumping instructions
621 - intel/brw: Track the number of uses of each def in def_analysis
622 - intel/brw: Fix typo in DPAS emission code
623 - intel/brw: Add unit tests for scoreboard handling FIXED_GRF with stride
624 - intel/brw: Make component_size() consistent between VGRF and FIXED_GRF
626 - intel/brw: Print SWSB information when dumping instructions
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H A D24.0.5.rst107 - intel/brw: Clear write_accumulator flag when changing the destination
108 - intel/brw: Use enums for DPAS source regioning
109 - nir: intel/brw: Change the order of sources for nir_dpas_intel
136 - intel/brw: Fix generate_mov_indirect to check has_64bit_int not float
137 - intel/brw: Fix lower_regioning for BROADCAST, MOV_INDIRECT on Q types
H A D24.2.1.rst110 - intel/brw/gfx12.5+: Fix IR of sub-dword atomic LSC operations.
156 - intel/brw: Pass opcode to brw_swsb_encode/decode
157 - intel/brw: Fix Xe2+ SWSB encoding/decoding for DPAS instructions
179 - brw: switch mesh/task URB fence prior to EOT to GPU
248 - brw,elk: Fix opening flags on dumping shader binaries
H A D24.2.3.rst122 - intel/brw: Use NUM_BRW_OPCODES in can_omit_write() check
134 - brw: use a builder of the size of the physical register for uniforms
135 - brw: fix vecN rebuilds
179 - brw: Fix mov cmod propagation when there's int signedness mismatch
H A D24.2.2.rst105 - intel/brw: Drop misguided sign extension attempts in extract_imm()
106 - intel/brw: Fix extract_imm for subregion reads of 64-bit immediates
116 - brw: align spilling offsets to physical register sizes
H A D24.1.5.rst98 - intel/brw: Implement null push constant workaround.
156 - brw: fix uniform rebuild of sources
169 - intel/brw: Use REG_CLASS_COUNT
H A D24.0.4.rst57 - intel/brw: Use helper to create accumulator register
58 - intel/brw: Fix validation of accumulator register
124 - intel/brw: Fix opt_split_sends() to allow for FIXED_GRF send sources
H A D10.6.9.rst37 brw_meta_fast_clear (brw=brw\@entry=0x7fffd4097a08,
/aosp_15_r20/external/mesa3d/src/intel/compiler/
H A Dbrw_fs.h46 namespace brw {
141 namespace brw {
218 void load_subgroup_id(const brw::fs_builder &bld, brw_reg &dest) const;
245 void load_shader_type(const brw::fs_builder &bld, brw_reg &dest) const;
303 void invalidate_analysis(brw::analysis_dependency_class c);
333 brw::simple_allocator alloc;
341 brw_analysis<brw::fs_live_variables, fs_visitor> live_analysis;
342 brw_analysis<brw::register_pressure, fs_visitor> regpressure_analysis;
343 brw_analysis<brw::performance, fs_visitor> performance_analysis;
344 brw_analysis<brw::idom_tree, fs_visitor> idom_analysis;
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H A Dbrw_fs.cpp46 using namespace brw;
1439 brw::register_pressure::register_pressure(const fs_visitor *v) in register_pressure()
1465 brw::register_pressure::~register_pressure() in ~register_pressure()
1471 fs_visitor::invalidate_analysis(brw::analysis_dependency_class c) in invalidate_analysis()
1884 namespace brw { namespace
1886 fetch_payload_reg(const brw::fs_builder &bld, uint8_t regs[2], in fetch_payload_reg()
1894 const brw::fs_builder hbld = bld.exec_all().group(16, 0); in fetch_payload_reg()
1915 fetch_barycentric_reg(const brw::fs_builder &bld, uint8_t regs[2]) in fetch_barycentric_reg()
1923 const brw::fs_builder hbld = bld.exec_all().group(8, 0); in fetch_barycentric_reg()
H A Dbrw_ir_analysis.h28 namespace brw {
125 * brw::analysis_dependency_class specifying the set of IR objects that are
179 invalidate(brw::analysis_dependency_class c) in invalidate()
/aosp_15_r20/external/igt-gpu-tools/assembler/
H A Dbrw_eu_emit.c67 struct intel_context *intel = &p->brw->intel; in gen6_resolve_implied_move()
96 struct intel_context *intel = &p->brw->intel; in gen7_convert_mrf_to_grf()
250 struct brw_context *brw = p->brw; in brw_set_src0() local
251 struct intel_context *intel = &brw->intel; in brw_set_src0()
354 struct brw_context *brw = p->brw; in brw_set_src1() local
355 struct intel_context *intel = &brw->intel; in brw_set_src1()
380 /* It's only BRW that does not support register-indirect addressing on in brw_set_src1()
453 struct intel_context *intel = &p->brw->intel; in brw_set_message_descriptor()
486 struct brw_context *brw = p->brw; in brw_set_math_message() local
487 struct intel_context *intel = &brw->intel; in brw_set_math_message()
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H A Dbrw_eu.c116 if (p->brw->intel.gen >= 6) { in brw_set_compression_control()
159 if (p->brw->intel.gen >= 6) in brw_set_acc_write_control()
182 brw_init_compile(struct brw_context *brw, struct brw_compile *p, void *mem_ctx) in brw_init_compile() argument
186 p->brw = brw; in brw_init_compile()
218 brw_init_compaction_tables(&brw->intel); in brw_init_compile()
234 struct brw_context *brw = p->brw; in brw_dump_compile() local
235 struct intel_context *intel = &brw->intel; in brw_dump_compile()
266 brw_disasm(stdout, insn, p->brw->intel.gen); in brw_dump_compile()
H A Dbrw_eu_compact.c454 struct brw_context *brw = p->brw; in brw_try_compact_instruction() local
455 struct intel_context *intel = &brw->intel; in brw_try_compact_instruction()
670 struct brw_context *brw = p->brw; in brw_compact_instructions() local
671 struct intel_context *intel = &brw->intel; in brw_compact_instructions()
H A Dbrw_context.c41 brw_init_context(struct brw_context *brw, int gen) in brw_init_context() argument
43 return intel_init_context(&brw->intel, gen); in brw_init_context()
/aosp_15_r20/external/mesa3d/src/intel/blorp/
H A Dblorp_brw.c16 const struct brw_compiler *compiler = blorp->compiler->brw; in blorp_nir_options_brw()
26 const struct brw_compiler *compiler = blorp->compiler->brw; in blorp_compile_fs_brw()
69 const struct brw_compiler *compiler = blorp->compiler->brw; in blorp_compile_vs_brw()
122 const struct brw_compiler *compiler = blorp->compiler->brw; in blorp_compile_cs_brw()
266 struct isl_device *isl_dev, const struct brw_compiler *brw, in blorp_init_brw() argument
270 assert(brw); in blorp_init_brw()
272 blorp->compiler->brw = brw; in blorp_init_brw()
/aosp_15_r20/external/deqp/external/vulkancts/data/vulkan/amber/graphicsfuzz/
H A Dindex.txt49 …erse-uniform-condition", "A fragment shader that covers specific BRW code paths" …
57 …imit-from-always-false", "A fragment shader that covers specific BRW code paths" …
69 …oop-index-bitwise-not", "A fragment shader that covers specific BRW code paths" …
113 …vector-global-loop-count", "A fragment shader that covers specific BRW code paths" …
115 …op-min-max-always-zero", "A fragment shader that covers specific BRW code paths" …
116 …lized-matrix-never-chosen", "A fragment shader that covers specific BRW code paths" …
117 …y-after-nested-loops", "A fragment shader that covers specific BRW code paths" …
177 …agcoord-bitwise-not", "A fragment shader that covers specific BRW code paths" …
230 …n-vec2-never-discard", "A fragment shader that covers specific BRW code paths", …
231 …s-called-from-nested-loops", "A fragment shader that covers specific BRW code paths" …
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/aosp_15_r20/external/mesa3d/src/intel/decoder/
H A Dintel_batch_decoder_brw.c23 brw_disassemble_with_errors(ctx->brw, bo.map, 0, ctx->fp); in ctx_disassemble_program_brw()
26 int size = brw_disassemble_find_end(ctx->brw, bo.map, 0); in ctx_disassemble_program_brw()
48 ctx->brw = isa; in intel_batch_decode_ctx_init_brw()
/aosp_15_r20/external/mesa3d/src/intel/tools/
H A Daubinator.c64 struct brw_isa_info brw; variable
103 brw_init_isa_info(&brw, &devinfo); in aubinator_init()
104 intel_batch_decode_ctx_init_brw(&batch_ctx, &brw, &devinfo, outfile, in aubinator_init()
328 fprintf(stderr, "can't parse gen: '%s', expected lpt, brw, g4x, ilk, " in main()
/aosp_15_r20/external/mesa3d/
H A D.mr-label-maker.yml39 'intel/brw': 'intel-brw'
255 '^src/intel/compiler/brw': ['intel-brw']
/aosp_15_r20/external/autotest/server/site_tests/bluetooth_AdapterCLHealth/
H A Dcontrol.cl_sdp_service_browse_test22 TP/SERVER/BRW/BV-01-C
23 TP/SERVER/BRW/BV-02-C

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