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/linux-6.14.4/drivers/pinctrl/renesas/
Dsh_pfc.h1 /* SPDX-License-Identifier: GPL-2.0
12 #include <linux/pinctrl/pinconf-generic.h>
43 const char *name; member
50 .name = #alias, \
56 #define SH_PFC_PIN_GROUP(name) SH_PFC_PIN_GROUP_ALIAS(name, name) argument
62 .name = #_name, \
79 const char *name; member
86 .name = #n, \
92 const char *name; member
99 const char *name; member
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/linux-6.14.4/tools/testing/selftests/gpio/
Dgpio-sim.sh2 # SPDX-License-Identifier: GPL-2.0
6 CONFIGFS_DIR="/sys/kernel/config/gpio-sim"
7 MODULE="gpio-sim"
25 BANK=`basename $FILE`
26 if [ "$BANK" = "live" -o "$BANK" = "dev_name" ]; then
30 LINES=`ls $CONFIGFS_DIR/$CHIP/$BANK/ | grep -E ^line`
33 if [ -e $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog ]; then
34 rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog || \
38 rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE || \
43 rmdir $CONFIGFS_DIR/$CHIP/$BANK
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/linux-6.14.4/drivers/pinctrl/samsung/
Dpinctrl-exynos.c1 // SPDX-License-Identifier: GPL-2.0+
29 #include <linux/soc/samsung/exynos-pmu.h>
30 #include <linux/soc/samsung/exynos-regs-pmu.h>
32 #include "pinctrl-samsung.h"
33 #include "pinctrl-exynos.h"
56 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_mask() local
61 if (bank->eint_mask_offset) in exynos_irq_mask()
62 reg_mask = bank->pctl_offset + bank->eint_mask_offset; in exynos_irq_mask()
64 reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
66 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_mask()
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Dpinctrl-samsung.c1 // SPDX-License-Identifier: GPL-2.0+
3 // pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
32 #include "pinctrl-samsung.h"
42 { "samsung,pin-pud", PINCFG_TYPE_PUD },
43 { "samsung,pin-drv", PINCFG_TYPE_DRV },
44 { "samsung,pin-con-pdn", PINCFG_TYPE_CON_PDN },
45 { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN },
46 { "samsung,pin-val", PINCFG_TYPE_DAT },
53 return pmx->nr_groups; in samsung_get_group_count()
61 return pmx->pin_groups[group].name; in samsung_get_group_name()
[all …]
Dpinctrl-samsung.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
70 * enum pud_index - Possible index values to access the pud_val array.
84 * enum eint_type - possible external interrupt types.
85 * @EINT_TYPE_NONE: bank does not support external interrupts
86 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
87 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
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Dpinctrl-s3c64xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 // S3C64xx specific support for pinctrl-samsung driver.
7 // Based on pinctrl-exynos.c, please see the file for original copyrights.
24 #include "pinctrl-samsung.h"
106 .name = id \
116 .eint_mask = (1 << (pins)) - 1, \
118 .name = id \
130 .name = id \
140 .eint_mask = (1 << (pins)) - 1, \
142 .name = id \
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/linux-6.14.4/drivers/crypto/intel/qat/qat_common/
Dadf_transport_debug.c1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
15 struct adf_etr_ring_data *ring = sfile->private; in adf_ring_start()
21 if (*pos >= (ADF_SIZE_TO_RING_SIZE_IN_BYTES(ring->ring_size) / in adf_ring_start()
22 ADF_MSG_SIZE_TO_BYTES(ring->msg_size))) in adf_ring_start()
25 return ring->base_addr + in adf_ring_start()
26 (ADF_MSG_SIZE_TO_BYTES(ring->msg_size) * (*pos)++); in adf_ring_start()
31 struct adf_etr_ring_data *ring = sfile->private; in adf_ring_next()
33 if (*pos >= (ADF_SIZE_TO_RING_SIZE_IN_BYTES(ring->ring_size) / in adf_ring_next()
34 ADF_MSG_SIZE_TO_BYTES(ring->msg_size))) in adf_ring_next()
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/linux-6.14.4/drivers/pinctrl/nuvoton/
Dpinctrl-ma35.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Shan-Chun Hung <[email protected]>
24 #include "pinctrl-ma35.h"
59 /* GPIO pull-up and pull-down selection control */
66 * The MA35_GP_REG_INTEN bits 0 ~ 15 control low-level or falling edge trigger,
67 * while bits 16 ~ 31 control high-level or rising edge trigger.
84 /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
85 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
86 #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
102 const char *name; member
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/linux-6.14.4/drivers/pinctrl/
Dpinctrl-equilibrium.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pinctrl/pinconf-generic.h>
19 #include "pinctrl-equilibrium.h"
21 #define PIN_NAME_FMT "io-%d"
32 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
33 writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR); in eqbr_gpio_disable_irq()
34 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
45 gc->direction_input(gc, offset); in eqbr_gpio_enable_irq()
47 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_enable_irq()
48 writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET); in eqbr_gpio_enable_irq()
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Dpinctrl-st.c1 // SPDX-License-Identifier: GPL-2.0-only
64 * There are two registers cfg0 and cfg1 in this style for each bank.
65 * Each field in this register is 8 bit corresponding to 8 pins in the bank.
100 * (direction, retime-type, retime-clk, retime-delay)
102 * +----------------+
103 *[31:28]| reserved-3 |
104 * +----------------+-------------
106 * +----------------+ v
108 * +----------------+ ^
110 * +----------------+-------------
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Dpinctrl-rockchip.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2020-2024 Rockchip Electronics Co., Ltd.
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
244 * @offset: if initialized to -1 it will be autocalculated, by specifying
277 * @offset: if initialized to -1 it will be autocalculated, by specifying
290 * @dev: the pinctrl device bind to the bank
291 * @reg_base: register base of the gpio bank
293 * @clk: clock of the gpio bank
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Dpinctrl-at91-pio4.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/pinctrl/at91.h>
21 #include <linux/pinctrl/pinconf-generic.h>
28 #include "pinctrl-utils.h"
34 * designed the pin id into this bank.
80 * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
82 * @last_bank_count: number of lines in the last bank (can be less than
93 const char *name; member
101 unsigned int bank; member
107 * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
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Dpinctrl-eyeq5.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * pull-down, pull-up, drive strength and muxing.
10 * that is pin-dependent. Functions are declared statically in this driver.
15 * We use eq5p_ as prefix, as-in "EyeQ5 Pinctrl", but way shorter.
33 #include <linux/pinctrl/pinconf-generic.h>
39 #include "pinctrl-utils.h"
74 * Comments to the right of each pin are the "signal name" in the datasheet.
77 /* Bank A */
110 /* Bank B */
137 /* Bank A */
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Dpinctrl-microchip-sgpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
138 addr->port = pin / priv->bitcount; in sgpio_pin_to_addr()
139 addr->bit = pin % priv->bitcount; in sgpio_pin_to_addr()
144 return bit + port * priv->bitcount; in sgpio_addr_to_pin()
149 return (priv->properties->regoff[rno] + off) * in sgpio_get_addr()
150 regmap_get_reg_stride(priv->regs); in sgpio_get_addr()
159 ret = regmap_read(priv->regs, addr, &val); in sgpio_readl()
171 ret = regmap_write(priv->regs, addr, val); in sgpio_writel()
181 ret = regmap_update_bits(priv->regs, addr, clear | set, set); in sgpio_clrsetbits()
187 int width = priv->bitcount - 1; in sgpio_configure_bitstream()
[all …]
/linux-6.14.4/arch/arm/mach-omap2/
Dpowerdomain.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
6 * Copyright (C) 2007-2011 Nokia Corporation
65 static struct powerdomain *_pwrdm_lookup(const char *name) in _pwrdm_lookup() argument
72 if (!strcmp(name, temp_pwrdm->name)) { in _pwrdm_lookup()
82 * _pwrdm_register - register a powerdomain
86 * -EINVAL if given a null pointer, -EEXIST if a powerdomain is
87 * already registered by the provided name, or 0 upon success.
94 if (!pwrdm || !pwrdm->name) in _pwrdm_register()
95 return -EINVAL; in _pwrdm_register()
[all …]
/linux-6.14.4/drivers/gpio/
Dgpio-sim.c1 // SPDX-License-Identifier: GPL-2.0-or-later
74 guard(mutex)(&chip->lock); in gpio_sim_apply_pull()
76 if (test_bit(offset, chip->request_map) && in gpio_sim_apply_pull()
77 test_bit(offset, chip->direction_map)) { in gpio_sim_apply_pull()
78 if (value == !!test_bit(offset, chip->value_map)) in gpio_sim_apply_pull()
82 * This is fine - it just means, nobody is listening in gpio_sim_apply_pull()
87 irq = irq_find_mapping(chip->irq_sim, offset); in gpio_sim_apply_pull()
104 if (!test_bit(offset, chip->request_map) || in gpio_sim_apply_pull()
105 test_bit(offset, chip->direction_map)) in gpio_sim_apply_pull()
106 __assign_bit(offset, chip->value_map, value); in gpio_sim_apply_pull()
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Dgpio-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
22 #include <linux/pinctrl/pinconf-generic.h>
27 #include "../pinctrl/pinctrl-rockchip.h"
31 * Bits [31:24] - Major Version
32 * Bits [23:16] - Minor Version
33 * Bits [15:0] - Revision Number
83 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, in rockchip_gpio_writel() argument
86 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel()
88 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_writel()
94 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank, in rockchip_gpio_readl() argument
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/linux-6.14.4/drivers/pinctrl/sunxi/
Dpinctrl-sunxi.h6 * Maxime Ripard <maxime.ripard@free-electrons.com>
32 #define SUNXI_PINCTRL_PIN(bank, pin) \ argument
33 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
58 #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
62 #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
66 #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
123 const char *name; member
147 const char *name; member
153 const char *name; member
200 .name = _name, \
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/linux-6.14.4/drivers/uio/
Duio_fsl_elbc_gpcm.c1 // SPDX-License-Identifier: GPL-2.0
9 using the general purpose chip-select mode (GPCM).
17 compatible = "fsl,elbc-gpcm-uio";
19 elbc-gpcm-br = <0xff810800>;
20 elbc-gpcm-or = <0xffff09f7>;
21 interrupt-parent = <&mpic>;
25 netx5152,init-win0-offset = <0x0>;
29 Only the entries reg (to identify bank) and elbc-gpcm-* (initial BR/OR
31 are optional (as well as any type-specific options such as
32 netx5152,init-win0-offset). As long as no interrupt handler is needed,
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/linux-6.14.4/drivers/pinctrl/stm32/
Dpinctrl-stm32.c1 // SPDX-License-Identifier: GPL-2.0
29 #include <linux/pinctrl/pinconf-generic.h>
36 #include "../pinctrl-utils.h"
37 #include "pinctrl-stm32.h"
83 const char *name; member
150 return function - 1; in stm32_gpio_get_alt()
158 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, in stm32_gpio_backup_value() argument
161 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); in stm32_gpio_backup_value()
162 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; in stm32_gpio_backup_value()
165 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_mode() argument
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/linux-6.14.4/arch/x86/kernel/cpu/mce/
Damd.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (c) 2005-2016 Advanced Micro Devices, Inc.
5 * Written by Jacob Shin - AMD, Inc.
81 u8 sysfs_id; /* Value used for sysfs name. */
131 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) in smca_get_bank_type() argument
135 if (bank >= MAX_NR_BANKS) in smca_get_bank_type()
138 b = &per_cpu(smca_banks, cpu)[bank]; in smca_get_bank_type()
139 if (!b->hwid) in smca_get_bank_type()
142 return b->hwid->bank_type; in smca_get_bank_type()
212 * So to define a unique name for each bank, we use a temp c-string to append
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/linux-6.14.4/drivers/pinctrl/meson/
Dpinctrl-meson.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a
14 * The AO bank is special because it belongs to the Always-On power
15 * domain which can't be powered off; the bank also uses a set of
31 * For the pull and GPIO configuration every bank uses a contiguous
46 #include <linux/pinctrl/pinconf-generic.h>
56 #include "../pinctrl-utils.h"
57 #include "pinctrl-meson.h"
64 * meson_get_bank() - find the bank containing a given pin
68 * @bank: the found bank
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Dpinctrl-meson.h1 /* SPDX-License-Identifier: GPL-2.0-only */
20 * struct meson_pmx_group - a pinmux group
22 * @name: group name
31 const char *name; member
38 * struct meson_pmx_func - a pinmux function
40 * @name: function name
45 const char *name; member
51 * struct meson_reg_desc - a register descriptor
57 * pull-enable, direction, etc. for a single pin
65 * enum meson_reg_type - type of registers encoded in @meson_reg_desc
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-st.txt3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
26 Second type has a dedicated interrupt per gpio bank.
28 [irqN]----> [gpio-bank (n)]
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/linux-6.14.4/drivers/gpu/drm/amd/amdgpu/
Damdgpu_aca.c31 typedef int bank_handler_t(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type…
55 INIT_LIST_HEAD(&banks->list); in aca_banks_init()
58 static int aca_banks_add_bank(struct aca_banks *banks, struct aca_bank *bank) in aca_banks_add_bank() argument
62 if (!bank) in aca_banks_add_bank()
63 return -EINVAL; in aca_banks_add_bank()
67 return -ENOMEM; in aca_banks_add_bank()
69 memcpy(&node->bank, bank, sizeof(*bank)); in aca_banks_add_bank()
71 INIT_LIST_HEAD(&node->node); in aca_banks_add_bank()
72 list_add_tail(&node->node, &banks->list); in aca_banks_add_bank()
74 banks->nr_banks++; in aca_banks_add_bank()
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