Lines Matching +full:bank +full:- +full:name
1 // SPDX-License-Identifier: GPL-2.0-only
3 * (c) 2005-2016 Advanced Micro Devices, Inc.
5 * Written by Jacob Shin - AMD, Inc.
81 u8 sysfs_id; /* Value used for sysfs name. */
131 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) in smca_get_bank_type() argument
135 if (bank >= MAX_NR_BANKS) in smca_get_bank_type()
138 b = &per_cpu(smca_banks, cpu)[bank]; in smca_get_bank_type()
139 if (!b->hwid) in smca_get_bank_type()
142 return b->hwid->bank_type; in smca_get_bank_type()
212 * So to define a unique name for each bank, we use a temp c-string to append
213 * the MCA_IPID[InstanceId] to type's name in get_name().
216 * is greater than 8 plus 1 (for underscore) plus length of longest type name.
222 /* This block's number within its bank. */
224 /* MCA bank number that contains this block. */
225 unsigned int bank; member
226 /* CPU which controls this block's MCA bank. */
232 /* Bank can generate an interrupt. */
238 /* List of threshold blocks within this block's MCA bank. */
267 static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) in smca_set_misc_banks_map() argument
273 * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4). in smca_set_misc_banks_map()
275 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) in smca_set_misc_banks_map()
281 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high)) in smca_set_misc_banks_map()
285 per_cpu(smca_misc_banks_map, cpu) |= BIT_ULL(bank); in smca_set_misc_banks_map()
289 static void smca_configure(unsigned int bank, unsigned int cpu) in smca_configure() argument
295 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); in smca_configure()
302 * bank. It also means that the OS will configure deferred in smca_configure()
311 * SMCA sets the Deferred Error Interrupt type per bank. in smca_configure()
324 this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8)); in smca_configure()
329 smca_set_misc_banks_map(bank, cpu); in smca_configure()
331 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { in smca_configure()
332 pr_warn("Failed to read MCA_IPID for bank %d\n", bank); in smca_configure()
342 if (hwid_mcatype == s_hwid->hwid_mcatype) { in smca_configure()
343 this_cpu_ptr(smca_banks)[bank].hwid = s_hwid; in smca_configure()
344 this_cpu_ptr(smca_banks)[bank].id = low; in smca_configure()
345 this_cpu_ptr(smca_banks)[bank].sysfs_id = bank_counts[s_hwid->bank_type]++; in smca_configure()
361 switch (b->address) { in bank4_names()
373 WARN(1, "Funny MSR: 0x%08x\n", b->address); in bank4_names()
379 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) in lvt_interrupt_supported() argument
382 * bank 4 supports APIC LVT interrupts implicitly since forever. in lvt_interrupt_supported()
384 if (bank == 4) in lvt_interrupt_supported()
389 * bank can generate APIC LVT interrupts in lvt_interrupt_supported()
400 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, in lvt_off_valid()
401 b->bank, b->block, b->address, hi, lo); in lvt_off_valid()
415 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", in lvt_off_valid()
416 b->cpu, apic, b->bank, b->block, b->address, hi, lo); in lvt_off_valid()
423 /* Reprogram MCx_MISC MSR behind this threshold bank. */
430 if (!this_cpu_read(threshold_banks) && !tr->set_lvt_off) in threshold_restart_bank()
433 rdmsr(tr->b->address, lo, hi); in threshold_restart_bank()
435 if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) in threshold_restart_bank()
436 tr->reset = 1; /* limit cannot be lower than err count */ in threshold_restart_bank()
438 if (tr->reset) { /* reset err count and overflow bit */ in threshold_restart_bank()
441 (THRESHOLD_MAX - tr->b->threshold_limit); in threshold_restart_bank()
442 } else if (tr->old_limit) { /* change limit w/o reset */ in threshold_restart_bank()
444 (tr->old_limit - tr->b->threshold_limit); in threshold_restart_bank()
453 if (!tr->b->interrupt_capable) in threshold_restart_bank()
456 if (tr->set_lvt_off) { in threshold_restart_bank()
457 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { in threshold_restart_bank()
460 hi |= tr->lvt_off << 20; in threshold_restart_bank()
464 if (tr->b->interrupt_enable) in threshold_restart_bank()
470 wrmsr(tr->b->address, lo, hi); in threshold_restart_bank()
481 b->threshold_limit = THRESHOLD_MAX; in mce_threshold_block_init()
506 int def_offset = -1, def_new; in deferred_error_interrupt_enable()
529 static u32 smca_get_block_address(unsigned int bank, unsigned int block, in smca_get_block_address() argument
533 return MSR_AMD64_SMCA_MCx_MISC(bank); in smca_get_block_address()
535 if (!(per_cpu(smca_misc_banks_map, cpu) & BIT_ULL(bank))) in smca_get_block_address()
538 return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); in smca_get_block_address()
542 unsigned int bank, unsigned int block, in get_block_address() argument
547 if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS)) in get_block_address()
551 return smca_get_block_address(bank, block, cpu); in get_block_address()
556 addr = mca_msr_reg(bank, MCA_MISC); in get_block_address()
570 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, in prepare_threshold_block() argument
579 per_cpu(bank_map, cpu) |= BIT_ULL(bank); in prepare_threshold_block()
583 b.bank = bank; in prepare_threshold_block()
586 b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); in prepare_threshold_block()
618 enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank); in amd_filter_mce()
621 /* See Family 17h Models 10h-2Fh Erratum #1114. */ in amd_filter_mce()
622 if (c->x86 == 0x17 && in amd_filter_mce()
623 c->x86_model >= 0x10 && c->x86_model <= 0x2F && in amd_filter_mce()
624 bank_type == SMCA_IF && XEC(m->status, 0x3f) == 10) in amd_filter_mce()
628 if (c->x86 < 0x17) { in amd_filter_mce()
629 if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5) in amd_filter_mce()
638 * - MC4_MISC thresholding is not supported on Family 0x15.
639 * - Prevent possible spurious interrupts from the IF bank on Family 0x17
640 * Models 0x10-0x2F due to Erratum #1114.
642 static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank) in disable_err_thresholding() argument
649 if (c->x86 == 0x15 && bank == 4) { in disable_err_thresholding()
653 } else if (c->x86 == 0x17 && in disable_err_thresholding()
654 (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) { in disable_err_thresholding()
656 if (smca_get_bank_type(smp_processor_id(), bank) != SMCA_IF) in disable_err_thresholding()
659 msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank); in disable_err_thresholding()
684 unsigned int bank, block, cpu = smp_processor_id(); in mce_amd_feature_init() local
686 int offset = -1; in mce_amd_feature_init()
689 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { in mce_amd_feature_init()
691 smca_configure(bank, cpu); in mce_amd_feature_init()
693 disable_err_thresholding(c, bank); in mce_amd_feature_init()
696 address = get_block_address(address, low, high, bank, block, cpu); in mce_amd_feature_init()
710 offset = prepare_threshold_block(bank, block, address, offset, high); in mce_amd_feature_init()
719 * DRAM ECC errors are reported in the Northbridge (bank 4) with
724 return m->bank == 4 && XEC(m->status, 0x1f) == 8; in legacy_mce_is_memory_error()
735 if (XEC(m->status, 0x3f)) in smca_mce_is_memory_error()
738 bank_type = smca_get_bank_type(m->extcpu, m->bank); in smca_mce_is_memory_error()
760 * northbridge (bank 4).
765 * a) Reported in legacy bank 4 with extended error code (XEC) 8.
766 * b) MCA_STATUS[43] is *not* defined as poison in legacy bank 4. Therefore,
777 else if (m->bank == 4) in amd_mce_usable_address()
781 /* Check poison bit for all other bank types. */ in amd_mce_usable_address()
782 if (m->status & MCI_STATUS_POISON) in amd_mce_usable_address()
789 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) in __log_error() argument
796 m->status = status; in __log_error()
797 m->misc = misc; in __log_error()
798 m->bank = bank; in __log_error()
799 m->tsc = rdtsc(); in __log_error()
801 if (m->status & MCI_STATUS_ADDRV) { in __log_error()
802 m->addr = addr; in __log_error()
808 rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m->ipid); in __log_error()
810 if (m->status & MCI_STATUS_SYNDV) { in __log_error()
811 rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m->synd); in __log_error()
812 rdmsrl(MSR_AMD64_SMCA_MCx_SYND1(bank), err.vendor.amd.synd1); in __log_error()
813 rdmsrl(MSR_AMD64_SMCA_MCx_SYND2(bank), err.vendor.amd.synd2); in __log_error()
833 _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) in _log_error_bank() argument
844 __log_error(bank, status, addr, misc); in _log_error_bank()
851 static bool _log_error_deferred(unsigned int bank, u32 misc) in _log_error_deferred() argument
853 if (!_log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS), in _log_error_deferred()
854 mca_msr_reg(bank, MCA_ADDR), misc)) in _log_error_deferred()
858 * Non-SMCA systems don't have MCA_DESTAT/MCA_DEADDR registers. in _log_error_deferred()
865 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); in _log_error_deferred()
872 * 1) Non-SMCA systems check MCA_STATUS and log error if found.
878 static void log_error_deferred(unsigned int bank) in log_error_deferred() argument
880 if (_log_error_deferred(bank, 0)) in log_error_deferred()
887 _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), in log_error_deferred()
888 MSR_AMD64_SMCA_MCx_DEADDR(bank), 0); in log_error_deferred()
894 unsigned int bank; in amd_deferred_error_interrupt() local
896 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) in amd_deferred_error_interrupt()
897 log_error_deferred(bank); in amd_deferred_error_interrupt()
900 static void log_error_thresholding(unsigned int bank, u64 misc) in log_error_thresholding() argument
902 _log_error_deferred(bank, misc); in log_error_thresholding()
913 if (rdmsr_safe(block->address, &low, &high)) in log_and_reset_block()
920 log_error_thresholding(block->bank, ((u64)high << 32) | low); in log_and_reset_block()
936 unsigned int bank, cpu = smp_processor_id(); in amd_threshold_interrupt() local
939 * Validate that the threshold bank has been initialized already. The in amd_threshold_interrupt()
946 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { in amd_threshold_interrupt()
947 if (!(per_cpu(bank_map, cpu) & BIT_ULL(bank))) in amd_threshold_interrupt()
950 first_block = bp[bank]->blocks; in amd_threshold_interrupt()
959 list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) in amd_threshold_interrupt()
974 #define SHOW_FIELDS(name) \ argument
975 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \
977 return sprintf(buf, "%lu\n", (unsigned long) b->name); \
988 if (!b->interrupt_capable) in SHOW_FIELDS()
989 return -EINVAL; in SHOW_FIELDS()
992 return -EINVAL; in SHOW_FIELDS()
994 b->interrupt_enable = !!new; in SHOW_FIELDS()
999 if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1)) in SHOW_FIELDS()
1000 return -ENODEV; in SHOW_FIELDS()
1012 return -EINVAL; in store_threshold_limit()
1020 tr.old_limit = b->threshold_limit; in store_threshold_limit()
1021 b->threshold_limit = new; in store_threshold_limit()
1024 if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1)) in store_threshold_limit()
1025 return -ENODEV; in store_threshold_limit()
1035 if (rdmsr_on_cpu(b->cpu, b->address, &lo, &hi)) in show_error_count()
1036 return -ENODEV; in show_error_count()
1038 return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - in show_error_count()
1039 (THRESHOLD_MAX - b->threshold_limit))); in show_error_count()
1043 .attr = {.name = __stringify(error_count), .mode = 0444 },
1049 .attr = {.name = __stringify(val), .mode = 0644 }, \
1074 ret = a->show ? a->show(b, buf) : -EIO; in show()
1086 ret = a->store ? a->store(b, buf, count) : -EIO; in store()
1104 static const char *get_name(unsigned int cpu, unsigned int bank, struct threshold_block *b) in get_name() argument
1109 if (b && bank == 4) in get_name()
1112 return th_names[bank]; in get_name()
1115 bank_type = smca_get_bank_type(cpu, bank); in get_name()
1120 if (b->block < ARRAY_SIZE(smca_umc_block_names)) in get_name()
1121 return smca_umc_block_names[b->block]; in get_name()
1130 per_cpu(smca_banks, cpu)[bank].sysfs_id); in get_name()
1135 unsigned int bank, unsigned int block, in allocate_threshold_blocks() argument
1142 if ((bank >= this_cpu_read(mce_num_banks)) || (block >= NR_BLOCKS)) in allocate_threshold_blocks()
1161 return -ENOMEM; in allocate_threshold_blocks()
1163 b->block = block; in allocate_threshold_blocks()
1164 b->bank = bank; in allocate_threshold_blocks()
1165 b->cpu = cpu; in allocate_threshold_blocks()
1166 b->address = address; in allocate_threshold_blocks()
1167 b->interrupt_enable = 0; in allocate_threshold_blocks()
1168 b->interrupt_capable = lvt_interrupt_supported(bank, high); in allocate_threshold_blocks()
1169 b->threshold_limit = THRESHOLD_MAX; in allocate_threshold_blocks()
1171 if (b->interrupt_capable) { in allocate_threshold_blocks()
1173 b->interrupt_enable = 1; in allocate_threshold_blocks()
1178 INIT_LIST_HEAD(&b->miscj); in allocate_threshold_blocks()
1181 if (tb->blocks) in allocate_threshold_blocks()
1182 list_add(&b->miscj, &tb->blocks->miscj); in allocate_threshold_blocks()
1184 tb->blocks = b; in allocate_threshold_blocks()
1186 err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(cpu, bank, b)); in allocate_threshold_blocks()
1190 address = get_block_address(address, low, high, bank, ++block, cpu); in allocate_threshold_blocks()
1194 err = allocate_threshold_blocks(cpu, tb, bank, block, address); in allocate_threshold_blocks()
1199 kobject_uevent(&b->kobj, KOBJ_ADD); in allocate_threshold_blocks()
1205 list_del(&b->miscj); in allocate_threshold_blocks()
1206 kobject_put(&b->kobj); in allocate_threshold_blocks()
1212 unsigned int bank) in threshold_create_bank() argument
1216 const char *name = get_name(cpu, bank, NULL); in threshold_create_bank() local
1220 return -ENODEV; in threshold_create_bank()
1224 err = -ENOMEM; in threshold_create_bank()
1228 /* Associate the bank with the per-CPU MCE device */ in threshold_create_bank()
1229 b->kobj = kobject_create_and_add(name, &dev->kobj); in threshold_create_bank()
1230 if (!b->kobj) { in threshold_create_bank()
1231 err = -EINVAL; in threshold_create_bank()
1235 err = allocate_threshold_blocks(cpu, b, bank, 0, mca_msr_reg(bank, MCA_MISC)); in threshold_create_bank()
1239 bp[bank] = b; in threshold_create_bank()
1243 kobject_put(b->kobj); in threshold_create_bank()
1255 static void deallocate_threshold_blocks(struct threshold_bank *bank) in deallocate_threshold_blocks() argument
1259 list_for_each_entry_safe(pos, tmp, &bank->blocks->miscj, miscj) { in deallocate_threshold_blocks()
1260 list_del(&pos->miscj); in deallocate_threshold_blocks()
1261 kobject_put(&pos->kobj); in deallocate_threshold_blocks()
1264 kobject_put(&bank->blocks->kobj); in deallocate_threshold_blocks()
1267 static void threshold_remove_bank(struct threshold_bank *bank) in threshold_remove_bank() argument
1269 if (!bank->blocks) in threshold_remove_bank()
1272 deallocate_threshold_blocks(bank); in threshold_remove_bank()
1275 kobject_put(bank->kobj); in threshold_remove_bank()
1276 kfree(bank); in threshold_remove_bank()
1281 unsigned int bank, numbanks = this_cpu_read(mce_num_banks); in __threshold_remove_device() local
1283 for (bank = 0; bank < numbanks; bank++) { in __threshold_remove_device()
1284 if (!bp[bank]) in __threshold_remove_device()
1287 threshold_remove_bank(bp[bank]); in __threshold_remove_device()
1288 bp[bank] = NULL; in __threshold_remove_device()
1311 * mce_threshold_create_device - Create the per-CPU MCE threshold device
1323 unsigned int numbanks, bank; in mce_threshold_create_device() local
1337 return -ENOMEM; in mce_threshold_create_device()
1339 for (bank = 0; bank < numbanks; ++bank) { in mce_threshold_create_device()
1340 if (!(this_cpu_read(bank_map) & BIT_ULL(bank))) in mce_threshold_create_device()
1342 err = threshold_create_bank(bp, cpu, bank); in mce_threshold_create_device()