Lines Matching +full:bank +full:- +full:name
1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pinctrl/pinconf-generic.h>
19 #include "pinctrl-equilibrium.h"
21 #define PIN_NAME_FMT "io-%d"
32 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
33 writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR); in eqbr_gpio_disable_irq()
34 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
45 gc->direction_input(gc, offset); in eqbr_gpio_enable_irq()
47 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_enable_irq()
48 writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET); in eqbr_gpio_enable_irq()
49 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_gpio_enable_irq()
59 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_ack_irq()
60 writel(BIT(offset), gctrl->membase + GPIO_IRNCR); in eqbr_gpio_ack_irq()
61 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_gpio_ack_irq()
85 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_irq_type_cfg()
86 eqbr_cfg_bit(gctrl->membase + GPIO_IRNCFG, offset, type->trig_type); in eqbr_irq_type_cfg()
87 eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR1, offset, type->trig_type); in eqbr_irq_type_cfg()
88 eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR0, offset, type->logic_type); in eqbr_irq_type_cfg()
89 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_irq_type_cfg()
138 return -EINVAL; in eqbr_gpio_set_irq_type()
158 pins = readl(gctrl->membase + GPIO_IRNCR); in eqbr_irq_handler()
160 for_each_set_bit(offset, &pins, gc->ngpio) in eqbr_irq_handler()
161 generic_handle_domain_irq(gc->irq.domain, offset); in eqbr_irq_handler()
167 .name = "gpio_irq",
182 gc = &gctrl->chip; in gpiochip_setup()
183 gc->label = gctrl->name; in gpiochip_setup()
184 gc->fwnode = gctrl->fwnode; in gpiochip_setup()
186 if (!fwnode_property_read_bool(gctrl->fwnode, "interrupt-controller")) { in gpiochip_setup()
188 gctrl->name); in gpiochip_setup()
192 girq = &gctrl->chip.irq; in gpiochip_setup()
194 girq->parent_handler = eqbr_irq_handler; in gpiochip_setup()
195 girq->num_parents = 1; in gpiochip_setup()
196 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), GFP_KERNEL); in gpiochip_setup()
197 if (!girq->parents) in gpiochip_setup()
198 return -ENOMEM; in gpiochip_setup()
200 girq->default_type = IRQ_TYPE_NONE; in gpiochip_setup()
201 girq->handler = handle_bad_irq; in gpiochip_setup()
202 girq->parents[0] = gctrl->virq; in gpiochip_setup()
209 struct device *dev = drvdata->dev; in gpiolib_reg()
215 for (i = 0; i < drvdata->nr_gpio_ctrls; i++) { in gpiolib_reg()
216 gctrl = drvdata->gpio_ctrls + i; in gpiolib_reg()
217 np = to_of_node(gctrl->fwnode); in gpiolib_reg()
219 gctrl->name = devm_kasprintf(dev, GFP_KERNEL, "gpiochip%d", i); in gpiolib_reg()
220 if (!gctrl->name) in gpiolib_reg()
221 return -ENOMEM; in gpiolib_reg()
225 return -ENXIO; in gpiolib_reg()
228 gctrl->membase = devm_ioremap_resource(dev, &res); in gpiolib_reg()
229 if (IS_ERR(gctrl->membase)) in gpiolib_reg()
230 return PTR_ERR(gctrl->membase); in gpiolib_reg()
232 gctrl->virq = irq_of_parse_and_map(np, 0); in gpiolib_reg()
233 if (!gctrl->virq) { in gpiolib_reg()
235 gctrl->name); in gpiolib_reg()
236 return -ENXIO; in gpiolib_reg()
238 raw_spin_lock_init(&gctrl->lock); in gpiolib_reg()
240 ret = bgpio_init(&gctrl->chip, dev, gctrl->bank->nr_pins / 8, in gpiolib_reg()
241 gctrl->membase + GPIO_IN, in gpiolib_reg()
242 gctrl->membase + GPIO_OUTSET, in gpiolib_reg()
243 gctrl->membase + GPIO_OUTCLR, in gpiolib_reg()
244 gctrl->membase + GPIO_DIR, in gpiolib_reg()
255 ret = devm_gpiochip_add_data(dev, &gctrl->chip, gctrl); in gpiolib_reg()
266 struct eqbr_pin_bank *bank; in find_pinbank_via_pin() local
269 for (i = 0; i < pctl->nr_banks; i++) { in find_pinbank_via_pin()
270 bank = &pctl->pin_banks[i]; in find_pinbank_via_pin()
271 if (pin >= bank->pin_base && in find_pinbank_via_pin()
272 (pin - bank->pin_base) < bank->nr_pins) in find_pinbank_via_pin()
273 return bank; in find_pinbank_via_pin()
290 struct eqbr_pin_bank *bank; in eqbr_set_pin_mux() local
295 bank = find_pinbank_via_pin(pctl, pin); in eqbr_set_pin_mux()
296 if (!bank) { in eqbr_set_pin_mux()
297 dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin); in eqbr_set_pin_mux()
298 return -ENODEV; in eqbr_set_pin_mux()
300 mem = bank->membase; in eqbr_set_pin_mux()
301 offset = pin - bank->pin_base; in eqbr_set_pin_mux()
303 if (!(bank->aval_pinmap & BIT(offset))) { in eqbr_set_pin_mux()
304 dev_err(pctl->dev, in eqbr_set_pin_mux()
306 pin, bank->pin_base, bank->aval_pinmap); in eqbr_set_pin_mux()
307 return -ENODEV; in eqbr_set_pin_mux()
310 raw_spin_lock_irqsave(&pctl->lock, flags); in eqbr_set_pin_mux()
312 raw_spin_unlock_irqrestore(&pctl->lock, flags); in eqbr_set_pin_mux()
327 return -EINVAL; in eqbr_pinmux_set_mux()
331 return -EINVAL; in eqbr_pinmux_set_mux()
333 pinmux = grp->data; in eqbr_pinmux_set_mux()
334 for (i = 0; i < grp->grp.npins; i++) in eqbr_pinmux_set_mux()
335 eqbr_set_pin_mux(pctl, pinmux[i], grp->grp.pins[i]); in eqbr_pinmux_set_mux()
360 unsigned int idx = offset / DRV_CUR_PINS; /* 0-15, 16-31 per register*/ in get_drv_cur()
368 struct eqbr_pin_bank *bank) in get_gpio_ctrls_via_bank() argument
372 for (i = 0; i < pctl->nr_gpio_ctrls; i++) { in get_gpio_ctrls_via_bank()
373 if (pctl->gpio_ctrls[i].bank == bank) in get_gpio_ctrls_via_bank()
374 return &pctl->gpio_ctrls[i]; in get_gpio_ctrls_via_bank()
386 struct eqbr_pin_bank *bank; in eqbr_pinconf_get() local
392 bank = find_pinbank_via_pin(pctl, pin); in eqbr_pinconf_get()
393 if (!bank) { in eqbr_pinconf_get()
394 dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin); in eqbr_pinconf_get()
395 return -ENODEV; in eqbr_pinconf_get()
397 mem = bank->membase; in eqbr_pinconf_get()
398 offset = pin - bank->pin_base; in eqbr_pinconf_get()
400 if (!(bank->aval_pinmap & BIT(offset))) { in eqbr_pinconf_get()
401 dev_err(pctl->dev, in eqbr_pinconf_get()
403 pin, bank->pin_base, bank->aval_pinmap); in eqbr_pinconf_get()
404 return -ENODEV; in eqbr_pinconf_get()
407 raw_spin_lock_irqsave(&pctl->lock, flags); in eqbr_pinconf_get()
425 gctrl = get_gpio_ctrls_via_bank(pctl, bank); in eqbr_pinconf_get()
427 dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n", in eqbr_pinconf_get()
428 bank->pin_base, pin); in eqbr_pinconf_get()
429 raw_spin_unlock_irqrestore(&pctl->lock, flags); in eqbr_pinconf_get()
430 return -ENODEV; in eqbr_pinconf_get()
432 val = !!(readl(gctrl->membase + GPIO_DIR) & BIT(offset)); in eqbr_pinconf_get()
435 raw_spin_unlock_irqrestore(&pctl->lock, flags); in eqbr_pinconf_get()
436 return -ENOTSUPP; in eqbr_pinconf_get()
438 raw_spin_unlock_irqrestore(&pctl->lock, flags); in eqbr_pinconf_get()
450 struct eqbr_pin_bank *bank; in eqbr_pinconf_set() local
462 bank = find_pinbank_via_pin(pctl, pin); in eqbr_pinconf_set()
463 if (!bank) { in eqbr_pinconf_set()
464 dev_err(pctl->dev, in eqbr_pinconf_set()
465 "Couldn't find pin bank for pin %u\n", pin); in eqbr_pinconf_set()
466 return -ENODEV; in eqbr_pinconf_set()
468 mem = bank->membase; in eqbr_pinconf_set()
469 offset = pin - bank->pin_base; in eqbr_pinconf_set()
494 gctrl = get_gpio_ctrls_via_bank(pctl, bank); in eqbr_pinconf_set()
496 dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n", in eqbr_pinconf_set()
497 bank->pin_base, pin); in eqbr_pinconf_set()
498 return -ENODEV; in eqbr_pinconf_set()
500 gc = &gctrl->chip; in eqbr_pinconf_set()
501 gc->direction_output(gc, offset, 0); in eqbr_pinconf_set()
504 return -ENOTSUPP; in eqbr_pinconf_set()
507 raw_spin_lock_irqsave(&pctl->lock, flags); in eqbr_pinconf_set()
511 raw_spin_unlock_irqrestore(&pctl->lock, flags); in eqbr_pinconf_set()
530 return -ENOTSUPP; in eqbr_pinconf_group_get()
533 return -ENOTSUPP; in eqbr_pinconf_group_get()
569 static bool is_func_exist(struct pinfunction *funcs, const char *name, in is_func_exist() argument
578 if (funcs[i].name && !strcmp(funcs[i].name, name)) { in is_func_exist()
590 struct device_node *node = dev->of_node; in funcs_utils()
606 (char *)prop->value); in funcs_utils()
618 funcs[i].name = fn_name; in funcs_utils()
632 groups[j] = prop->value; in funcs_utils()
637 return -EINVAL; in funcs_utils()
647 struct device *dev = drvdata->dev; in eqbr_build_functions()
658 return -ENOMEM; in eqbr_build_functions()
675 return -ENOMEM; in eqbr_build_functions()
685 if (funcs[i].name == NULL) in eqbr_build_functions()
688 ret = pinmux_generic_add_function(drvdata->pctl_dev, in eqbr_build_functions()
689 funcs[i].name, in eqbr_build_functions()
695 funcs[i].name); in eqbr_build_functions()
705 struct device *dev = drvdata->dev; in eqbr_build_groups()
706 struct device_node *node = dev->of_node; in eqbr_build_groups()
719 dev_err(dev, "No pins in the group: %s\n", prop->name); in eqbr_build_groups()
722 grp->npins = err; in eqbr_build_groups()
723 grp->name = prop->value; in eqbr_build_groups()
724 pins = devm_kcalloc(dev, grp->npins, sizeof(*pins), GFP_KERNEL); in eqbr_build_groups()
726 return -ENOMEM; in eqbr_build_groups()
728 grp->pins = pins; in eqbr_build_groups()
730 pinmux = devm_kcalloc(dev, grp->npins, sizeof(*pinmux), GFP_KERNEL); in eqbr_build_groups()
732 return -ENOMEM; in eqbr_build_groups()
734 for (j = 0; j < grp->npins; j++) { in eqbr_build_groups()
737 grp->name); in eqbr_build_groups()
738 return -EINVAL; in eqbr_build_groups()
740 if (pin_id >= drvdata->pctl_desc.npins) { in eqbr_build_groups()
742 grp->name, j, pin_id); in eqbr_build_groups()
743 return -EINVAL; in eqbr_build_groups()
748 grp->name); in eqbr_build_groups()
749 return -EINVAL; in eqbr_build_groups()
754 err = pinctrl_generic_add_group(drvdata->pctl_dev, in eqbr_build_groups()
755 grp->name, grp->pins, grp->npins, in eqbr_build_groups()
758 dev_err(dev, "Failed to register group %s\n", grp->name); in eqbr_build_groups()
777 dev = drvdata->dev; in pinctrl_reg()
778 pctl_desc = &drvdata->pctl_desc; in pinctrl_reg()
779 pctl_desc->name = "eqbr-pinctrl"; in pinctrl_reg()
780 pctl_desc->owner = THIS_MODULE; in pinctrl_reg()
781 pctl_desc->pctlops = &eqbr_pctl_ops; in pinctrl_reg()
782 pctl_desc->pmxops = &eqbr_pinmux_ops; in pinctrl_reg()
783 pctl_desc->confops = &eqbr_pinconf_ops; in pinctrl_reg()
784 raw_spin_lock_init(&drvdata->lock); in pinctrl_reg()
786 for (i = 0, nr_pins = 0; i < drvdata->nr_banks; i++) in pinctrl_reg()
787 nr_pins += drvdata->pin_banks[i].nr_pins; in pinctrl_reg()
791 return -ENOMEM; in pinctrl_reg()
794 return -ENOMEM; in pinctrl_reg()
799 pdesc[i].name = pin_names; in pinctrl_reg()
802 pctl_desc->pins = pdesc; in pinctrl_reg()
803 pctl_desc->npins = nr_pins; in pinctrl_reg()
807 &drvdata->pctl_dev); in pinctrl_reg()
823 return pinctrl_enable(drvdata->pctl_dev); in pinctrl_reg()
828 struct eqbr_pin_bank *bank, unsigned int id) in pinbank_init() argument
830 struct device *dev = drvdata->dev; in pinbank_init()
834 bank->membase = drvdata->membase + id * PAD_REG_OFF; in pinbank_init()
836 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &spec); in pinbank_init()
838 dev_err(dev, "gpio-range not available!\n"); in pinbank_init()
842 bank->pin_base = spec.args[1]; in pinbank_init()
843 bank->nr_pins = spec.args[2]; in pinbank_init()
845 bank->aval_pinmap = readl(bank->membase + REG_AVAIL); in pinbank_init()
846 bank->id = id; in pinbank_init()
849 id, bank->membase, bank->pin_base, in pinbank_init()
850 bank->nr_pins, bank->aval_pinmap); in pinbank_init()
857 struct device *dev = drvdata->dev; in pinbank_probe()
863 /* Count gpio bank number */ in pinbank_probe()
871 dev_err(dev, "NO pin bank available!\n"); in pinbank_probe()
872 return -ENODEV; in pinbank_probe()
875 /* Count pin bank number and gpio controller number */ in pinbank_probe()
878 return -ENOMEM; in pinbank_probe()
882 return -ENOMEM; in pinbank_probe()
886 /* Initialize Pin bank */ in pinbank_probe()
895 gctrls[i].bank = banks + i; in pinbank_probe()
899 drvdata->pin_banks = banks; in pinbank_probe()
900 drvdata->nr_banks = nr_gpio; in pinbank_probe()
901 drvdata->gpio_ctrls = gctrls; in pinbank_probe()
902 drvdata->nr_gpio_ctrls = nr_gpio; in pinbank_probe()
910 struct device *dev = &pdev->dev; in eqbr_pinctrl_probe()
915 return -ENOMEM; in eqbr_pinctrl_probe()
917 drvdata->dev = dev; in eqbr_pinctrl_probe()
919 drvdata->membase = devm_platform_ioremap_resource(pdev, 0); in eqbr_pinctrl_probe()
920 if (IS_ERR(drvdata->membase)) in eqbr_pinctrl_probe()
921 return PTR_ERR(drvdata->membase); in eqbr_pinctrl_probe()
940 { .compatible = "intel,lgm-io" },
948 .name = "eqbr-pinctrl",