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/linux-6.14.4/drivers/net/ethernet/freescale/dpaa2/
Ddpkg.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2013-2015 Freescale Semiconductor Inc.
16 * DPKG_NUM_OF_MASKS - Number of masks per key extraction
21 * DPKG_MAX_NUM_OF_EXTRACTS - Number of extractions per key profile
26 * enum dpkg_extract_from_hdr_type - Selecting extraction by header types
34 DPKG_FULL_FIELD = 2
38 * enum dpkg_extract_type - Enumeration for selecting extraction type
41 * @DPKG_EXTRACT_FROM_PARSE: Extract from parser-result;
52 * struct dpkg_mask - A structure for defining a single extraction mask
64 #define NH_FLD_ETH_DA BIT(0)
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/linux-6.14.4/drivers/net/dsa/microchip/
Dksz9477_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2024 Microchip Technology Inc.
14 /* 0 - Operation */
43 #define SW_GIGABIT_ABLE BIT(6)
44 #define SW_REDUNDANCY_ABLE BIT(5)
45 #define SW_AVB_ABLE BIT(4)
63 #define SW_QW_ABLE BIT(5)
69 #define LUE_INT BIT(31)
70 #define TRIG_TS_INT BIT(30)
71 #define APB_TIMEOUT_INT BIT(29)
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Dksz8_reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
20 #define KS_PRIO_S 2
27 #define KSZ8863_GLOBAL_SOFTWARE_RESET BIT(4)
28 #define KSZ8863_PCS_RESET BIT(0)
31 #define KSZ88X3_PORT3_RMII_CLK_INTERNAL BIT(3)
35 #define SW_NEW_BACKOFF BIT(7)
36 #define SW_GLOBAL_RESET BIT(6)
37 #define SW_FLUSH_DYN_MAC_TABLE BIT(5)
38 #define SW_FLUSH_STA_MAC_TABLE BIT(4)
39 #define SW_LINK_AUTO_AGING BIT(0)
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Dlan937x_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2019-2024 Microchip Technology Inc.
10 /* 0 - Operation */
13 #define SW_PHY_REG_BLOCK BIT(7)
14 #define SW_FAST_MODE BIT(3)
15 #define SW_FAST_MODE_OVERRIDE BIT(2)
20 #define LUE_INT BIT(31)
21 #define TRIG_TS_INT BIT(30)
22 #define APB_TIMEOUT_INT BIT(29)
23 #define OVER_TEMP_INT BIT(28)
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/linux-6.14.4/include/linux/mfd/abx500/
Dab8500-sysctrl.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) ST-Ericsson SA 2010
83 #define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
84 #define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1)
85 #define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2)
86 #define AB8500_TURNONSTATUS_RTCALARM BIT(3)
87 #define AB8500_TURNONSTATUS_MAINCHDET BIT(4)
88 #define AB8500_TURNONSTATUS_VBUSDET BIT(5)
89 #define AB8500_TURNONSTATUS_USBIDDETECT BIT(6)
91 #define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0)
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/linux-6.14.4/drivers/crypto/intel/qat/qat_common/
Dadf_gen4_ras.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #define ADF_GEN4_ERRSOU0_BIT BIT(0)
18 #define ADF_GEN4_ERRSOU1_HIAEUNCERRLOG_CPP0_BIT BIT(0)
19 #define ADF_GEN4_ERRSOU1_HICPPAGENTCMDPARERRLOG_BIT BIT(1)
20 #define ADF_GEN4_ERRSOU1_RIMEM_PARERR_STS_BIT BIT(2)
21 #define ADF_GEN4_ERRSOU1_TIMEM_PARERR_STS_BIT BIT(3)
22 #define ADF_GEN4_ERRSOU1_RIMISCSTS_BIT BIT(4)
51 * BIT(0) - BIT(3) - ri_iosf_pdata_rxq[0:3] parity error
52 * BIT(4) - ri_tlq_phdr parity error
53 * BIT(5) - ri_tlq_pdata parity error
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/linux-6.14.4/drivers/comedi/drivers/
Dni_tio_internal.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * COMEDI - Linux Control and Measurement Device Interface
17 #define GI_ARM BIT(0)
18 #define GI_SAVE_TRACE BIT(1)
19 #define GI_LOAD BIT(2)
20 #define GI_DISARM BIT(4)
23 #define GI_WRITE_SWITCH BIT(7)
24 #define GI_SYNC_GATE BIT(8)
25 #define GI_LITTLE_BIG_ENDIAN BIT(9)
26 #define GI_BANK_SWITCH_START BIT(10)
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/linux-6.14.4/include/linux/mfd/
Dlp873x.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
68 #define LP873X_BUCK0_CTRL_1_BUCK0_FPWM BIT(3)
69 #define LP873X_BUCK0_CTRL_1_BUCK0_RDIS_EN BIT(2)
70 #define LP873X_BUCK0_CTRL_1_BUCK0_EN_PIN_CTRL BIT(1)
71 #define LP873X_BUCK0_CTRL_1_BUCK0_EN BIT(0)
76 #define LP873X_BUCK1_CTRL_1_BUCK1_FPWM BIT(3)
77 #define LP873X_BUCK1_CTRL_1_BUCK1_RDIS_EN BIT(2)
78 #define LP873X_BUCK1_CTRL_1_BUCK1_EN_PIN_CTRL BIT(1)
79 #define LP873X_BUCK1_CTRL_1_BUCK1_EN BIT(0)
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Dlp87565.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
97 #define LP87565_BUCK_CTRL_1_EN BIT(7)
98 #define LP87565_BUCK_CTRL_1_EN_PIN_CTRL BIT(6)
101 #define LP87565_BUCK_CTRL_1_ROOF_FLOOR_EN BIT(3)
102 #define LP87565_BUCK_CTRL_1_RDIS_EN BIT(2)
103 #define LP87565_BUCK_CTRL_1_FPWM BIT(1)
105 #define LP87565_BUCK_CTRL_1_FPWM_MP_0_2 BIT(0)
119 #define LP87565_RESET_SW_RESET BIT(0)
121 #define LP87565_CONFIG_DOUBLE_DELAY BIT(7)
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Dtps65219.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/
82 #define TPS65219_REG_INT_BUCK_3_POS 2
98 #define TPS65219_BUCKS_UV_THR_SEL_MASK BIT(6)
99 #define TPS65219_BUCKS_BW_SEL_MASK BIT(7)
101 #define TPS65219_LDOS_BYP_CONFIG_MASK BIT(LDO_BYP_SHIFT)
102 #define TPS65219_LDOS_LSW_CONFIG_MASK BIT(7)
104 #define TPS65219_ENABLE_BUCK1_EN_MASK BIT(0)
105 #define TPS65219_ENABLE_BUCK2_EN_MASK BIT(1)
106 #define TPS65219_ENABLE_BUCK3_EN_MASK BIT(2)
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Drohm-bd71815.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 * Author: yanglsh@embest-tech.com
32 /* LDO for Low-Power State Retention */
236 #define BD71815_BUCK_PWM_FIXED BIT(4)
237 #define BD71815_BUCK_SNVS_ON BIT(3)
238 #define BD71815_BUCK_RUN_ON BIT(2)
239 #define BD71815_BUCK_LPSR_ON BIT(1)
240 #define BD71815_BUCK_SUSP_ON BIT(0)
243 #define BD71815_BUCK_DVSSEL BIT(7)
244 #define BD71815_BUCK_STBY_DVS BIT(6)
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Dtps6594.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
248 #define TPS6594_BIT_BUCK_EN BIT(0)
249 #define TPS6594_BIT_BUCK_FPWM BIT(1)
250 #define TPS6594_BIT_BUCK_FPWM_MP BIT(2)
251 #define TPS6594_BIT_BUCK_VSEL BIT(3)
252 #define TPS6594_BIT_BUCK_VMON_EN BIT(4)
253 #define TPS6594_BIT_BUCK_PLDN BIT(5)
254 #define TPS6594_BIT_BUCK_RV_SEL BIT(7)
257 #define TPS6594_MASK_BUCK_SLEW_RATE GENMASK(2, 0)
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/linux-6.14.4/sound/soc/codecs/
Dsma1307.h1 /* SPDX-License-Identifier: GPL-2.0-or-later
2 * sma1307.h -- sma1307 ALSA SoC Audio driver
7 * it under the terms of the GNU General Public License version 2 as
232 /* SMA1307 Registers Bit Fields */
234 #define SMA1307_POWER_MASK BIT(0)
236 #define SMA1307_POWER_ON BIT(0)
239 #define SMA1307_RESET_MASK BIT(1)
240 #define SMA1307_RESET_ON BIT(1)
243 #define SMA1307_LEFTPOL_MASK BIT(3)
245 #define SMA1307_HIGH_FIRST_CH BIT(3)
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/linux-6.14.4/drivers/hid/intel-thc-hid/intel-thc/
Dintel-thc-hw.h1 /* SPDX-License-Identifier: GPL-2.0 */
88 /* Touch Device Interrupt Cause register Format Configuration Register 2 */
139 /* THC Read PRD Base Address Low for the 2nd RXDMA */
141 /* THC Read PRD Base Address High for the 2nd RXDMA */
143 /* THC Read PRD Control for the 2nd RXDMA */
145 /* THC Read DMA Control for the 2nd RXDMA */
147 /* THC Read Interrupt Status for the 2nd RXDMA */
149 /* THC Read DMA Error Register for the 2nd RXDMA */
151 /* Touch Sequencer GuC Tail Offset Address Low for the 2nd RXDMA */
153 /* Touch Sequencer GuC Tail Offset Address High for the 2nd RXDMA */
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/linux-6.14.4/drivers/media/i2c/
Dtda1997x_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Page 0x00 - General Control */
128 #define DETECT_UTIL BIT(7) /* utility of HDMI level */
129 #define DETECT_HPD BIT(6) /* HPD of HDMI level */
130 #define DETECT_5V_SEL BIT(2) /* 5V present on selected input */
131 #define DETECT_5V_B BIT(1) /* 5V present on input B */
132 #define DETECT_5V_A BIT(0) /* 5V present on input A */
135 #define INPUT_SEL_RST_FMT BIT(7) /* 1=reset format measurement */
136 #define INPUT_SEL_RST_VDP BIT(2) /* 1=reset video data path */
137 #define INPUT_SEL_OUT_MODE BIT(1) /* 0=loop 1=bypass */
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/linux-6.14.4/drivers/net/dsa/hirschmann/
Dhellcreek.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
6 * Copyright (C) 2019-2021 Linutronix GmbH
19 #include <linux/platform_data/hirschmann-hellcreek.h>
29 * - 0: CPU
30 * - 1: Tunnel
31 * - 2: TSN front port 1
32 * - 3: TSN front port 2
33 * - ...
45 #define HR_MODID_C (0 * 2)
46 #define HR_REL_L_C (1 * 2)
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/linux-6.14.4/drivers/clk/sunxi-ng/
Dccu-sun50i-a64.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun50i-a64.h"
27 .enable = BIT(31),
28 .lock = BIT(28),
30 .k = _SUNXI_CCU_MULT(4, 2),
31 .m = _SUNXI_CCU_DIV(0, 2),
32 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
35 .hw.init = CLK_HW_INIT("pll-cpux",
44 * the base (2x, 4x and 8x), and one variable divider (the one true
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/linux-6.14.4/drivers/clk/stm32/
Dstm32mp13_rcc.h1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
3 * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
216 #define RCC_SECCFGR_HSESEC 2
238 #define RCC_MP_SREQSETR_STPREQ_P0 BIT(0)
241 #define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0)
244 #define RCC_MP_APRSTCR_RDCTLEN BIT(0)
257 #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
258 #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
261 #define RCC_BR_RSTSCLRR_PORRSTF BIT(0)
262 #define RCC_BR_RSTSCLRR_BORRSTF BIT(1)
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/linux-6.14.4/drivers/media/i2c/ccs/
Dccs-regs.h1 /* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
2 /* Copyright (C) 2019--2020 Intel Corporation */
4 * Generated by Documentation/driver-api/media/drivers/ccs/mk-ccs-regs;
13 #include <media/v4l2-cci.h>
16 #define CCS_FL_FLOAT_IREAL BIT(CCS_FL_BASE)
17 #define CCS_FL_IREAL BIT(CCS_FL_BASE + 1)
19 BUILD_BUG_ON(~CCI_REG_PRIVATE_MASK & (BIT(CCS_FL_BASE) | BIT(CCS_FL_BASE + 1)))
26 #define CCS_PIXEL_ORDER_BGGR 2U
46 #define CCS_MODULE_DATE_PHASE_CS 2U
56 #define CCS_FRAME_FORMAT_MODEL_TYPE_4_BYTE 2U
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/linux-6.14.4/include/linux/mfd/syscon/
Dimx6q-iomuxc-gpr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
69 #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK BIT(7)
71 #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX BIT(7)
72 #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK BIT(6)
74 #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3 BIT(6)
75 #define IMX6Q_GPR0_DMAREQ_MUX_SEL5_MASK BIT(5)
77 #define IMX6Q_GPR0_DMAREQ_MUX_SEL5_EPIT2 BIT(5)
78 #define IMX6Q_GPR0_DMAREQ_MUX_SEL4_MASK BIT(4)
80 #define IMX6Q_GPR0_DMAREQ_MUX_SEL4_I2C1 BIT(4)
81 #define IMX6Q_GPR0_DMAREQ_MUX_SEL3_MASK BIT(3)
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/linux-6.14.4/drivers/net/ethernet/stmicro/stmmac/
Ddwmac4.h1 /* SPDX-License-Identifier: GPL-2.0-only */
57 #define GMAC_RXQCTRL_AVCPQ_MASK GENMASK(2, 0)
67 #define GMAC_RXQCTRL_MCBCQEN BIT(20)
69 #define GMAC_RXQCTRL_TACPQE BIT(21)
74 #define GMAC_PACKET_FILTER_PR BIT(0)
75 #define GMAC_PACKET_FILTER_HMC BIT(2)
76 #define GMAC_PACKET_FILTER_PM BIT(4)
77 #define GMAC_PACKET_FILTER_PCF BIT(7)
78 #define GMAC_PACKET_FILTER_HPF BIT(10)
79 #define GMAC_PACKET_FILTER_VTFE BIT(16)
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/linux-6.14.4/drivers/staging/vme_user/
Dvme_tsi148.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
28 #define TSI148_MAX_DMA 2 /* Max DMA Controllers */
35 wait_queue_head_t dma_queue[2];
50 * Layout of a DMAC Linked-List Descriptor
53 * correctly laid out - It must also be aligned on 64-bit boundaries.
65 __be32 ddbs; /* 2eSST Broadcast select */
70 * The descriptor needs to be aligned on a 64-bit boundary, we increase
79 * TSI148 ASIC register structure overlays and bit field definitions.
83 * PCFS - PCI Configuration Space Registers
84 * LCSR - Local Control and Status Registers
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/linux-6.14.4/drivers/net/wireless/ath/wil6210/
Dtxrx.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2012-2016 Qualcomm Atheros, Inc.
4 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
26 return le32_to_cpu(addr->addr_low) | in wil_desc_addr()
27 ((u64)le16_to_cpu(addr->addr_high) << 32); in wil_desc_addr()
33 addr->addr_low = cpu_to_le32(lower_32_bits(pa)); in wil_desc_addr_set()
34 addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa)); in wil_desc_addr_set()
37 /* Tx descriptor - MAC part
39 * bit 0.. 9 : lifetime_expiry_value:10
40 * bit 10 : interrupt_en:1
[all …]
Dtxrx_edma.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2012-2016,2018-2019, The Linux Foundation. All rights reserved.
32 #define WIL_RX_EDMA_ERROR_KEY (2) /* Key missing */
37 #define WIL_RX_EDMA_ERROR_L3_ERR (BIT(0) | BIT(1))
38 #define WIL_RX_EDMA_ERROR_L4_ERR (BIT(0) | BIT(1))
40 #define WIL_RX_EDMA_DLPF_LU_MISS_BIT BIT(11)
44 #define WIL_RX_EDMA_DLPF_LU_MISS_CID_POS 2
49 #define WIL_RX_EDMA_MID_VALID_BIT BIT(20)
58 #define WIL_EDMA_DESC_TX_CFG_TSO_DESC_TYPE_LEN 2
75 /* Enhanced Rx descriptor - MAC part
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/linux-6.14.4/drivers/net/wireless/intel/iwlwifi/fw/api/
Drs.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2022, 2024 Intel Corporation
12 * enum iwl_tlc_mng_cfg_flags - options for TLC config flags
22 * for BPSK (MCS 0) with 2 spatial
27 IWL_TLC_MNG_CFG_FLAGS_STBC_MSK = BIT(0),
28 IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK = BIT(1),
29 IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK = BIT(2),
30 IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK = BIT(3),
31 IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK = BIT(4),
32 IWL_TLC_MNG_CFG_FLAGS_EHT_EXTRA_LTF_MSK = BIT(6),
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