Lines Matching +full:2 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/
82 #define TPS65219_REG_INT_BUCK_3_POS 2
98 #define TPS65219_BUCKS_UV_THR_SEL_MASK BIT(6)
99 #define TPS65219_BUCKS_BW_SEL_MASK BIT(7)
101 #define TPS65219_LDOS_BYP_CONFIG_MASK BIT(LDO_BYP_SHIFT)
102 #define TPS65219_LDOS_LSW_CONFIG_MASK BIT(7)
104 #define TPS65219_ENABLE_BUCK1_EN_MASK BIT(0)
105 #define TPS65219_ENABLE_BUCK2_EN_MASK BIT(1)
106 #define TPS65219_ENABLE_BUCK3_EN_MASK BIT(2)
107 #define TPS65219_ENABLE_LDO1_EN_MASK BIT(3)
108 #define TPS65219_ENABLE_LDO2_EN_MASK BIT(4)
109 #define TPS65219_ENABLE_LDO3_EN_MASK BIT(5)
110 #define TPS65219_ENABLE_LDO4_EN_MASK BIT(6)
111 /* power ON-OFF sequence slot */
115 #define TPS65219_STBY1_BUCK1_STBY_EN_MASK BIT(0)
116 #define TPS65219_STBY1_BUCK2_STBY_EN_MASK BIT(1)
117 #define TPS65219_STBY1_BUCK3_STBY_EN_MASK BIT(2)
118 #define TPS65219_STBY1_LDO1_STBY_EN_MASK BIT(3)
119 #define TPS65219_STBY1_LDO2_STBY_EN_MASK BIT(4)
120 #define TPS65219_STBY1_LDO3_STBY_EN_MASK BIT(5)
121 #define TPS65219_STBY1_LDO4_STBY_EN_MASK BIT(6)
123 #define TPS65219_STBY2_GPO1_STBY_EN_MASK BIT(0)
124 #define TPS65219_STBY2_GPO2_STBY_EN_MASK BIT(1)
125 #define TPS65219_STBY2_GPIO_STBY_EN_MASK BIT(2)
127 #define TPS65219_MFP_I2C_OFF_REQ_MASK BIT(0)
128 #define TPS65219_MFP_STBY_I2C_CTRL_MASK BIT(1)
129 #define TPS65219_MFP_COLD_RESET_I2C_CTRL_MASK BIT(2)
130 #define TPS65219_MFP_WARM_RESET_I2C_CTRL_MASK BIT(3)
131 #define TPS65219_MFP_GPIO_STATUS_MASK BIT(4)
133 #define TPS65219_MFP_1_VSEL_DDR_SEL_MASK BIT(0)
134 #define TPS65219_MFP_1_VSEL_SD_POL_MASK BIT(1)
135 #define TPS65219_MFP_1_VSEL_RAIL_MASK BIT(2)
138 #define TPS65219_MFP_2_MODE_RESET_MASK BIT(2)
139 #define TPS65219_MFP_2_EN_PB_VSENSE_DEGL_MASK BIT(3)
141 #define TPS65219_MFP_2_WARM_COLD_RESET_MASK BIT(6)
142 #define TPS65219_MFP_2_PU_ON_FSD_MASK BIT(7)
144 #define TPS65219_MFP_2_PB BIT(4)
145 #define TPS65219_MFP_2_VSENSE BIT(5)
147 #define TPS65219_REG_MASK_UV_LDO1_UV_MASK BIT(0)
148 #define TPS65219_REG_MASK_UV_LDO2_UV_MASK BIT(1)
149 #define TPS65219_REG_MASK_UV_LDO3_UV_MASK BIT(2)
150 #define TPS65219_REG_MASK_UV_LDO4_UV_MASK BIT(3)
151 #define TPS65219_REG_MASK_UV_BUCK1_UV_MASK BIT(4)
152 #define TPS65219_REG_MASK_UV_BUCK2_UV_MASK BIT(5)
153 #define TPS65219_REG_MASK_UV_BUCK3_UV_MASK BIT(6)
154 #define TPS65219_REG_MASK_UV_RETRY_MASK BIT(7)
157 #define TPS65219_REG_MASK_INT_FOR_RV_MASK BIT(4)
158 #define TPS65219_REG_MASK_EFFECT_MASK GENMASK(2, 1)
159 #define TPS65219_REG_MASK_INT_FOR_PB_MASK BIT(7)
160 /* UnderVoltage - Short to GND - OverCurrent*/
161 /* LDO3-4 */
162 #define TPS65219_INT_LDO3_SCG_MASK BIT(0)
163 #define TPS65219_INT_LDO3_OC_MASK BIT(1)
164 #define TPS65219_INT_LDO3_UV_MASK BIT(2)
165 #define TPS65219_INT_LDO4_SCG_MASK BIT(3)
166 #define TPS65219_INT_LDO4_OC_MASK BIT(4)
167 #define TPS65219_INT_LDO4_UV_MASK BIT(5)
168 /* LDO1-2 */
169 #define TPS65219_INT_LDO1_SCG_MASK BIT(0)
170 #define TPS65219_INT_LDO1_OC_MASK BIT(1)
171 #define TPS65219_INT_LDO1_UV_MASK BIT(2)
172 #define TPS65219_INT_LDO2_SCG_MASK BIT(3)
173 #define TPS65219_INT_LDO2_OC_MASK BIT(4)
174 #define TPS65219_INT_LDO2_UV_MASK BIT(5)
176 #define TPS65219_INT_BUCK3_SCG_MASK BIT(0)
177 #define TPS65219_INT_BUCK3_OC_MASK BIT(1)
178 #define TPS65219_INT_BUCK3_NEG_OC_MASK BIT(2)
179 #define TPS65219_INT_BUCK3_UV_MASK BIT(3)
180 /* BUCK1-2 */
181 #define TPS65219_INT_BUCK1_SCG_MASK BIT(0)
182 #define TPS65219_INT_BUCK1_OC_MASK BIT(1)
183 #define TPS65219_INT_BUCK1_NEG_OC_MASK BIT(2)
184 #define TPS65219_INT_BUCK1_UV_MASK BIT(3)
185 #define TPS65219_INT_BUCK2_SCG_MASK BIT(4)
186 #define TPS65219_INT_BUCK2_OC_MASK BIT(5)
187 #define TPS65219_INT_BUCK2_NEG_OC_MASK BIT(6)
188 #define TPS65219_INT_BUCK2_UV_MASK BIT(7)
190 #define TPS65219_INT_SENSOR_3_WARM_MASK BIT(0)
191 #define TPS65219_INT_SENSOR_2_WARM_MASK BIT(1)
192 #define TPS65219_INT_SENSOR_1_WARM_MASK BIT(2)
193 #define TPS65219_INT_SENSOR_0_WARM_MASK BIT(3)
194 #define TPS65219_INT_SENSOR_3_HOT_MASK BIT(4)
195 #define TPS65219_INT_SENSOR_2_HOT_MASK BIT(5)
196 #define TPS65219_INT_SENSOR_1_HOT_MASK BIT(6)
197 #define TPS65219_INT_SENSOR_0_HOT_MASK BIT(7)
199 #define TPS65219_INT_BUCK1_RV_MASK BIT(0)
200 #define TPS65219_INT_BUCK2_RV_MASK BIT(1)
201 #define TPS65219_INT_BUCK3_RV_MASK BIT(2)
202 #define TPS65219_INT_LDO1_RV_MASK BIT(3)
203 #define TPS65219_INT_LDO2_RV_MASK BIT(4)
204 #define TPS65219_INT_LDO3_RV_MASK BIT(5)
205 #define TPS65219_INT_LDO4_RV_MASK BIT(6)
207 #define TPS65219_INT_BUCK1_RV_SD_MASK BIT(0)
208 #define TPS65219_INT_BUCK2_RV_SD_MASK BIT(1)
209 #define TPS65219_INT_BUCK3_RV_SD_MASK BIT(2)
210 #define TPS65219_INT_LDO1_RV_SD_MASK BIT(3)
211 #define TPS65219_INT_LDO2_RV_SD_MASK BIT(4)
212 #define TPS65219_INT_LDO3_RV_SD_MASK BIT(5)
213 #define TPS65219_INT_LDO4_RV_SD_MASK BIT(6)
214 #define TPS65219_INT_TIMEOUT_MASK BIT(7)
216 #define TPS65219_INT_PB_FALLING_EDGE_DETECT_MASK BIT(0)
217 #define TPS65219_INT_PB_RISING_EDGE_DETECT_MASK BIT(1)
218 #define TPS65219_INT_PB_REAL_TIME_STATUS_MASK BIT(2)
225 #define TPS65219_BUCK_3_POS 2
231 /* LDO3-4 register IRQs */
238 /* LDO1-2 */
250 /* BUCK1-2 */
302 /* Number of step-down converters available */
323 * struct tps65219 - tps65219 sub-driver chip access routines