Lines Matching +full:2 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
88 /* Touch Device Interrupt Cause register Format Configuration Register 2 */
139 /* THC Read PRD Base Address Low for the 2nd RXDMA */
141 /* THC Read PRD Base Address High for the 2nd RXDMA */
143 /* THC Read PRD Control for the 2nd RXDMA */
145 /* THC Read DMA Control for the 2nd RXDMA */
147 /* THC Read Interrupt Status for the 2nd RXDMA */
149 /* THC Read DMA Error Register for the 2nd RXDMA */
151 /* Touch Sequencer GuC Tail Offset Address Low for the 2nd RXDMA */
153 /* Touch Sequencer GuC Tail Offset Address High for the 2nd RXDMA */
155 /* Touch Host Controller GuC Work Queue Item Size for the 2nd RXDMA */
157 /* Touch Host Controller GuC Control register for the 2nd RXDMA */
159 /* Touch Sequencer Control for the 2nd DMA */
161 /* Touch Sequencer GuC Doorbell Address Low for the 2nd RXDMA */
163 /* Touch Sequencer GuC Doorbell Address High for the 2nd RXDMA */
167 /* Touch Sequencer GuC Tail Offset Initial Value for the 2nd RXDMA */
169 /* THC Device Address for the bulk/touch data read for the 2nd RXDMA */
171 /* THC Gfx/SW Doorbell Count from the 2nd Stream RXDMA on this port */
173 /* THC Frame Count from the 2nd Stream RXDMA on this port */
175 /* THC Micro Frame Count from the 2nd Stream RXDMA on this port */
177 /* THC Packet Count from the 2nd Stream RXDMA on this port */
180 * THC Software Interrupt Count from the 2nd Stream RXDMA
184 /* Touch Sequencer Frame Drop Counter for the 2nd RXDMA */
186 /* THC Coaescing 2 */
212 /* THC timing based Frame/Interrupt caolescing control register for 2nd RXDMA */
216 /* Touch Sequencer PRD Table Empty Counter for the 2nd RXDM */
220 /* THC coalescing status to reflect the current coalescing FSM state for 2nd RXDMA */
240 #define TXN_ERR_INT_STS_BIT BIT(28)
241 #define TXN_FATAL_INT_STS_BIT BIT(30)
243 #define NONDMA_INT_STS_BIT BIT(4)
244 #define EOF_INT_STS_BIT BIT(5)
249 #define THC_CFG_STS_CMD_IOSE BIT(0)
250 #define THC_CFG_STS_CMD_MSE BIT(1)
251 #define THC_CFG_STS_CMD_BME BIT(2)
252 #define THC_CFG_STS_CMD_SPCYC BIT(3)
253 #define THC_CFG_STS_CMD_MWRIEN BIT(4)
254 #define THC_CFG_STS_CMD_VGAPS BIT(5)
255 #define THC_CFG_STS_CMD_PERRR BIT(6)
256 #define THC_CFG_STS_CMD_SERREN BIT(8)
257 #define THC_CFG_STS_CMD_FBTBEN BIT(9)
258 #define THC_CFG_STS_CMD_INTD BIT(10)
259 #define THC_CFG_STS_CMD_INTS BIT(19)
260 #define THC_CFG_STS_CMD_CAPL BIT(20)
261 #define THC_CFG_STS_CMD_MCAP BIT(21)
262 #define THC_CFG_STS_CMD_FBTBC BIT(23)
263 #define THC_CFG_STS_CMD_MDPE BIT(24)
265 #define THC_CFG_STS_CMD_STA BIT(27)
266 #define THC_CFG_STS_CMD_RTA BIT(28)
267 #define THC_CFG_STS_CMD_RMA BIT(29)
268 #define THC_CFG_STS_CMD_SSE BIT(30)
269 #define THC_CFG_STS_CMD_DPE BIT(31)
279 #define THC_CFG_BIST_HTYPE_LT_CLS_MFD BIT(23)
281 #define THC_CFG_BAR0_LOW_MEMSPACE BIT(0)
282 #define THC_CFG_BAR0_LOW_TYP GENMASK(2, 1)
283 #define THC_CFG_BAR0_LOW_PREFETCH BIT(3)
296 #define THC_CFG_UR_STS_CTL_URRE BIT(0)
297 #define THC_CFG_UR_STS_CTL_URD BIT(1)
298 #define THC_CFG_UR_STS_CTL_FD BIT(2)
302 #define THC_CFG_MSIMC_MSINP_MSICID_MSIE BIT(16)
305 #define THC_CFG_MSIMC_MSINP_MSICID_XAC BIT(23)
306 #define THC_CFG_MSIMC_MSINP_MSICID_PVMC BIT(24)
307 #define THC_CFG_MSIMA_MADDR GENMASK(31, 2)
314 #define THC_CFG_PMCAP_PMNP_PMCID_PMECLK BIT(19)
315 #define THC_CFG_PMCAP_PMNP_PMCID_DSI BIT(21)
317 #define THC_CFG_PMCAP_PMNP_PMCID_D1S BIT(25)
318 #define THC_CFG_PMCAP_PMNP_PMCID_D2S BIT(26)
322 #define THC_CFG_PMD_PMCSRBSE_PMCSR_NSR BIT(3)
323 #define THC_CFG_PMD_PMCSRBSE_PMCSR_PMEEN BIT(8)
326 #define THC_CFG_PMD_PMCSRBSE_PMCSR_PMESTS BIT(15)
338 #define THC_CFG_SWLTRPTR_VALID BIT(0)
342 #define THC_CFG_DEVIDLEPTR_VALID BIT(0)
348 #define THC_CFG_PCE_SPE BIT(0)
349 #define THC_CFG_PCE_I3E BIT(1)
350 #define THC_CFG_PCE_D3HE BIT(2)
351 #define THC_CFG_PCE_SE BIT(3)
352 #define THC_CFG_PCE_HAE BIT(5)
359 #define THC_M_CMN_DEVIDLECTRL_CIP BIT(0)
360 #define THC_M_CMN_DEVIDLECTRL_IR BIT(1)
361 #define THC_M_CMN_DEVIDLECTRL_DEVIDLE BIT(2)
362 #define THC_M_CMN_DEVIDLECTRL_RR BIT(3)
363 #define THC_M_CMN_DEVIDLECTRL_IRC BIT(4)
366 #define THC_M_CMN_LTR_CTRL_ACTIVE_LTR_REQ BIT(0)
367 #define THC_M_CMN_LTR_CTRL_ACTIVE_LTR_EN BIT(1)
368 #define THC_M_CMN_LTR_CTRL_LP_LTR_REQ BIT(2)
369 #define THC_M_CMN_LTR_CTRL_LP_LTR_EN BIT(3)
376 #define THC_M_PRT_CONTROL_TSFTRST BIT(0)
377 #define THC_M_PRT_CONTROL_THC_DEVINT_QUIESCE_EN BIT(1)
378 #define THC_M_PRT_CONTROL_THC_DEVINT_QUIESCE_HW_STS BIT(2)
379 #define THC_M_PRT_CONTROL_DEVRST BIT(3)
380 #define THC_M_PRT_CONTROL_THC_DRV_LOCK_EN BIT(13)
384 #define THC_M_PRT_CONTROL_THC_BIOS_LOCK_EN BIT(27)
385 #define THC_M_PRT_CONTROL_PORT_SUPPORTED BIT(28)
386 #define THC_M_PRT_CONTROL_SPI_IO_RDY BIT(29)
390 #define THC_M_PRT_SPI_CFG_SPI_TRMODE GENMASK(3, 2)
395 #define THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN BIT(23)
402 #define THC_M_PRT_INT_EN_SIPE BIT(0)
403 #define THC_M_PRT_INT_EN_SBO BIT(1)
404 #define THC_M_PRT_INT_EN_SIDR BIT(2)
405 #define THC_M_PRT_INT_EN_SOFB BIT(3)
406 #define THC_M_PRT_INT_EN_INVLD_DEV_ENTRY_INT_EN BIT(9)
407 #define THC_M_PRT_INT_EN_FRAME_BABBLE_ERR_INT_EN BIT(10)
408 #define THC_M_PRT_INT_EN_BUF_OVRRUN_ERR_INT_EN BIT(12)
409 #define THC_M_PRT_INT_EN_PRD_ENTRY_ERR_INT_EN BIT(13)
410 #define THC_M_PRT_INT_EN_DISP_SYNC_EVT_INT_EN BIT(14)
411 #define THC_M_PRT_INT_EN_DEV_RAW_INT_EN BIT(15)
412 #define THC_M_PRT_INT_EN_FATAL_ERR_INT_EN BIT(16)
413 #define THC_M_PRT_INT_EN_THC_I2C_IC_RX_UNDER_INT_EN BIT(17)
414 #define THC_M_PRT_INT_EN_THC_I2C_IC_RX_OVER_INT_EN BIT(18)
415 #define THC_M_PRT_INT_EN_THC_I2C_IC_RX_FULL_INT_EN BIT(19)
416 #define THC_M_PRT_INT_EN_THC_I2C_IC_TX_OVER_INT_EN BIT(20)
417 #define THC_M_PRT_INT_EN_THC_I2C_IC_TX_EMPTY_INT_EN BIT(21)
418 #define THC_M_PRT_INT_EN_THC_I2C_IC_TX_ABRT_INT_EN BIT(22)
419 #define THC_M_PRT_INT_EN_THC_I2C_IC_SCL_STUCK_AT_LOW_DET_INT_EN BIT(24)
420 #define THC_M_PRT_INT_EN_THC_I2C_IC_STOP_DET_INT_EN BIT(25)
421 #define THC_M_PRT_INT_EN_THC_I2C_IC_START_DET_INT_EN BIT(26)
422 #define THC_M_PRT_INT_EN_THC_I2C_IC_MST_ON_HOLD_INT_EN BIT(27)
423 #define THC_M_PRT_INT_EN_TXN_ERR_INT_EN BIT(29)
424 #define THC_M_PRT_INT_EN_GBL_INT_EN BIT(31)
426 #define THC_M_PRT_INT_STATUS_DISP_SYNC_EVT_INT_STS BIT(14)
427 #define THC_M_PRT_INT_STATUS_DEV_RAW_INT_STS BIT(15)
428 #define THC_M_PRT_INT_STATUS_THC_I2C_IC_RX_UNDER_INT_STS BIT(17)
429 #define THC_M_PRT_INT_STATUS_THC_I2C_IC_RX_OVER_INT_STS BIT(18)
430 #define THC_M_PRT_INT_STATUS_THC_I2C_IC_RX_FULL_INT_STS BIT(19)
431 #define THC_M_PRT_INT_STATUS_THC_I2C_IC_TX_OVER_INT_STS BIT(20)
432 #define THC_M_PRT_INT_STATUS_THC_I2C_IC_TX_EMPTY_INT_STS BIT(21)
433 #define THC_M_PRT_INT_STATUS_THC_I2C_IC_TX_ABRT_INT_STS BIT(22)
434 #define THC_M_PRT_INT_STATUS_THC_I2C_IC_ACTIVITY_INT_STS BIT(23)
435 #define THC_M_PRT_INT_STATUS_THC_I2C_IC_SCL_STUCK_AT_LOW_INT_STS BIT(24)
436 #define THC_M_PRT_INT_STATUS_THC_I2C_IC_STOP_DET_INT_STS BIT(25)
437 #define THC_M_PRT_INT_STATUS_THC_I2C_IC_START_DET_INT_STS BIT(26)
438 #define THC_M_PRT_INT_STATUS_THC_I2C_IC_MST_ON_HOLD_INT_STS BIT(27)
439 #define THC_M_PRT_INT_STATUS_TXN_ERR_INT_STS BIT(28)
440 #define THC_M_PRT_INT_STATUS_FATAL_ERR_INT_STS BIT(30)
442 #define THC_M_PRT_ERR_CAUSE_INVLD_DEV_ENTRY BIT(9)
443 #define THC_M_PRT_ERR_CAUSE_FRAME_BABBLE_ERR BIT(10)
444 #define THC_M_PRT_ERR_CAUSE_BUF_OVRRUN_ERR BIT(12)
445 #define THC_M_PRT_ERR_CAUSE_PRD_ENTRY_ERR BIT(13)
448 #define THC_M_PRT_SW_SEQ_CNTRL_TSSGO BIT(0)
449 #define THC_M_PRT_SW_SEQ_CNTRL_THC_SS_CD_IE BIT(1)
452 #define THC_M_PRT_SW_SEQ_STS_TSSDONE BIT(0)
453 #define THC_M_PRT_SW_SEQ_STS_THC_SS_ERR BIT(1)
454 #define THC_M_PRT_SW_SEQ_STS_THC_SS_CIP BIT(3)
461 #define THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_START BIT(0)
462 #define THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_IE_IOC_ERROR BIT(1)
463 #define THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_IE_IOC BIT(2)
464 #define THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_IE_IOC_DMACPL BIT(3)
465 #define THC_M_PRT_WRITE_DMA_CNTRL_THC_WRDMA_UHS BIT(23)
468 #define THC_M_PRT_WRITE_INT_STS_THC_WRDMA_CMPL_STATUS BIT(0)
469 #define THC_M_PRT_WRITE_INT_STS_THC_WRDMA_ERROR_STS BIT(1)
470 #define THC_M_PRT_WRITE_INT_STS_THC_WRDMA_IOC_STS BIT(2)
471 #define THC_M_PRT_WRITE_INT_STS_THC_WRDMA_ACTIVE BIT(3)
478 #define THC_M_PRT_DEV_INT_CAUSE_REG_VAL_BEGINNING_OF_FRAME BIT(29)
479 #define THC_M_PRT_DEV_INT_CAUSE_REG_VAL_END_OF_FRAME BIT(30)
480 #define THC_M_PRT_DEV_INT_CAUSE_REG_VAL_FRAME_TYPE BIT(31)
483 #define THC_M_PRT_TX_FRM_CNT_THC_M_PRT_TX_FRM_CNT_RST BIT(31)
486 #define THC_M_PRT_TXDMA_PKT_CNT_THC_M_PRT_TXDMA_PKT_CNT_RST BIT(31)
489 #define THC_M_PRT_DEVINT_CNT_THC_M_PRT_DEVINT_CNT_RST BIT(31)
494 #define THC_M_PRT_DEVINT_CFG_1_THC_M_PRT_SEND_ICR_US_EN BIT(15)
500 #define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_FTYPE_IGNORE BIT(16)
501 #define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_FTYPE_VAL BIT(17)
502 #define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_RXDMA_ADDRINC_DIS BIT(24)
503 #define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_TXDMA_ADDRINC_DIS BIT(25)
504 #define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_RXDMA_PKT_STRM_EN BIT(26)
505 #define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_TXDMA_PKT_STRM_EN BIT(27)
506 #define THC_M_PRT_DEVINT_CFG_2_THC_M_PRT_DEVINT_POL BIT(28)
515 #define THC_M_PRT_READ_DMA_CNTRL_START BIT(0)
516 #define THC_M_PRT_READ_DMA_CNTRL_IE_ERROR BIT(1)
517 #define THC_M_PRT_READ_DMA_CNTRL_IE_IOC BIT(2)
518 #define THC_M_PRT_READ_DMA_CNTRL_IE_STALL BIT(3)
519 #define THC_M_PRT_READ_DMA_CNTRL_IE_NDDI BIT(4)
520 #define THC_M_PRT_READ_DMA_CNTRL_IE_EOF BIT(5)
521 #define THC_M_PRT_READ_DMA_CNTRL_IE_DMACPL BIT(7)
524 #define THC_M_PRT_READ_DMA_CNTRL_INT_SW_DMA_EN BIT(28)
525 #define THC_M_PRT_READ_DMA_CNTRL_SOO BIT(29)
526 #define THC_M_PRT_READ_DMA_CNTRL_UHS BIT(30)
527 #define THC_M_PRT_READ_DMA_CNTRL_TPCPR BIT(31)
529 #define THC_M_PRT_READ_DMA_INT_STS_DMACPL_STS BIT(0)
530 #define THC_M_PRT_READ_DMA_INT_STS_ERROR_STS BIT(1)
531 #define THC_M_PRT_READ_DMA_INT_STS_IOC_STS BIT(2)
532 #define THC_M_PRT_READ_DMA_INT_STS_STALL_STS BIT(3)
533 #define THC_M_PRT_READ_DMA_INT_STS_NONDMA_INT_STS BIT(4)
534 #define THC_M_PRT_READ_DMA_INT_STS_EOF_INT_STS BIT(5)
535 #define THC_M_PRT_READ_DMA_INT_STS_ACTIVE BIT(8)
537 #define THC_M_PRT_READ_DMA_ERR_1_DLERR BIT(0)
546 #define THC_M_PRT_TSEQ_CNTRL_1_RGD BIT(2)
547 #define THC_M_PRT_TSEQ_CNTRL_1_EGP BIT(3)
548 #define THC_M_PRT_TSEQ_CNTRL_1_RTO BIT(4)
549 #define THC_M_PRT_TSEQ_CNTRL_1_EWOG BIT(5)
550 #define THC_M_PRT_TSEQ_CNTRL_1_RWOGC BIT(6)
552 #define THC_M_PRT_TSEQ_CNTRL_1_RESET_PREP_CHICKEN BIT(30)
553 #define THC_M_PRT_TSEQ_CNTRL_1_INT_EDG_DET_EN BIT(31)
555 #define THC_M_PRT_GUC_DB_ADDR_LOW_1_GUC_DB_ADDR_LOW GENMASK(31, 2)
563 #define THC_M_PRT_DB_CNT_1_THC_M_PRT_DB_CNT_RST BIT(31)
566 #define THC_M_PRT_FRM_CNT_1_THC_M_PRT_FRM_CNT_RST BIT(31)
569 #define THC_M_PRT_UFRM_CNT_1_THC_M_PRT_UFRM_CNT_RST BIT(31)
572 #define THC_M_PRT_RXDMA_PKT_CNT_1_THC_M_PRT_RXDMA_PKT_CNT_RST BIT(31)
575 #define THC_M_PRT_SWINT_CNT_1_THC_M_PRT_SWINT_CNT_RST BIT(31)
578 #define THC_M_PRT_FRAME_DROP_CNT_1_RFDC BIT(31)
585 #define THC_M_PRT_READ_DMA_ERR_2_DLERR BIT(0)
595 #define THC_M_PRT_TSEQ_CNTRL_2_RGD BIT(2)
596 #define THC_M_PRT_TSEQ_CNTRL_2_EGP BIT(3)
597 #define THC_M_PRT_TSEQ_CNTRL_2_RTO BIT(4)
599 #define THC_M_PRT_GUC_DB_ADDR_LOW_2_GUC_DB_ADDR_LOW GENMASK(31, 2)
609 #define THC_M_PRT_DB_CNT_2_THC_M_PRT_DB_CNT_RST BIT(31)
612 #define THC_M_PRT_FRM_CNT_2_THC_M_PRT_FRM_CNT_RST BIT(31)
615 #define THC_M_PRT_UFRM_CNT_2_THC_M_PRT_UFRM_CNT_RST BIT(31)
618 #define THC_M_PRT_RXDMA_PKT_CNT_2_THC_M_PRT_RXDMA_PKT_CNT_RST BIT(31)
621 #define THC_M_PRT_SWINT_CNT_2_THC_M_PRT_SWINT_CNT_RST BIT(31)
624 #define THC_M_PRT_FRAME_DROP_CNT_2_RFDC BIT(31)
628 #define THC_M_PRT_SW_SEQ_I2C_WR_CNTRL_THC_I2C_RW_PIO_EN BIT(23)
631 #define THC_M_PRT_RPRD_CNTRL_SW_THC_SWDMA_I2C_RX_DLEN_EN BIT(23)
634 #define THC_M_PRT_PRD_EMPTY_CNT_1_RPTEC BIT(31)
635 #define THC_M_PRT_PRD_EMPTY_CNT_2_RPTEC BIT(31)
640 #define THC_M_PRT_SPI_DUTYC_CFG_SPI_CSA_CK_DELAY_EN BIT(25)
651 #define THC_ARB_POLICY_FRAME_BOUNDARY 2
660 /* Last fragment indicator is bit 15 for HIDSPI */
665 /* MFS unit in power of 2 */
666 #define THC_UNIT_MICROFRAME_SIZE 2
668 #define THC_BITMASK_INVALID_TYPE_DATA 2
676 * Scale is geometric progression of 2^5 step, starting from 2^0.
677 * For example, THC_LTR_SCALE_2(2) means 2^(5 * 2) = 1024, unit is ns.
681 #define THC_LTR_SCALE_2 2
687 #define THC_LTR_MIN_VAL_SCALE_3 BIT(10)
688 #define THC_LTR_MAX_VAL_SCALE_3 BIT(15)
689 #define THC_LTR_MIN_VAL_SCALE_4 BIT(15)
690 #define THC_LTR_MAX_VAL_SCALE_4 BIT(20)
691 #define THC_LTR_MIN_VAL_SCALE_5 BIT(20)
692 #define THC_LTR_MAX_VAL_SCALE_5 BIT(25)
716 * @THC_SINGLE_IO: single IO mode, 1(opcode) - 1(address) - 1(data)
717 * @THC_DUAL_IO: dual IO mode, 1(opcode) - 2(address) - 2(data)
718 * @THC_QUAD_IO: quad IO mode, 1(opcode) - 4(address) - 4(data)
719 * @THC_QUAD_PARALLEL_IO: parallel quad IO mode, 4(opcode) - 4(address) - 4(data)
724 THC_QUAD_IO = 2,
731 * This DIV final value is determined by THC_M_PRT_SPI_CFG_SPI_LOW_FREQ_EN bit.
744 THC_SPI_FRQ_DIV_2 = 2,
752 /* THC I2C sub-system registers */
822 * THC I2C sub-system supported speed mode
826 THC_I2C_FAST_AND_PLUS = 2,
830 /* THC I2C sub-system register bits definition */
831 #define THC_I2C_IC_ENABLE_ENABLE BIT(0)
832 #define THC_I2C_IC_ENABLE_ABORT BIT(1)
833 #define THC_I2C_IC_ENABLE_TX_CMD_BLOCK BIT(2)
834 #define THC_I2C_IC_ENABLE_SDA_STUCK_RECOVERY_ENABLE BIT(3)
835 #define THC_I2C_IC_ENABLE_SMBUS_CLK_RESET BIT(16)
836 #define THC_I2C_IC_ENABLE_SMBUS_SUSPEND_EN BIT(17)
837 #define THC_I2C_IC_ENABLE_SMBUS_ALERT_EN BIT(18)
839 #define THC_I2C_IC_CON_MASTER_MODE BIT(0)
840 #define THC_I2C_IC_CON_SPEED GENMASK(2, 1)
841 #define THC_I2C_IC_CON_IC_10BITADDR_SLAVE BIT(3)
842 #define THC_I2C_IC_CON_IC_10BITADDR_MASTER BIT(4)
843 #define THC_I2C_IC_CON_IC_RESTART_EN BIT(5)
844 #define THC_I2C_IC_CON_IC_SLAVE_DISABLE BIT(6)
845 #define THC_I2C_IC_CON_STOP_DET_IFADDRESSED BIT(7)
846 #define THC_I2C_IC_CON_TX_EMPTY_CTRL BIT(8)
847 #define THC_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL BIT(9)
848 #define THC_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE BIT(10)
849 #define THC_I2C_IC_CON_BUS_CLEAR_FEATURE_CTRL BIT(11)
850 #define THC_I2C_IC_CON_OPTIONAL_SAR_CTRL BIT(16)
851 #define THC_I2C_IC_CON_SMBUS_SLAVE_QUICK_EN BIT(17)
852 #define THC_I2C_IC_CON_SMBUS_ARP_EN BIT(18)
853 #define THC_I2C_IC_CON_SMBUS_PERSISTENT_SLV_ADDR_EN BIT(19)
856 #define THC_I2C_IC_TAR_GC_OR_START BIT(10)
857 #define THC_I2C_IC_TAR_SPECIAL BIT(11)
858 #define THC_I2C_IC_TAR_IC_10BITADDR_MASTER BIT(12)
859 #define THC_I2C_IC_TAR_DEVICE_ID BIT(13)
860 #define THC_I2C_IC_TAR_SMBUS_QUICK_CMD BIT(16)
862 #define THC_I2C_IC_INTR_MASK_M_RX_UNDER BIT(0)
863 #define THC_I2C_IC_INTR_MASK_M_RX_OVER BIT(1)
864 #define THC_I2C_IC_INTR_MASK_M_RX_FULL BIT(2)
865 #define THC_I2C_IC_INTR_MASK_M_TX_OVER BIT(3)
866 #define THC_I2C_IC_INTR_MASK_M_TX_EMPTY BIT(4)
867 #define THC_I2C_IC_INTR_MASK_M_RD_REQ BIT(5)
868 #define THC_I2C_IC_INTR_MASK_M_TX_ABRT BIT(6)
869 #define THC_I2C_IC_INTR_MASK_M_RX_DONE BIT(7)
870 #define THC_I2C_IC_INTR_MASK_M_ACTIVITY BIT(8)
871 #define THC_I2C_IC_INTR_MASK_M_STOP_DET BIT(9)
872 #define THC_I2C_IC_INTR_MASK_M_START_DET BIT(10)
873 #define THC_I2C_IC_INTR_MASK_M_GEN_CALL BIT(11)
874 #define THC_I2C_IC_INTR_MASK_M_RESTART_DET BIT(12)
875 #define THC_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD BIT(13)
876 #define THC_I2C_IC_INTR_MASK_M_SCL_STUCK_AT_LOW BIT(14)
878 #define THC_I2C_IC_DMA_CR_RDMAE BIT(0)
879 #define THC_I2C_IC_DMA_CR_TDMAE BIT(1)