Lines Matching +full:2 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun50i-a64.h"
27 .enable = BIT(31),
28 .lock = BIT(28),
30 .k = _SUNXI_CCU_MULT(4, 2),
31 .m = _SUNXI_CCU_DIV(0, 2),
32 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
35 .hw.init = CLK_HW_INIT("pll-cpux",
44 * the base (2x, 4x and 8x), and one variable divider (the one true
47 * With sigma-delta modulation for fractional-N on the audio PLL,
61 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
65 pll_audio_sdm_table, BIT(24),
66 0x284, BIT(31),
67 BIT(31), /* gate */
68 BIT(28), /* lock */
71 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST(pll_video0_clk, "pll-video0",
77 BIT(24), /* frac enable */
78 BIT(25), /* frac select */
81 BIT(31), /* gate */
82 BIT(28), /* lock */
85 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
89 BIT(24), /* frac enable */
90 BIT(25), /* frac select */
93 BIT(31), /* gate */
94 BIT(28), /* lock */
97 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
100 4, 2, /* K */
101 0, 2, /* M */
102 BIT(31), /* gate */
103 BIT(28), /* lock */
107 .enable = BIT(31),
108 .lock = BIT(28),
110 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
111 .fixed_post_div = 2,
115 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
121 .enable = BIT(31),
122 .lock = BIT(28),
124 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
125 .fixed_post_div = 2,
129 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
134 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
140 BIT(24), /* frac enable */
141 BIT(25), /* frac select */
144 BIT(31), /* gate */
145 BIT(28), /* lock */
148 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
152 BIT(24), /* frac enable */
153 BIT(25), /* frac select */
156 BIT(31), /* gate */
157 BIT(28), /* lock */
170 * The bit 23 and 22 are called "LDO{1,2}_EN" on the SoC's
174 .enable = BIT(31) | BIT(23) | BIT(22),
175 .lock = BIT(28),
177 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
183 .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",
192 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
196 BIT(24), /* frac enable */
197 BIT(25), /* frac select */
200 BIT(31), /* gate */
201 BIT(28), /* lock */
204 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
208 BIT(24), /* frac enable */
209 BIT(25), /* frac select */
212 BIT(31), /* gate */
213 BIT(28), /* lock */
216 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
219 0, 2, /* M */
220 BIT(31), /* gate */
221 BIT(28), /* lock */
225 "pll-cpux", "pll-cpux" };
227 0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
229 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
232 "axi", "pll-periph0" };
234 { .index = 3, .shift = 6, .width = 2 },
237 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
241 .width = 2,
258 { .val = 0, .div = 2 },
259 { .val = 1, .div = 2 },
260 { .val = 2, .div = 4 },
265 0x054, 8, 2, apb1_div_table, 0);
268 "pll-periph0-2x",
269 "pll-periph0-2x" };
272 16, 2, /* P */
273 24, 2, /* mux */
276 static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };
278 { .index = 1, .div = 2 },
298 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
299 0x060, BIT(1), 0);
300 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
301 0x060, BIT(5), 0);
302 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
303 0x060, BIT(6), 0);
304 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
305 0x060, BIT(8), 0);
306 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
307 0x060, BIT(9), 0);
308 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
309 0x060, BIT(10), 0);
310 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
311 0x060, BIT(13), 0);
312 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
313 0x060, BIT(14), 0);
314 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
315 0x060, BIT(17), 0);
316 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",
317 0x060, BIT(18), 0);
318 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
319 0x060, BIT(19), 0);
320 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
321 0x060, BIT(20), 0);
322 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
323 0x060, BIT(21), 0);
324 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
325 0x060, BIT(23), 0);
326 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
327 0x060, BIT(24), 0);
328 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2",
329 0x060, BIT(25), 0);
330 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
331 0x060, BIT(28), 0);
332 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2",
333 0x060, BIT(29), 0);
335 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
336 0x064, BIT(0), 0);
337 static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
338 0x064, BIT(3), 0);
339 static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1",
340 0x064, BIT(4), 0);
341 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",
342 0x064, BIT(5), 0);
343 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
344 0x064, BIT(8), 0);
345 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1",
346 0x064, BIT(11), 0);
347 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
348 0x064, BIT(12), 0);
349 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
350 0x064, BIT(20), 0);
351 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
352 0x064, BIT(21), 0);
353 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
354 0x064, BIT(22), 0);
356 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
357 0x068, BIT(0), 0);
358 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
359 0x068, BIT(1), 0);
360 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
361 0x068, BIT(5), 0);
362 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",
363 0x068, BIT(8), 0);
364 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
365 0x068, BIT(12), 0);
366 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
367 0x068, BIT(13), 0);
368 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
369 0x068, BIT(14), 0);
371 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
372 0x06c, BIT(0), 0);
373 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
374 0x06c, BIT(1), 0);
375 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
376 0x06c, BIT(2), 0);
377 static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2",
378 0x06c, BIT(5), 0);
379 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
380 0x06c, BIT(16), 0);
381 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
382 0x06c, BIT(17), 0);
383 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
384 0x06c, BIT(18), 0);
385 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
386 0x06c, BIT(19), 0);
387 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
388 0x06c, BIT(20), 0);
390 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
391 0x070, BIT(7), 0);
395 { .val = 1, .div = 2 },
396 { .val = 2, .div = 4 },
402 .enable = BIT(31),
403 .div = _SUNXI_CCU_DIV_TABLE(0, 2, ths_div_table),
404 .mux = _SUNXI_CCU_MUX(24, 2),
414 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
415 "pll-periph1" };
418 16, 2, /* P */
419 24, 2, /* mux */
420 BIT(31), /* gate */
425 * the mode switch. This means they have a 2x post divider between the clock
431 * The alternative would be to add the 2x multiplier when setting the MMC
434 static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x",
435 "pll-periph1-2x" };
439 16, 2, /* P */
440 24, 2, /* mux */
441 BIT(31), /* gate */
442 2, /* post-div */
448 16, 2, /* P */
449 24, 2, /* mux */
450 BIT(31), /* gate */
451 2, /* post-div */
457 16, 2, /* P */
458 24, 2, /* mux */
459 BIT(31), /* gate */
460 2, /* post-div */
463 static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
466 16, 2, /* P */
468 BIT(31), /* gate */
473 16, 2, /* P */
474 24, 2, /* mux */
475 BIT(31), /* gate */
480 16, 2, /* P */
481 24, 2, /* mux */
482 BIT(31), /* gate */
487 16, 2, /* P */
488 24, 2, /* mux */
489 BIT(31), /* gate */
492 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
493 "pll-audio-2x", "pll-audio" };
495 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
498 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
501 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
503 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
504 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
506 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
507 0x0cc, BIT(8), 0);
508 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
509 0x0cc, BIT(9), 0);
510 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
511 0x0cc, BIT(10), 0);
512 static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M",
513 0x0cc, BIT(11), 0);
514 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M",
515 0x0cc, BIT(16), 0);
516 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "usb-ohci0",
517 0x0cc, BIT(17), 0);
519 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
521 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
523 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
524 0x100, BIT(0), 0);
525 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
526 0x100, BIT(1), 0);
527 static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
528 0x100, BIT(2), 0);
529 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
530 0x100, BIT(3), 0);
532 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
534 0x104, 0, 4, 24, 3, BIT(31),
538 * Experiments showed that RGB output requires pll-video0-2x, while DSI
539 * requires pll-mipi. It will not work with incorrect clock, the screen will
541 * sun50i-a64.dtsi assigns pll-mipi as TCON0 parent by default
543 static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
544 static const u8 tcon0_table[] = { 0, 2, };
546 tcon0_table, 0x118, 24, 3, BIT(31),
549 static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
550 static const u8 tcon1_table[] = { 0, 2, };
554 24, 2, /* mux */
555 BIT(31), /* gate */
558 static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
560 0x124, 0, 4, 24, 3, BIT(31), 0);
562 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",
563 0x130, BIT(31), 0);
565 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
566 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
567 0x134, 16, 4, 24, 3, BIT(31), 0);
569 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1", "pll-periph1" };
570 static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
571 0x134, 0, 5, 8, 3, BIT(15), 0);
573 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
574 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
576 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
577 0x140, BIT(31), CLK_SET_RATE_PARENT);
579 static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x",
580 0x140, BIT(30), CLK_SET_RATE_PARENT);
583 0x144, BIT(31), 0);
585 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
587 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
589 static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
590 0x154, BIT(31), 0);
592 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
593 "pll-ddr0", "pll-ddr1" };
595 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
597 static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
598 static const u8 dsi_dphy_table[] = { 0, 2, };
599 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(dsi_dphy_clk, "dsi-dphy",
601 0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT);
603 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
604 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
607 static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
614 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
617 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
619 2, 1, CLK_SET_RATE_PARENT);
620 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
623 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
625 1, 2, CLK_SET_RATE_PARENT);
626 static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
628 1, 2, 0);
629 static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
631 1, 2, 0);
632 static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
634 1, 2, CLK_SET_RATE_PARENT);
862 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
863 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
864 [RST_USB_HSIC] = { 0x0cc, BIT(2) },
866 [RST_DRAM] = { 0x0f4, BIT(31) },
867 [RST_MBUS] = { 0x0fc, BIT(31) },
869 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
870 [RST_BUS_CE] = { 0x2c0, BIT(5) },
871 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
872 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
873 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
874 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
875 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
876 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
877 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
878 [RST_BUS_TS] = { 0x2c0, BIT(18) },
879 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
880 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
881 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
882 [RST_BUS_OTG] = { 0x2c0, BIT(23) },
883 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
884 [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
885 [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
886 [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
888 [RST_BUS_VE] = { 0x2c4, BIT(0) },
889 [RST_BUS_TCON0] = { 0x2c4, BIT(3) },
890 [RST_BUS_TCON1] = { 0x2c4, BIT(4) },
891 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
892 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
893 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
894 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
895 [RST_BUS_DE] = { 0x2c4, BIT(12) },
896 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
897 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
898 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
899 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
901 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
903 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
904 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
905 [RST_BUS_THS] = { 0x2d0, BIT(8) },
906 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
907 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
908 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
910 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
911 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
912 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
913 [RST_BUS_SCR] = { 0x2d8, BIT(5) },
914 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
915 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
916 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
917 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
918 [RST_BUS_UART4] = { 0x2d8, BIT(20) },
934 .enable = BIT(31),
935 .lock = BIT(28),
955 /* Force the PLL-Audio-1x divider to 1 */ in sun50i_a64_ccu_probe()
962 ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc); in sun50i_a64_ccu_probe()
977 { .compatible = "allwinner,sun50i-a64-ccu" },
985 .name = "sun50i-a64-ccu",