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/linux-6.14.4/drivers/clk/mediatek/
Dclk-mt7988-infracfg.c19 #define MT7988_INFRA_RST0_SET_OFFSET 0x70
20 #define MT7988_INFRA_RST1_SET_OFFSET 0x80
60 infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1, -1, -1, -1),
62 infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1, -1, -1, -1),
64 infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1, -1, -1, -1),
66 0x0018, 0x0010, 0x0014, 4, 1, -1, -1, -1),
68 0x0018, 0x0010, 0x0014, 5, 1, -1, -1, -1),
70 0x0018, 0x0010, 0x0014, 6, 1, -1, -1, -1),
71 MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x0018,
72 0x0010, 0x0014, 14, 2, -1, -1, -1),
[all …]
Dclk-mt7981-infracfg.c48 infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
51 infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
54 infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
57 infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1,
60 infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1,
63 infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1,
66 infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1,
69 infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1,
72 infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1,
75 infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
[all …]
Dclk-mt7986-infracfg.c41 infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
44 infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
47 infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
50 infra_spi_parents, 0x0018, 0x0010, 0x0014, 4, 1,
53 infra_spi_parents, 0x0018, 0x0010, 0x0014, 5, 1,
56 infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 9,
59 infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 11,
62 infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
66 infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
71 .set_ofs = 0x40,
[all …]
/linux-6.14.4/arch/arm/mach-omap2/
Dprcm_mpu44xx.h27 #define OMAP4430_PRCM_MPU_BASE 0x48243000
33 #define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000
34 #define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200
35 #define OMAP4430_PRCM_MPU_CPU0_INST 0x0400
36 #define OMAP4430_PRCM_MPU_CPU1_INST 0x0800
39 #define OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS 0x0018
40 #define OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS 0x0018
53 #define OMAP4_REVISION_PRCM_OFFSET 0x0000
54 … OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
57 #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
[all …]
Dprm2xxx.h35 #define OMAP2_PRCM_REVISION_OFFSET 0x0000
36 #define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
37 #define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010
38 #define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
40 #define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
41 #define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
42 #define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
43 #define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
45 #define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050
46 #define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
[all …]
Dcm33xx.h17 #define AM33XX_CM_BASE 0x44e00000
23 #define AM33XX_CM_PER_MOD 0x0000
24 #define AM33XX_CM_WKUP_MOD 0x0400
25 #define AM33XX_CM_DPLL_MOD 0x0500
26 #define AM33XX_CM_MPU_MOD 0x0600
27 #define AM33XX_CM_DEVICE_MOD 0x0700
28 #define AM33XX_CM_RTC_MOD 0x0800
29 #define AM33XX_CM_GFX_MOD 0x0900
30 #define AM33XX_CM_CEFUSE_MOD 0x0A00
33 #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
[all …]
Dprm44xx.h28 #define OMAP4430_PRM_BASE 0x4a306000
35 #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
36 #define OMAP4430_PRM_CKGEN_INST 0x0100
37 #define OMAP4430_PRM_MPU_INST 0x0300
38 #define OMAP4430_PRM_TESLA_INST 0x0400
39 #define OMAP4430_PRM_ABE_INST 0x0500
40 #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
41 #define OMAP4430_PRM_CORE_INST 0x0700
42 #define OMAP4430_PRM_IVAHD_INST 0x0f00
43 #define OMAP4430_PRM_CAM_INST 0x1000
[all …]
Dprm3xxx.h33 #define OMAP3_PRM_REVISION_OFFSET 0x0004
34 #define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
35 #define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
36 #define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
38 #define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
39 #define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
40 #define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
41 #define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
44 #define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
45 #define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
[all …]
/linux-6.14.4/arch/arm/boot/dts/ti/keystone/
Dkeystone-k2g-netcp.dtsi13 power-domains = <&k2g_pds 0x0018>;
14 clocks = <&k2g_clks 0x0018 0>;
17 queue-range = <0 0x80>;
18 linkram0 = <0x4020000 0x7ff>;
26 managed-queues = <0 0x80>;
27 reg = <0x4100000 0x800>,
28 <0x4040000 0x100>,
29 <0x4080000 0x800>,
30 <0x40c0000 0x800>;
38 qpend-0 {
[all …]
/linux-6.14.4/drivers/gpu/drm/ast/
Dast_dram_tables.h12 { 0x0108, 0x00000000 },
13 { 0x0120, 0x00004a21 },
14 { 0xFF00, 0x00000043 },
15 { 0x0000, 0xFFFFFFFF },
16 { 0x0004, 0x00000089 },
17 { 0x0008, 0x22331353 },
18 { 0x000C, 0x0d07000b },
19 { 0x0010, 0x11113333 },
20 { 0x0020, 0x00110350 },
21 { 0x0028, 0x1e0828f0 },
[all …]
/linux-6.14.4/drivers/dma/dw-edma/
Ddw-edma-v0-regs.h15 #define EDMA_V0_VIEWPORT_MASK GENMASK(2, 0)
16 #define EDMA_V0_DONE_INT_MASK GENMASK(7, 0)
18 #define EDMA_V0_WRITE_CH_COUNT_MASK GENMASK(3, 0)
21 #define EDMA_V0_DOORBELL_CH_MASK GENMASK(2, 0)
22 #define EDMA_V0_LINKED_LIST_ERR_MASK GENMASK(7, 0)
25 #define EDMA_V0_CH_EVEN_MSI_DATA_MASK GENMASK(15, 0)
28 u32 ch_control1; /* 0x0000 */
29 u32 ch_control2; /* 0x0004 */
30 u32 transfer_size; /* 0x0008 */
32 u64 reg; /* 0x000c..0x0010 */
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/spl/
Ddc_spl_scl_filters.c11 // <sharpness> = 0
17 0x1000, 0x0000,
18 0x0FF0, 0x0010,
19 0x0FB0, 0x0050,
20 0x0F34, 0x00CC,
21 0x0E68, 0x0198,
22 0x0D44, 0x02BC,
23 0x0BC4, 0x043C,
24 0x09FC, 0x0604,
25 0x0800, 0x0800
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/dce/
Ddce_scl_filters.c31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
[all …]
/linux-6.14.4/drivers/gpu/drm/lima/
Dlima_regs.h14 #define LIMA_PMU_POWER_UP 0x00
15 #define LIMA_PMU_POWER_DOWN 0x04
16 #define LIMA_PMU_POWER_GP0_MASK BIT(0)
29 #define LIMA_PMU_STATUS 0x08
30 #define LIMA_PMU_INT_MASK 0x0C
31 #define LIMA_PMU_INT_RAWSTAT 0x10
32 #define LIMA_PMU_INT_CLEAR 0x18
33 #define LIMA_PMU_INT_CMD_MASK BIT(0)
34 #define LIMA_PMU_SW_DELAY 0x1C
37 #define LIMA_L2_CACHE_SIZE 0x0004
[all …]
/linux-6.14.4/arch/arm/boot/dts/nxp/imx/
Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_6_1_offset.h27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
/linux-6.14.4/include/linux/platform_data/
Dgpio-omap.h18 #define OMAP1_MPUIO_BASE 0xfffb5000
24 #define OMAP_MPUIO_INPUT_LATCH 0x00
25 #define OMAP_MPUIO_OUTPUT 0x04
26 #define OMAP_MPUIO_IO_CNTL 0x08
27 #define OMAP_MPUIO_KBR_LATCH 0x10
28 #define OMAP_MPUIO_KBC 0x14
29 #define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
30 #define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
31 #define OMAP_MPUIO_KBD_INT 0x20
32 #define OMAP_MPUIO_GPIO_INT 0x24
[all …]
/linux-6.14.4/drivers/tty/serial/
Ddz.h18 #define DZ_TRDY 0x8000 /* Transmitter empty */
19 #define DZ_TIE 0x4000 /* Transmitter Interrupt Enbl */
20 #define DZ_TLINE 0x0300 /* Transmitter Line Number */
21 #define DZ_RDONE 0x0080 /* Receiver data ready */
22 #define DZ_RIE 0x0040 /* Receive Interrupt Enable */
23 #define DZ_MSE 0x0020 /* Master Scan Enable */
24 #define DZ_CLR 0x0010 /* Master reset */
25 #define DZ_MAINT 0x0008 /* Loop Back Mode */
30 #define DZ_RBUF_MASK 0x00FF /* Data Mask */
31 #define DZ_LINE_MASK 0x0300 /* Line Mask */
[all …]
/linux-6.14.4/arch/arm64/boot/dts/freescale/
Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
/linux-6.14.4/drivers/media/usb/gspca/
Dspca508.c23 #define CreativeVista 0
51 .priv = 0},
62 {0x0000, 0x870b},
64 {0x0020, 0x8112}, /* Video drop enable, ISO streaming disable */
65 {0x0003, 0x8111}, /* Reset compression & memory */
66 {0x0000, 0x8110}, /* Disable all outputs */
67 /* READ {0x0000, 0x8114} -> 0000: 00 */
68 {0x0000, 0x8114}, /* SW GPIO data */
69 {0x0008, 0x8110}, /* Enable charge pump output */
70 {0x0002, 0x8116}, /* 200 kHz pump clock */
[all …]
/linux-6.14.4/drivers/scsi/isci/
Dregisters.h66 #define SCU_VIIT_ENTRY_ID_MASK (0xC0000000)
69 #define SCU_VIIT_ENTRY_FUNCTION_MASK (0x0FF00000)
72 #define SCU_VIIT_ENTRY_IPPTMODE_MASK (0x0001F800)
75 #define SCU_VIIT_ENTRY_LPVIE_MASK (0x00000F00)
78 #define SCU_VIIT_ENTRY_STATUS_MASK (0x000000FF)
79 #define SCU_VIIT_ENTRY_STATUS_SHIFT (0)
81 #define SCU_VIIT_ENTRY_ID_INVALID (0 << SCU_VIIT_ENTRY_ID_SHIFT)
86 #define SCU_VIIT_IPPT_SSP_INITIATOR (0x01 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
87 #define SCU_VIIT_IPPT_SMP_INITIATOR (0x02 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
88 #define SCU_VIIT_IPPT_STP_INITIATOR (0x04 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
[all …]
/linux-6.14.4/drivers/ntb/hw/intel/
Dntb_hw_gen1.h50 #define XEON_PBAR23LMT_OFFSET 0x0000
51 #define XEON_PBAR45LMT_OFFSET 0x0008
52 #define XEON_PBAR4LMT_OFFSET 0x0008
53 #define XEON_PBAR5LMT_OFFSET 0x000c
54 #define XEON_PBAR23XLAT_OFFSET 0x0010
55 #define XEON_PBAR45XLAT_OFFSET 0x0018
56 #define XEON_PBAR4XLAT_OFFSET 0x0018
57 #define XEON_PBAR5XLAT_OFFSET 0x001c
58 #define XEON_SBAR23LMT_OFFSET 0x0020
59 #define XEON_SBAR45LMT_OFFSET 0x0028
[all …]
/linux-6.14.4/drivers/net/ethernet/qualcomm/emac/
Demac-sgmii-qdf2400.c12 #define EMAC_SGMII_PHY_TX_PWR_CTRL 0x000C
13 #define EMAC_SGMII_PHY_LANE_CTRL1 0x0018
14 #define EMAC_SGMII_PHY_CDR_CTRL0 0x0058
15 #define EMAC_SGMII_PHY_POW_DWN_CTRL0 0x0080
16 #define EMAC_SGMII_PHY_RESET_CTRL 0x00a8
17 #define EMAC_SGMII_PHY_INTERRUPT_MASK 0x00b4
20 #define EMAC_SGMII_LN_DRVR_CTRL0 0x000C
21 #define EMAC_SGMII_LN_DRVR_CTRL1 0x0010
22 #define EMAC_SGMII_LN_DRVR_TAP_EN 0x0018
23 #define EMAC_SGMII_LN_TX_MARGINING 0x001C
[all …]
Demac-sgmii-qdf2432.c12 #define EMAC_SGMII_PHY_TX_PWR_CTRL 0x000C
13 #define EMAC_SGMII_PHY_LANE_CTRL1 0x0018
14 #define EMAC_SGMII_PHY_CDR_CTRL0 0x0058
15 #define EMAC_SGMII_PHY_POW_DWN_CTRL0 0x0080
16 #define EMAC_SGMII_PHY_RESET_CTRL 0x00a8
17 #define EMAC_SGMII_PHY_INTERRUPT_MASK 0x00b4
20 #define EMAC_SGMII_LN_DRVR_CTRL0 0x000C
21 #define EMAC_SGMII_LN_DRVR_TAP_EN 0x0018
22 #define EMAC_SGMII_LN_TX_MARGINING 0x001C
23 #define EMAC_SGMII_LN_TX_PRE 0x0020
[all …]

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