Lines Matching +full:0 +full:x0018
50 #define XEON_PBAR23LMT_OFFSET 0x0000
51 #define XEON_PBAR45LMT_OFFSET 0x0008
52 #define XEON_PBAR4LMT_OFFSET 0x0008
53 #define XEON_PBAR5LMT_OFFSET 0x000c
54 #define XEON_PBAR23XLAT_OFFSET 0x0010
55 #define XEON_PBAR45XLAT_OFFSET 0x0018
56 #define XEON_PBAR4XLAT_OFFSET 0x0018
57 #define XEON_PBAR5XLAT_OFFSET 0x001c
58 #define XEON_SBAR23LMT_OFFSET 0x0020
59 #define XEON_SBAR45LMT_OFFSET 0x0028
60 #define XEON_SBAR4LMT_OFFSET 0x0028
61 #define XEON_SBAR5LMT_OFFSET 0x002c
62 #define XEON_SBAR23XLAT_OFFSET 0x0030
63 #define XEON_SBAR45XLAT_OFFSET 0x0038
64 #define XEON_SBAR4XLAT_OFFSET 0x0038
65 #define XEON_SBAR5XLAT_OFFSET 0x003c
66 #define XEON_SBAR0BASE_OFFSET 0x0040
67 #define XEON_SBAR23BASE_OFFSET 0x0048
68 #define XEON_SBAR45BASE_OFFSET 0x0050
69 #define XEON_SBAR4BASE_OFFSET 0x0050
70 #define XEON_SBAR5BASE_OFFSET 0x0054
71 #define XEON_SBDF_OFFSET 0x005c
72 #define XEON_NTBCNTL_OFFSET 0x0058
73 #define XEON_PDOORBELL_OFFSET 0x0060
74 #define XEON_PDBMSK_OFFSET 0x0062
75 #define XEON_SDOORBELL_OFFSET 0x0064
76 #define XEON_SDBMSK_OFFSET 0x0066
77 #define XEON_USMEMMISS_OFFSET 0x0070
78 #define XEON_SPAD_OFFSET 0x0080
79 #define XEON_PBAR23SZ_OFFSET 0x00d0
80 #define XEON_PBAR45SZ_OFFSET 0x00d1
81 #define XEON_PBAR4SZ_OFFSET 0x00d1
82 #define XEON_SBAR23SZ_OFFSET 0x00d2
83 #define XEON_SBAR45SZ_OFFSET 0x00d3
84 #define XEON_SBAR4SZ_OFFSET 0x00d3
85 #define XEON_PPD_OFFSET 0x00d4
86 #define XEON_PBAR5SZ_OFFSET 0x00d5
87 #define XEON_SBAR5SZ_OFFSET 0x00d6
88 #define XEON_WCCNTRL_OFFSET 0x00e0
89 #define XEON_UNCERRSTS_OFFSET 0x014c
90 #define XEON_CORERRSTS_OFFSET 0x0158
91 #define XEON_LINK_STATUS_OFFSET 0x01a2
92 #define XEON_SPCICMD_OFFSET 0x0504
93 #define XEON_DEVCTRL_OFFSET 0x0598
94 #define XEON_DEVSTS_OFFSET 0x059a
95 #define XEON_SLINK_STATUS_OFFSET 0x05a2
96 #define XEON_B2B_SPAD_OFFSET 0x0100
97 #define XEON_B2B_DOORBELL_OFFSET 0x0140
98 #define XEON_B2B_XLAT_OFFSETL 0x0144
99 #define XEON_B2B_XLAT_OFFSETU 0x0148
100 #define XEON_PPD_CONN_MASK 0x03
101 #define XEON_PPD_CONN_TRANSPARENT 0x00
102 #define XEON_PPD_CONN_B2B 0x01
103 #define XEON_PPD_CONN_RP 0x02
104 #define XEON_PPD_DEV_MASK 0x10
105 #define XEON_PPD_DEV_USD 0x00
106 #define XEON_PPD_DEV_DSD 0x10
107 #define XEON_PPD_SPLIT_BAR_MASK 0x40
129 #define XEON_B2B_BAR0_ADDR 0x1000000000000000ull
130 #define XEON_B2B_BAR2_ADDR64 0x2000000000000000ull
131 #define XEON_B2B_BAR4_ADDR64 0x4000000000000000ull
132 #define XEON_B2B_BAR4_ADDR32 0x20000000u
133 #define XEON_B2B_BAR5_ADDR32 0x40000000u
136 #define XEON_B2B_MIN_SIZE 0x8000
139 #define NTB_HWERR_SDOORBELL_LOCKUP BIT_ULL(0)