Lines Matching +full:0 +full:x0018

19 #define	MT7988_INFRA_RST0_SET_OFFSET	0x70
20 #define	MT7988_INFRA_RST1_SET_OFFSET	0x80
60 			     infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1, -1, -1, -1),
62 			     infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1, -1, -1, -1),
64 			     infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1, -1, -1, -1),
66 			     0x0018, 0x0010, 0x0014, 4, 1, -1, -1, -1),
68 			     0x0018, 0x0010, 0x0014, 5, 1, -1, -1, -1),
70 			     0x0018, 0x0010, 0x0014, 6, 1, -1, -1, -1),
71 	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x0018,
72 			     0x0010, 0x0014, 14, 2, -1, -1, -1),
74 			     0x0018, 0x0010, 0x0014, 16, 2, -1, -1, -1),
76 			     0x0018, 0x0010, 0x0014, 18, 2, -1, -1, -1),
78 			     0x0018, 0x0010, 0x0014, 20, 2, -1, -1, -1),
80 			     0x0018, 0x0010, 0x0014, 22, 2, -1, -1, -1),
82 			     0x0018, 0x0010, 0x0014, 24, 2, -1, -1, -1),
84 			     0x0018, 0x0010, 0x0014, 26, 2, -1, -1, -1),
86 			     0x0018, 0x0010, 0x0014, 28, 2, -1, -1, -1),
88 			     0x0018, 0x0010, 0x0014, 30, 2, -1, -1, -1),
91 			     infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, 0x0020, 0x0024, 0, 2, -1,
94 			     infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, 0x0020, 0x0024, 2, 2, -1,
97 			     infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, 0x0020, 0x0024, 4, 2, -1,
100 			     infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, 0x0020, 0x0024, 6, 2, -1,
105 	.set_ofs = 0x10,
106 	.clr_ofs = 0x14,
107 	.sta_ofs = 0x18,
111 	.set_ofs = 0x40,
112 	.clr_ofs = 0x44,
113 	.sta_ofs = 0x48,
117 	.set_ofs = 0x50,
118 	.clr_ofs = 0x54,
119 	.sta_ofs = 0x58,
123 	.set_ofs = 0x60,
124 	.clr_ofs = 0x64,
125 	.sta_ofs = 0x68,
144 #define GATE_INFRA0(_id, _name, _parent, _shift) GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0)
146 #define GATE_INFRA1(_id, _name, _parent, _shift) GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
148 #define GATE_INFRA2(_id, _name, _parent, _shift) GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0)
150 #define GATE_INFRA3(_id, _name, _parent, _shift) GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
163 	GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", "sysaxi_sel", 0),
190 		    0),
220 	GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel", 0),
262 	[MT7988_INFRA_RST0_PEXTP_MAC_SWRST] = 0 * RST_NR_PER_BANK + 6,