Lines Matching +full:0 +full:x0018
12 #define EMAC_SGMII_PHY_TX_PWR_CTRL 0x000C
13 #define EMAC_SGMII_PHY_LANE_CTRL1 0x0018
14 #define EMAC_SGMII_PHY_CDR_CTRL0 0x0058
15 #define EMAC_SGMII_PHY_POW_DWN_CTRL0 0x0080
16 #define EMAC_SGMII_PHY_RESET_CTRL 0x00a8
17 #define EMAC_SGMII_PHY_INTERRUPT_MASK 0x00b4
20 #define EMAC_SGMII_LN_DRVR_CTRL0 0x000C
21 #define EMAC_SGMII_LN_DRVR_TAP_EN 0x0018
22 #define EMAC_SGMII_LN_TX_MARGINING 0x001C
23 #define EMAC_SGMII_LN_TX_PRE 0x0020
24 #define EMAC_SGMII_LN_TX_POST 0x0024
25 #define EMAC_SGMII_LN_TX_BAND_MODE 0x0060
26 #define EMAC_SGMII_LN_LANE_MODE 0x0064
27 #define EMAC_SGMII_LN_PARALLEL_RATE 0x0078
28 #define EMAC_SGMII_LN_CML_CTRL_MODE0 0x00B8
29 #define EMAC_SGMII_LN_MIXER_CTRL_MODE0 0x00D0
30 #define EMAC_SGMII_LN_VGA_INITVAL 0x0134
31 #define EMAC_SGMII_LN_UCDR_FO_GAIN_MODE0 0x017C
32 #define EMAC_SGMII_LN_UCDR_SO_GAIN_MODE0 0x0188
33 #define EMAC_SGMII_LN_UCDR_SO_CONFIG 0x0194
34 #define EMAC_SGMII_LN_RX_BAND 0x019C
35 #define EMAC_SGMII_LN_RX_RCVR_PATH1_MODE0 0x01B8
36 #define EMAC_SGMII_LN_RSM_CONFIG 0x01F0
37 #define EMAC_SGMII_LN_SIGDET_ENABLES 0x0224
38 #define EMAC_SGMII_LN_SIGDET_CNTRL 0x0228
39 #define EMAC_SGMII_LN_SIGDET_DEGLITCH_CNTRL 0x022C
40 #define EMAC_SGMII_LN_RX_EN_SIGNAL 0x02A0
41 #define EMAC_SGMII_LN_RX_MISC_CNTRL0 0x02AC
42 #define EMAC_SGMII_LN_DRVR_LOGIC_CLKDIV 0x02BC
46 #define UCDR_xO_GAIN_MODE(x) ((x) & 0x7f)
48 #define UCDR_SO_SATURATION(x) ((x) & 0x3f)
54 #define KR_PCIGEN3_MODE BIT(0)
56 #define MAIN_EN BIT(0)
59 #define TX_MARGINING(x) ((x) & 0x3f)
68 #define MIXER_LOADB_MODE(x) (((x) & 0xf) << 2)
71 #define VGA_THRESH_DFE(x) ((x) & 0x3f)
74 #define SIGDET_FLT_BYP BIT(0)
76 #define SIGDET_LVL(x) (((x) & 0xf) << 4)
78 #define SIGDET_DEGLITCH_CTRL(x) (((x) & 0xf) << 1)
81 #define DRVR_LOGIC_CLK_DIV(x) ((x) & 0xf)
83 #define PARALLEL_RATE_MODE0(x) ((x) & 0x3)
85 #define BAND_MODE0(x) ((x) & 0x3)
87 #define LANE_MODE(x) ((x) & 0x1f)
89 #define CDR_PD_SEL_MODE0(x) (((x) & 0x3) << 5)
91 #define BYPASS_RSM_DLL_CAL BIT(0)
95 #define PWRDN_B BIT(0)
97 #define CDR_MAX_CNT(x) ((x) & 0xff)
111 for (i = 0; i < size; ++itr, ++i) in emac_reg_write_all()
119 {EMAC_SGMII_LN_UCDR_SO_GAIN_MODE0, UCDR_xO_GAIN_MODE(0)},
141 {EMAC_SGMII_LN_RX_MISC_CNTRL0, 0},
156 {EMAC_SGMII_PHY_TX_PWR_CTRL, 0},
177 writel(0, phy_regs + EMAC_SGMII_PHY_RESET_CTRL); in emac_sgmii_init_qdf2432()
181 for (i = 0; i < SERDES_START_WAIT_TIMES; i++) { in emac_sgmii_init_qdf2432()
194 writel(0, phy_regs + SGMII_PHY_LN_BIST_GEN0); in emac_sgmii_init_qdf2432()
195 writel(0, phy_regs + SGMII_PHY_LN_BIST_GEN2); in emac_sgmii_init_qdf2432()
196 writel(0, phy_regs + SGMII_PHY_LN_CDR_CTRL1); in emac_sgmii_init_qdf2432()
199 writel(0, phy_regs + EMAC_SGMII_PHY_INTERRUPT_MASK); in emac_sgmii_init_qdf2432()
201 return 0; in emac_sgmii_init_qdf2432()