Lines Matching +full:0 +full:x0018
12 #define EMAC_SGMII_PHY_TX_PWR_CTRL 0x000C
13 #define EMAC_SGMII_PHY_LANE_CTRL1 0x0018
14 #define EMAC_SGMII_PHY_CDR_CTRL0 0x0058
15 #define EMAC_SGMII_PHY_POW_DWN_CTRL0 0x0080
16 #define EMAC_SGMII_PHY_RESET_CTRL 0x00a8
17 #define EMAC_SGMII_PHY_INTERRUPT_MASK 0x00b4
20 #define EMAC_SGMII_LN_DRVR_CTRL0 0x000C
21 #define EMAC_SGMII_LN_DRVR_CTRL1 0x0010
22 #define EMAC_SGMII_LN_DRVR_TAP_EN 0x0018
23 #define EMAC_SGMII_LN_TX_MARGINING 0x001C
24 #define EMAC_SGMII_LN_TX_PRE 0x0020
25 #define EMAC_SGMII_LN_TX_POST 0x0024
26 #define EMAC_SGMII_LN_TX_BAND_MODE 0x0060
27 #define EMAC_SGMII_LN_LANE_MODE 0x0064
28 #define EMAC_SGMII_LN_PARALLEL_RATE 0x007C
29 #define EMAC_SGMII_LN_CML_CTRL_MODE0 0x00C0
30 #define EMAC_SGMII_LN_MIXER_CTRL_MODE0 0x00D8
31 #define EMAC_SGMII_LN_VGA_INITVAL 0x013C
32 #define EMAC_SGMII_LN_UCDR_FO_GAIN_MODE0 0x0184
33 #define EMAC_SGMII_LN_UCDR_SO_GAIN_MODE0 0x0190
34 #define EMAC_SGMII_LN_UCDR_SO_CONFIG 0x019C
35 #define EMAC_SGMII_LN_RX_BAND 0x01A4
36 #define EMAC_SGMII_LN_RX_RCVR_PATH1_MODE0 0x01C0
37 #define EMAC_SGMII_LN_RSM_CONFIG 0x01F8
38 #define EMAC_SGMII_LN_SIGDET_ENABLES 0x0230
39 #define EMAC_SGMII_LN_SIGDET_CNTRL 0x0234
40 #define EMAC_SGMII_LN_SIGDET_DEGLITCH_CNTRL 0x0238
41 #define EMAC_SGMII_LN_RX_EN_SIGNAL 0x02AC
42 #define EMAC_SGMII_LN_RX_MISC_CNTRL0 0x02B8
43 #define EMAC_SGMII_LN_DRVR_LOGIC_CLKDIV 0x02C8
44 #define EMAC_SGMII_LN_RX_RESECODE_OFFSET 0x02CC
48 #define UCDR_xO_GAIN_MODE(x) ((x) & 0x7f)
50 #define UCDR_SO_SATURATION(x) ((x) & 0x3f)
56 #define KR_PCIGEN3_MODE BIT(0)
58 #define MAIN_EN BIT(0)
61 #define TX_MARGINING(x) ((x) & 0x3f)
70 #define RESCODE_OFFSET(x) ((x) & 0x1f)
72 #define MIXER_LOADB_MODE(x) (((x) & 0xf) << 2)
75 #define VGA_THRESH_DFE(x) ((x) & 0x3f)
78 #define SIGDET_FLT_BYP BIT(0)
80 #define SIGDET_LVL(x) (((x) & 0xf) << 4)
82 #define SIGDET_DEGLITCH_CTRL(x) (((x) & 0xf) << 1)
87 #define DRVR_LOGIC_CLK_DIV(x) ((x) & 0xf)
89 #define PARALLEL_RATE_MODE0(x) ((x) & 0x3)
91 #define BAND_MODE0(x) ((x) & 0x3)
93 #define LANE_MODE(x) ((x) & 0x1f)
95 #define CDR_PD_SEL_MODE0(x) (((x) & 0x3) << 5)
101 #define BYPASS_RSM_DLL_CAL BIT(0)
105 #define PWRDN_B BIT(0)
107 #define CDR_MAX_CNT(x) ((x) & 0xff)
121 for (i = 0; i < size; ++itr, ++i) in emac_reg_write_all()
129 {EMAC_SGMII_LN_UCDR_SO_GAIN_MODE0, UCDR_xO_GAIN_MODE(0)},
169 {EMAC_SGMII_PHY_TX_PWR_CTRL, 0},
190 writel(0, phy_regs + EMAC_SGMII_PHY_RESET_CTRL); in emac_sgmii_init_qdf2400()
194 for (i = 0; i < SERDES_START_WAIT_TIMES; i++) { in emac_sgmii_init_qdf2400()
207 writel(0, phy_regs + SGMII_PHY_LN_BIST_GEN0); in emac_sgmii_init_qdf2400()
208 writel(0, phy_regs + SGMII_PHY_LN_BIST_GEN2); in emac_sgmii_init_qdf2400()
209 writel(0, phy_regs + SGMII_PHY_LN_CDR_CTRL1); in emac_sgmii_init_qdf2400()
212 writel(0, phy_regs + EMAC_SGMII_PHY_INTERRUPT_MASK); in emac_sgmii_init_qdf2400()
214 return 0; in emac_sgmii_init_qdf2400()