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12

/linux-6.14.4/arch/arm/boot/dts/nvidia/
Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi13 emc-timings-0 {
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
19 nvidia,emc-mode-2 = <0x80200018>;
20 nvidia,emc-mode-reset = <0x80000b71>;
21 nvidia,emc-zcal-cnt-long = <0x00000040>;
25 0x0000001f /* EMC_RC */
26 0x00000069 /* EMC_RFC */
27 0x00000017 /* EMC_RAS */
28 0x00000007 /* EMC_RP */
[all …]
Dtegra30-asus-tf300t.dts75 reg = <0x10>;
94 mount-matrix = "0", "-1", "0",
95 "-1", "0", "0",
96 "0", "0", "-1";
100 mount-matrix = "-1", "0", "0",
101 "0", "1", "0",
102 "0", "0", "-1";
107 mount-matrix = "0", "-1", "0",
108 "-1", "0", "0",
109 "0", "0", "1";
[all …]
Dtegra30-asus-tf300tg.dts22 <TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>,
171 reg = <0x10>;
190 mount-matrix = "1", "0", "0",
191 "0", "-1", "0",
192 "0", "0", "-1";
196 mount-matrix = "-1", "0", "0",
197 "0", "1", "0",
198 "0", "0", "-1";
203 mount-matrix = "0", "-1", "0",
204 "-1", "0", "0",
[all …]
Dtegra30-asus-nexus7-grouper-memory-timings.dtsi5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
12 0x00020001 /* MC_EMEM_ARB_CFG */
13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
15 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
16 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
17 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
18 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
19 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
[all …]
/linux-6.14.4/sound/soc/codecs/
Dcs35l36.h16 #define CS35L36_FIRSTREG 0x00000000
17 #define CS35L36_LASTREG 0x00E037FC
18 #define CS35L36_SW_RESET 0x00000000
19 #define CS35L36_SW_REV 0x00000004
20 #define CS35L36_HW_REV 0x00000008
21 #define CS35L36_TESTKEY_CTRL 0x00000020
22 #define CS35L36_USERKEY_CTL 0x00000024
23 #define CS35L36_OTP_MEM30 0x00000478
24 #define CS35L36_OTP_CTRL1 0x00000500
25 #define CS35L36_OTP_CTRL2 0x00000504
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra30-emc.yaml35 const: 0
53 "^emc-timings-[0-9]+$":
62 "^timing-[0-9]+$":
75 minimum: 0
91 Mode Register 0.
98 minimum: 0
239 reg = <0x7000f400 0x400>;
240 interrupts = <0 78 4>;
247 #interconnect-cells = <0>;
255 nvidia,emc-auto-cal-interval = <0x001fffff>;
[all …]
/linux-6.14.4/drivers/net/wireless/ath/ath11k/
Dhw.c21 case 0: in ath11k_hw_ipq8074_mac_from_pdev_id()
22 return 0; in ath11k_hw_ipq8074_mac_from_pdev_id()
71 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; in ath11k_init_wmi_config_qca6390()
80 config->num_mcast_groups = 0; in ath11k_init_wmi_config_qca6390()
81 config->num_mcast_table_elems = 0; in ath11k_init_wmi_config_qca6390()
82 config->mcast2ucast_mode = 0; in ath11k_init_wmi_config_qca6390()
84 config->num_wds_entries = 0; in ath11k_init_wmi_config_qca6390()
85 config->dma_burst_size = 0; in ath11k_init_wmi_config_qca6390()
86 config->rx_skip_defrag_timeout_dup_detection_check = 0; in ath11k_init_wmi_config_qca6390()
89 config->num_msdu_desc = 0x400; in ath11k_init_wmi_config_qca6390()
[all …]
/linux-6.14.4/drivers/net/ipa/reg/
Dipa_reg-v3.1.c13 [COMP_CFG_ENABLE] = BIT(0),
21 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
24 [CLKON_RX] = BIT(0),
44 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
47 [ROUTE_DIS] = BIT(0),
57 REG_FIELDS(ROUTE, route, 0x00000048);
60 [MEM_SIZE] = GENMASK(15, 0),
64 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
67 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
72 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
[all …]
Dipa_reg-v3.5.1.c13 [COMP_CFG_ENABLE] = BIT(0),
21 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
24 [CLKON_RX] = BIT(0),
49 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
52 [ROUTE_DIS] = BIT(0),
62 REG_FIELDS(ROUTE, route, 0x00000048);
65 [MEM_SIZE] = GENMASK(15, 0),
69 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
72 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
77 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
[all …]
Dipa_reg-v4.2.c13 /* Bit 0 reserved */
34 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
37 [CLKON_RX] = BIT(0),
70 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
73 [ROUTE_DIS] = BIT(0),
83 REG_FIELDS(ROUTE, route, 0x00000048);
86 [MEM_SIZE] = GENMASK(15, 0),
90 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
93 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
98 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
[all …]
Dipa_reg-v4.5.c13 /* Bit 0 reserved */
35 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
38 [CLKON_RX] = BIT(0),
72 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
75 [ROUTE_DIS] = BIT(0),
85 REG_FIELDS(ROUTE, route, 0x00000048);
88 [MEM_SIZE] = GENMASK(15, 0),
92 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
95 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
100 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
[all …]
Dipa_reg-v4.7.c13 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
35 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
38 [CLKON_RX] = BIT(0),
72 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
75 [ROUTE_DIS] = BIT(0),
85 REG_FIELDS(ROUTE, route, 0x00000048);
88 [MEM_SIZE] = GENMASK(15, 0),
92 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
95 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
100 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
[all …]
Dipa_reg-v4.11.c13 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
41 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
44 [CLKON_RX] = BIT(0),
78 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
81 [ROUTE_DIS] = BIT(0),
91 REG_FIELDS(ROUTE, route, 0x00000048);
94 [MEM_SIZE] = GENMASK(15, 0),
98 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
101 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
106 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
[all …]
Dipa_reg-v4.9.c13 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
40 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
43 [CLKON_RX] = BIT(0),
77 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
80 [ROUTE_DIS] = BIT(0),
90 REG_FIELDS(ROUTE, route, 0x00000048);
93 [MEM_SIZE] = GENMASK(15, 0),
97 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
100 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
105 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
[all …]
Dipa_reg-v5.0.c13 [MAX_PIPES] = GENMASK(7, 0),
19 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000000);
22 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
50 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000002c);
53 [CLKON_RX] = BIT(0),
87 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000034);
90 [ROUTE_DEF_PIPE] = GENMASK(7, 0),
99 REG_FIELDS(ROUTE, route, 0x00000038);
102 [MEM_SIZE] = GENMASK(15, 0),
106 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000040);
[all …]
Dipa_reg-v5.5.c13 [MAX_PIPES] = GENMASK(7, 0),
19 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000000);
22 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
49 REG_FIELDS(COMP_CFG, comp_cfg, 0x00000048);
52 [CLKON_RX] = BIT(0),
86 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000050);
89 [ROUTE_DEF_PIPE] = GENMASK(7, 0),
98 REG_FIELDS(ROUTE, route, 0x00000054);
101 [MEM_SIZE] = GENMASK(15, 0),
105 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x0000005c);
[all …]
/linux-6.14.4/sound/pci/cs46xx/
Dcs46xx.h25 #define BA0_HISR 0x00000000
26 #define BA0_HSR0 0x00000004
27 #define BA0_HICR 0x00000008
28 #define BA0_DMSR 0x00000100
29 #define BA0_HSAR 0x00000110
30 #define BA0_HDAR 0x00000114
31 #define BA0_HDMR 0x00000118
32 #define BA0_HDCR 0x0000011C
33 #define BA0_PFMC 0x00000200
34 #define BA0_PFCV1 0x00000204
[all …]
/linux-6.14.4/include/sound/
Dcs35l41.h16 #define CS35L41_FIRSTREG 0x00000000
17 #define CS35L41_LASTREG 0x03804FE8
18 #define CS35L41_DEVID 0x00000000
19 #define CS35L41_REVID 0x00000004
20 #define CS35L41_FABID 0x00000008
21 #define CS35L41_RELID 0x0000000C
22 #define CS35L41_OTPID 0x00000010
23 #define CS35L41_SFT_RESET 0x00000020
24 #define CS35L41_TEST_KEY_CTL 0x00000040
25 #define CS35L41_USER_KEY_CTL 0x00000044
[all …]
/linux-6.14.4/drivers/video/fbdev/riva/
Driva_hw.c65 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || in nv3Busy()
66 NV_RD32(&chip->PGRAPH[0x000006B0/4], 0) & 0x01); in nv3Busy()
73 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || in nv4Busy()
74 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); in nv4Busy()
81 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || in nv10Busy()
82 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); in nv10Busy()
92 VGA_WR08(chip->PCIO, 0x3D4, 0x11); in vgaLockUnlock()
93 cr11 = VGA_RD08(chip->PCIO, 0x3D5); in vgaLockUnlock()
94 if(Lock) cr11 |= 0x80; in vgaLockUnlock()
95 else cr11 &= ~0x80; in vgaLockUnlock()
[all …]
/linux-6.14.4/drivers/gpu/drm/rockchip/
Drockchip_vop_reg.h11 #define RK3288_REG_CFG_DONE 0x0000
12 #define RK3288_VERSION_INFO 0x0004
13 #define RK3288_SYS_CTRL 0x0008
14 #define RK3288_SYS_CTRL1 0x000c
15 #define RK3288_DSP_CTRL0 0x0010
16 #define RK3288_DSP_CTRL1 0x0014
17 #define RK3288_DSP_BG 0x0018
18 #define RK3288_MCU_CTRL 0x001c
19 #define RK3288_INTR_CTRL0 0x0020
20 #define RK3288_INTR_CTRL1 0x0024
[all …]
/linux-6.14.4/drivers/net/wireless/ath/ath12k/
Dhw.c18 static const guid_t wcn7850_uuid = GUID_INIT(0xf634f534, 0x6147, 0x11ec,
19 0x90, 0xd6, 0x02, 0x42,
20 0xac, 0x12, 0x00, 0x03);
36 return 0; in ath12k_hw_mac_id_to_srng_id_qcn9274()
55 return 0; in ath12k_hw_mac_id_to_pdev_id_wcn7850()
71 if (ring_num == 0 || ring_num == 2 || ring_num == 4) in ath12k_dp_srng_is_comp_ring_wcn7850()
95 #define ATH12K_TX_RING_MASK_0 0x1
96 #define ATH12K_TX_RING_MASK_1 0x2
97 #define ATH12K_TX_RING_MASK_2 0x4
98 #define ATH12K_TX_RING_MASK_3 0x8
[all …]
/linux-6.14.4/drivers/net/ethernet/xilinx/
Dxilinx_axienet.h32 #define XAE_OPTION_PROMISC BIT(0)
75 #define XAXIDMA_TX_CR_OFFSET 0x00000000 /* Channel control */
76 #define XAXIDMA_TX_SR_OFFSET 0x00000004 /* Status */
77 #define XAXIDMA_TX_CDESC_OFFSET 0x00000008 /* Current descriptor pointer */
78 #define XAXIDMA_TX_TDESC_OFFSET 0x00000010 /* Tail descriptor pointer */
80 #define XAXIDMA_RX_CR_OFFSET 0x00000030 /* Channel control */
81 #define XAXIDMA_RX_SR_OFFSET 0x00000034 /* Status */
82 #define XAXIDMA_RX_CDESC_OFFSET 0x00000038 /* Current descriptor pointer */
83 #define XAXIDMA_RX_TDESC_OFFSET 0x00000040 /* Tail descriptor pointer */
85 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dpp_overdriver.c28 …{ 0x0213EA94DE0E4964, 0x00003C96, 0xFFFFE226, 0x00000656, 0x00002203, 0xFFFFF201, 0x000003FF, 0x00…
29 …{ 0x0213EA94DE0A1884, 0x00003CC5, 0xFFFFE23A, 0x0000064E, 0x00002258, 0xFFFFF1F7, 0x000003FC, 0x00…
30 …{ 0x0213EA94DE0E31A4, 0x00003CAF, 0xFFFFE36E, 0x00000602, 0x00001E98, 0xFFFFF569, 0x00000357, 0x00…
31 …{ 0x0213EA94DE2C1144, 0x0000391A, 0xFFFFE548, 0x000005C9, 0x00001B98, 0xFFFFF707, 0x00000324, 0x00…
32 …{ 0x0213EA94DE2C18C4, 0x00003821, 0xFFFFE674, 0x00000597, 0x00002196, 0xFFFFF361, 0x000003C0, 0x00…
33 …{ 0x0213EA94DE263884, 0x000044A2, 0xFFFFDCB7, 0x00000738, 0x0000325C, 0xFFFFE6A7, 0x000005E6, 0x00…
34 …{ 0x0213EA94DE082924, 0x00004057, 0xFFFFE1CF, 0x0000063C, 0x00002E2E, 0xFFFFEB62, 0x000004FD, 0x00…
35 …{ 0x0213EA94DE284924, 0x00003FD0, 0xFFFFDF0F, 0x000006E5, 0x0000267C, 0xFFFFEE2D, 0x000004AB, 0x00…
36 …{ 0x0213EA94DE280904, 0x00003F13, 0xFFFFE010, 0x000006AD, 0x000020E7, 0xFFFFF266, 0x000003EC, 0x00…
37 …{ 0x0213EA94DE082044, 0x00004088, 0xFFFFDFAB, 0x000006B6, 0x0000252B, 0xFFFFEFDB, 0x00000458, 0x00…
[all …]
/linux-6.14.4/drivers/mfd/
Dwm8998-tables.c22 { 0x0212, 0x0000 },
23 { 0x0211, 0x0014 },
24 { 0x04E4, 0x0E0D },
25 { 0x04E5, 0x0E0D },
26 { 0x04E6, 0x0E0D },
27 { 0x04EB, 0x060E },
28 { 0x0441, 0xC759 },
29 { 0x0442, 0x2A08 },
30 { 0x0443, 0x5CFA },
31 { 0x026E, 0x0064 },
[all …]
Dwm8997-tables.c18 { 0x80, 0x0003 },
19 { 0x214, 0x0008 },
20 { 0x458, 0x0000 },
21 { 0x0081, 0xE022 },
22 { 0x294, 0x0000 },
23 { 0x80, 0x0000 },
24 { 0x171, 0x0000 },
31 case 0: in wm8997_patch()
36 return 0; in wm8997_patch()
60 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
[all …]

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