Lines Matching +full:0 +full:x00000504
13 /* Bit 0 reserved */
34 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
37 [CLKON_RX] = BIT(0),
70 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
73 [ROUTE_DIS] = BIT(0),
83 REG_FIELDS(ROUTE, route, 0x00000048);
86 [MEM_SIZE] = GENMASK(15, 0),
90 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
93 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
98 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
101 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
108 REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
111 [IPV6_ROUTER_HASH] = BIT(0),
121 REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148);
124 [IPV6_ROUTER_HASH] = BIT(0),
134 REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
137 REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
139 REG(IPA_BCR, ipa_bcr, 0x000001d0);
142 [IPA_BASE_ADDR] = GENMASK(16, 0),
147 REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
150 REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
153 /* Bits 0-3 reserved */
158 REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);
161 /* Bits 0-1 reserved */
174 REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
177 [MAX_PIPES] = GENMASK(3, 0),
187 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
190 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
195 REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);
198 [X_MIN_LIM] = GENMASK(5, 0),
209 0x00000400, 0x0020);
212 [X_MIN_LIM] = GENMASK(5, 0),
223 0x00000404, 0x0020);
226 [X_MIN_LIM] = GENMASK(5, 0),
237 0x00000500, 0x0020);
240 [X_MIN_LIM] = GENMASK(5, 0),
251 0x00000504, 0x0020);
254 [FRAG_OFFLOAD_EN] = BIT(0),
262 REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
265 [NAT_EN] = GENMASK(1, 0),
269 REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
272 [HDR_LEN] = GENMASK(5, 0),
284 REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
287 [HDR_ENDIANNESS] = BIT(0),
296 REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
299 0x00000818, 0x0070);
302 [ENDP_MODE] = GENMASK(2, 0),
313 REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
316 [AGGR_EN] = GENMASK(1, 0),
328 REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
331 [HOL_BLOCK_EN] = BIT(0),
336 0x0000082c, 0x0070);
339 [TIMER_BASE_VALUE] = GENMASK(4, 0),
346 0x00000830, 0x0070);
349 [DEAGGR_HDR_LEN] = GENMASK(5, 0),
358 REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
361 [ENDP_RSRC_GRP] = BIT(0),
365 REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
368 [SEQ_TYPE] = GENMASK(7, 0),
373 REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
376 [STATUS_EN] = BIT(0),
384 REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
387 REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
390 REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
393 REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
396 [UC_INTR] = BIT(0),
400 REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
404 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
408 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
412 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);