Lines Matching +full:0 +full:x00000504
13 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
35 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
38 [CLKON_RX] = BIT(0),
72 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
75 [ROUTE_DIS] = BIT(0),
85 REG_FIELDS(ROUTE, route, 0x00000048);
88 [MEM_SIZE] = GENMASK(15, 0),
92 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
95 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
100 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
103 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
110 REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
113 [IPV6_ROUTER_HASH] = BIT(0),
123 REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
126 REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
129 [IPA_BASE_ADDR] = GENMASK(17, 0),
134 REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
137 REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
140 /* Bits 0-1 reserved */
152 REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
155 [MAX_PIPES] = GENMASK(3, 0),
165 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
168 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
173 REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);
176 [DPL_TIMESTAMP_LSB] = GENMASK(4, 0),
185 REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c);
188 [DIV_VALUE] = GENMASK(8, 0),
193 REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250);
196 [PULSE_GRAN_0] = GENMASK(2, 0),
201 REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);
204 [X_MIN_LIM] = GENMASK(5, 0),
215 0x00000400, 0x0020);
218 [X_MIN_LIM] = GENMASK(5, 0),
229 0x00000404, 0x0020);
232 [X_MIN_LIM] = GENMASK(5, 0),
243 0x00000500, 0x0020);
246 [X_MIN_LIM] = GENMASK(5, 0),
257 0x00000504, 0x0020);
260 [FRAG_OFFLOAD_EN] = BIT(0),
268 REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
271 [NAT_EN] = GENMASK(1, 0),
275 REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
278 [HDR_LEN] = GENMASK(5, 0),
290 REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
293 [HDR_ENDIANNESS] = BIT(0),
306 REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
309 0x00000818, 0x0070);
312 [ENDP_MODE] = GENMASK(2, 0),
322 REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
325 [AGGR_EN] = GENMASK(1, 0),
339 REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
342 [HOL_BLOCK_EN] = BIT(0),
347 0x0000082c, 0x0070);
350 [TIMER_LIMIT] = GENMASK(4, 0),
357 0x00000830, 0x0070);
360 [DEAGGR_HDR_LEN] = GENMASK(5, 0),
369 REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
372 [ENDP_RSRC_GRP] = BIT(0),
376 REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
379 [SEQ_TYPE] = GENMASK(7, 0),
383 REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
386 [STATUS_EN] = BIT(0),
393 REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
396 [FILTER_HASH_MSK_SRC_ID] = BIT(0),
403 [FILTER_HASH_MSK_ALL] = GENMASK(6, 0),
417 0x0000085c, 0x0070);
420 REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
423 REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
426 REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
429 [UC_INTR] = BIT(0),
433 REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
437 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
441 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
445 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);