Lines Matching +full:0 +full:x00000504
13 [MAX_PIPES] = GENMASK(7, 0),
19 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000000);
22 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
49 REG_FIELDS(COMP_CFG, comp_cfg, 0x00000048);
52 [CLKON_RX] = BIT(0),
86 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000050);
89 [ROUTE_DEF_PIPE] = GENMASK(7, 0),
98 REG_FIELDS(ROUTE, route, 0x00000054);
101 [MEM_SIZE] = GENMASK(15, 0),
105 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x0000005c);
108 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
113 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000070);
116 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
123 REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000074);
127 REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x00000120, 0x0004);
130 [ROUTER_CACHE] = BIT(0),
136 REG_FIELDS(FILT_ROUT_CACHE_FLUSH, filt_rout_cache_flush, 0x0000404);
139 [IPA_BASE_ADDR] = GENMASK(17, 0),
144 REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x00000478);
147 /* Bits 0-1 reserved */
161 REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x00000488);
164 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
169 REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x000004a8);
172 /* Bits 0-7 reserved */
179 REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x000004ac);
182 [DIV_VALUE] = GENMASK(8, 0),
187 REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x000004b0);
190 [PULSE_GRAN_0] = GENMASK(2, 0),
197 REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x000004b4);
200 [X_MIN_LIM] = GENMASK(5, 0),
211 0x00000500, 0x0020);
214 [X_MIN_LIM] = GENMASK(5, 0),
225 0x00000504, 0x0020);
228 [X_MIN_LIM] = GENMASK(5, 0),
239 0x00000508, 0x0020);
242 [X_MIN_LIM] = GENMASK(5, 0),
253 0x0000050c, 0x0020);
256 [X_MIN_LIM] = GENMASK(5, 0),
267 0x00000600, 0x0020);
270 [X_MIN_LIM] = GENMASK(5, 0),
281 0x00000604, 0x0020);
284 [X_MIN_LIM] = GENMASK(5, 0),
295 0x00000608, 0x0020);
298 [X_MIN_LIM] = GENMASK(5, 0),
309 0x0000060c, 0x0020);
313 REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000006b0, 0x0004);
316 [FRAG_OFFLOAD_EN] = BIT(0),
325 REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00001008, 0x0080);
328 [NAT_EN] = GENMASK(1, 0),
332 REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000100c, 0x0080);
335 [HDR_LEN] = GENMASK(5, 0),
347 REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00001010, 0x0080);
350 [HDR_ENDIANNESS] = BIT(0),
365 REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00001014, 0x0080);
368 0x00001018, 0x0080);
371 [ENDP_MODE] = GENMASK(2, 0),
381 REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00001020, 0x0080);
384 [AGGR_EN] = GENMASK(1, 0),
399 REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00001024, 0x0080);
402 [HOL_BLOCK_EN] = BIT(0),
407 0x0000102c, 0x0080);
410 [TIMER_LIMIT] = GENMASK(4, 0),
417 0x00001030, 0x0080);
420 [DEAGGR_HDR_LEN] = GENMASK(5, 0),
429 REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00001034, 0x0080);
432 [ENDP_RSRC_GRP] = GENMASK(2, 0),
436 REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00001038, 0x0080);
439 [SEQ_TYPE] = GENMASK(7, 0),
443 REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000103c, 0x0080);
446 [STATUS_EN] = BIT(0),
452 REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00001040, 0x0080);
455 [CACHE_MSK_SRC_ID] = BIT(0),
466 0x0000105c, 0x0080);
469 [CACHE_MSK_SRC_ID] = BIT(0),
480 0x00001060, 0x0080);
483 REG(IPA_IRQ_STTS, ipa_irq_stts, 0x0000c008 + 0x1000 * GSI_EE_AP);
486 REG(IPA_IRQ_EN, ipa_irq_en, 0x0000c00c + 0x1000 * GSI_EE_AP);
489 REG(IPA_IRQ_CLR, ipa_irq_clr, 0x0000c010 + 0x1000 * GSI_EE_AP);
492 [UC_INTR] = BIT(0),
496 REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000c01c + 0x1000 * GSI_EE_AP);
501 0x0000c030 + 0x1000 * GSI_EE_AP, 0x0004);
506 0x0000c050 + 0x1000 * GSI_EE_AP, 0x0004);
511 0x0000c070 + 0x1000 * GSI_EE_AP, 0x0004);