Lines Matching +full:0 +full:x00000504
13 [MAX_PIPES] = GENMASK(7, 0),
19 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000000);
22 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
50 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000002c);
53 [CLKON_RX] = BIT(0),
87 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000034);
90 [ROUTE_DEF_PIPE] = GENMASK(7, 0),
99 REG_FIELDS(ROUTE, route, 0x00000038);
102 [MEM_SIZE] = GENMASK(15, 0),
106 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000040);
109 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
114 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000054);
117 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
124 REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000058);
128 REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x00000100, 0x0004);
131 [ROUTER_CACHE] = BIT(0),
137 REG_FIELDS(FILT_ROUT_CACHE_FLUSH, filt_rout_cache_flush, 0x0000404);
140 [IPA_BASE_ADDR] = GENMASK(17, 0),
145 REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x00000478);
148 /* Bits 0-1 reserved */
162 REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x00000488);
165 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
170 REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x000004a8);
173 [DPL_TIMESTAMP_LSB] = GENMASK(4, 0),
182 REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x000004ac);
185 [DIV_VALUE] = GENMASK(8, 0),
190 REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x000004b0);
193 [PULSE_GRAN_0] = GENMASK(2, 0),
200 REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x000004b4);
203 [X_MIN_LIM] = GENMASK(5, 0),
214 0x00000500, 0x0020);
217 [X_MIN_LIM] = GENMASK(5, 0),
228 0x00000504, 0x0020);
231 [X_MIN_LIM] = GENMASK(5, 0),
242 0x00000508, 0x0020);
245 [X_MIN_LIM] = GENMASK(5, 0),
256 0x0000050c, 0x0020);
259 [X_MIN_LIM] = GENMASK(5, 0),
270 0x00000600, 0x0020);
273 [X_MIN_LIM] = GENMASK(5, 0),
284 0x00000604, 0x0020);
287 [X_MIN_LIM] = GENMASK(5, 0),
298 0x00000608, 0x0020);
301 [X_MIN_LIM] = GENMASK(5, 0),
312 0x0000060c, 0x0020);
316 REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000006b0, 0x0004);
319 [FRAG_OFFLOAD_EN] = BIT(0),
327 REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00001008, 0x0080);
330 [NAT_EN] = GENMASK(1, 0),
334 REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000100c, 0x0080);
337 [HDR_LEN] = GENMASK(5, 0),
349 REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00001010, 0x0080);
352 [HDR_ENDIANNESS] = BIT(0),
367 REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00001014, 0x0080);
370 0x00001018, 0x0080);
373 [ENDP_MODE] = GENMASK(2, 0),
383 REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00001020, 0x0080);
386 [AGGR_EN] = GENMASK(1, 0),
400 REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00001024, 0x0080);
403 [HOL_BLOCK_EN] = BIT(0),
408 0x0000102c, 0x0080);
411 [TIMER_LIMIT] = GENMASK(4, 0),
418 0x00001030, 0x0080);
421 [DEAGGR_HDR_LEN] = GENMASK(5, 0),
430 REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00001034, 0x0080);
433 [ENDP_RSRC_GRP] = GENMASK(2, 0),
437 REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00001038, 0x0080);
440 [SEQ_TYPE] = GENMASK(7, 0),
444 REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000103c, 0x0080);
447 [STATUS_EN] = BIT(0),
453 REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00001040, 0x0080);
456 [CACHE_MSK_SRC_ID] = BIT(0),
467 0x0000105c, 0x0080);
470 [CACHE_MSK_SRC_ID] = BIT(0),
481 0x00001070, 0x0080);
484 REG(IPA_IRQ_STTS, ipa_irq_stts, 0x0000c008 + 0x1000 * GSI_EE_AP);
487 REG(IPA_IRQ_EN, ipa_irq_en, 0x0000c00c + 0x1000 * GSI_EE_AP);
490 REG(IPA_IRQ_CLR, ipa_irq_clr, 0x0000c010 + 0x1000 * GSI_EE_AP);
493 [UC_INTR] = BIT(0),
497 REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000c01c + 0x1000 * GSI_EE_AP);
502 0x0000c030 + 0x1000 * GSI_EE_AP, 0x0004);
507 0x0000c050 + 0x1000 * GSI_EE_AP, 0x0004);
512 0x0000c070 + 0x1000 * GSI_EE_AP, 0x0004);