Searched defs:CTRL (Results 1 – 14 of 14) sorted by relevance
433 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member484 …__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register … member
452 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member503 …__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register … member
412 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
592 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member743 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register … member1043 …__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register … member
563 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member714 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register … member1014 …__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register … member
625 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member776 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register … member1076 …__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register … member
522 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member575 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
533 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member586 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
498 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
685 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member840 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member1144 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
667 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member822 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member1126 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
746 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member901 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member1205 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
948 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member1103 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member1410 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
424 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) ����״̬�Ĵ��� */ member