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Searched defs:CTRL (Results 1 – 14 of 14) sorted by relevance

/nrf52832-nimble/rt-thread/components/CMSIS/Include/
H A Dcore_cm0plus.h433 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
484 …__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register … member
H A Dcore_sc000.h452 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
503 …__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register … member
H A Dcore_cm0.h412 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
H A Dcore_cm3.h592 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
743 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register … member
1043 …__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register … member
H A Dcore_sc300.h563 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
714 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register … member
1014 …__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register … member
H A Dcore_cm4.h625 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
776 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register … member
1076 …__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register … member
/nrf52832-nimble/nordic/cmsis/include/
H A Dcore_cm0plus.h522 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
575 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
H A Dcore_sc000.h533 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
586 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
H A Dcore_cm0.h498 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
H A Dcore_cm3.h685 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
840 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1144 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
H A Dcore_sc300.h667 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
822 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1126 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
H A Dcore_cm4.h746 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
901 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1205 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
H A Dcore_cm7.h948 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1103 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1410 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
/nrf52832-nimble/rt-thread/libcpu/c-sky/ck802/
H A Dcore_ck802.h424 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) ����״̬�Ĵ��� */ member