break ifuwbptr dependency

fix cfiVec (#1842)

Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

Merge pull request #1690 from chenguokai/frontend_db

frontend: Add ChiselDB records

IFU: mmio wait until last instruction retiring

* add 1 stage for mmio_state before sending request to MMIO bus
* check whether the last fetch packet commit all its intructions (the
result of executi

IFU: mmio wait until last instruction retiring

* add 1 stage for mmio_state before sending request to MMIO bus
* check whether the last fetch packet commit all its intructions (the
result of execution path has been decided)
* avoid speculative execution to MMIO bus

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bpu: remove minimal pred and old ubtb

bpu: refactor prediction i/o bundles

bpu: refactor BranchPredictionUpdate bundle

Previously the BranchPredictionUpdate bundle was inherited from
BranchPredictionBundle, and that made some field of the bundle
unused. It was hard to find

bpu: refactor BranchPredictionUpdate bundle

Previously the BranchPredictionUpdate bundle was inherited from
BranchPredictionBundle, and that made some field of the bundle
unused. It was hard to find which signals are really in use.
Now we make BranchPredictionUpdate a independent bundle, so that
the signals in it are all in use.

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ftq: do not use original last_cycle_bpu_in as write enable of commitStateQueue

ftq: copy last_cycle_bpu_in[_ptr] to reduce fanout

Optimize ICache s2_hit_reg and Ftq timing

* copy Ftq to ICache read valid signal

* move sram read data and miss data selection to IFU (after predecode)

ftq: optimize to itlb and to prefetch timing

* copy address select signal for every copied port
* add 1 more copy for itlb request use
* add 1 cycle latency for ftq_pc_mem read before sending to IPr

ftq: optimize to itlb and to prefetch timing

* copy address select signal for every copied port
* add 1 more copy for itlb request use
* add 1 cycle latency for ftq_pc_mem read before sending to IPrefetch

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ftq: update cfi info on non-mispred redirect as well

ftq: move toICache copied registers in ftq

ftq: fix a bug bypassing newest target for ifu req

ftq: fix commit target bypass logic

ftq: use newest_entry_target when dequeueing the newest entry

ftq: add write bypass for ftq_pc_mem to fix ifu req bugs, and reduce potential bubbles

ftq: fix ifu req nextStartAddr bugs and commPtrPlus1 assign bug

* should use RegNext on ftq_pc_mem rdata with the wrapper implementation now

Ftq: add connection for no-prefetch config

ftq, ctrl: fix compiling errors after rebase

ftq, ctrl: fix newest_target logic, pass it to ctrlblock, remove jalrTargetMem and read target from pc_mem

ftq: fix ifu req target difftest print info

ftq: remove prefetch target diff, prefetch logic is to fix

ftq: fix bypass ifu req logic