feat(Ftq): split Ftq meta SRAM into smaller size (#4569)

split Ftq meta SRAM into smaller size: (64 × 160) × 2 -> (64 × 80) × 4

refactor(DFT): refactor `DFT` IO (#4530)

fix(FTB, FTQ): dont use CPL2 SplittedSRAM (#4485)

If the frontend directly uses the SplittedSRAM of coupledL2, the
frontend's SRAM will be marked as a multi-cycle path, the same as
coupledL2's SRAM.

feat(FTB, FTQ): split FTB meta SRAM and FTQ meta SRAM (#4360)

FTB meta SRAM: 512 × 320 -> (512 × 40) × 8
FTQ meta SRAM: 64 × 320 -> (64 × 160) × 2

chore: fix several deprecation warning (#4352)

feat(dfx): integerate dfx components (#4312)

fix(FTQ): start of the first instruction in an entry (#4072)

The start of the first instruction can be the second 2-byte of the entry.

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
Wh

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
WhenContext. For example, when(cond1){XSDebug(cond2, pable)} to
XSDebug(cond1 && cond2, pable)

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Frontend: modify the code related to configuration parameters (#3950)

feat(frontend): add ClockGate at frontend SRAMTemplate (#3889)

* Add param `withClockGate` at SRAMTemplate
* when SRAM is single-port, use maskedClock for both array\.read\(\) and
array\.write\(\)

feat(frontend): add ClockGate at frontend SRAMTemplate (#3889)

* Add param `withClockGate` at SRAMTemplate
* when SRAM is single-port, use maskedClock for both array\.read\(\) and
array\.write\(\) to ensure single-port SRAM access.
* when SRAM is multi-port, the read and write ports of the multi-port
SRAM are gated using different clocks.

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docs: add acknowledgements (#3861)

fix(ICache): cancel prefetch when there is exception from backend (#3787)

feat(ittage): Reuse always_taken to mark the first occurrence of the jalr inst (#3718)

Reuse always_taken to mark the first occurrence of the jalr instruction
and rename always_taken to strong_bias.

style(Frontend): use scalafmt formatting frontend (#3370)

Format frontend according to the scalafmt file drafted in #3061.

timing(FTQ): calculate requests sent to prefetcher one cycle in advance (#3499)

fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump

fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump
target address, which made it impossible to raise exceptions in such
cases.

To resolve this problem, we detect the invalid jump target in
jump/branch/CSR and, this information to frontend and store the complete
invalid target in a single register in backend. The frontend will then
raise an exception to backend and backend will also use the invalid
target in the register to write xtval and mepc.

---------

Co-authored-by: Muzi <[email protected]>
Co-authored-by: ngc7331 <[email protected]>

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fix(RAS): correct the Call and Ret signals during redirection, and modify the blocking mechanism of RAS. (#3514)

1. RAS: relax the conditions for unblocking the speculative queue after
it has been

fix(RAS): correct the Call and Ret signals during redirection, and modify the blocking mechanism of RAS. (#3514)

1. RAS: relax the conditions for unblocking the speculative queue after
it has been blocked
2. FTQ: correct the pre-decode information sent to the RAS

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Frontend: implement prefetch.i support (RVA23 Zicbop) (#3396)

FTQ: FTQ entry commit condition and move pointer condition

An FTQ entry should be committed when last instruction is committed
instead of all are committed, as backend may not commit every single

FTQ: FTQ entry commit condition and move pointer condition

An FTQ entry should be committed when last instruction is committed
instead of all are committed, as backend may not commit every single
instruction.

This PR also addresses the performance bugs noted in PR #3303, as it
involves a complete rewrite. The description of PR #3303 is as follows.

PR #3086 fixes the bug where multiple load replays will fill the whole
FTQ by committing the FTQ entries created by load replays. However,
these committed entries will generate FTB entries that negatively impact
the BP accuracy under certain conditions.

To mitigate this, FTQ entries containing only one single flushed
instruction will no longer generate FTB entries. The commPtr and
robcommPtr will sill advance in case of running FTQ entries.

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PcTargetMem: Fixed a bug that caused the backend to be unable to read the newest target (#3269)

Redirect fix timing (#3209)

ftq: fix redirectReadStart with IfuRedirectNum (#3199)

Backend,Frontend: pass flag of FtqPtr to TargetMem to avoid read out-of-date predict target (#3184)

* Hold newest predict target everytime it is updated by frontend.
* Don't use out-of-date predict

Backend,Frontend: pass flag of FtqPtr to TargetMem to avoid read out-of-date predict target (#3184)

* Hold newest predict target everytime it is updated by frontend.
* Don't use out-of-date predict value even if FtqIdx match.

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ICache: implement new ICache (#3051)

Co-authored-by: xu_zh <[email protected]>

fix: multiple load replays lead to running out of FTQ entries (#3086)

Previously, FTQ did not handle flush-itself redirect level, which is
used by load replays. This leads to running out of FTQ ent

fix: multiple load replays lead to running out of FTQ entries (#3086)

Previously, FTQ did not handle flush-itself redirect level, which is
used by load replays. This leads to running out of FTQ entries because
commPtr remains the same while ifuPtr keeps increasing when a new replay
redirect request arrives. Now, commPtr will also increase in this
scenario.

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