bpu: bring bpu control signals into use (#1477)

parameters: reduce ghr length and make it calculated using a formula (#1442)

* parameters: reduce ghr length and make it calculated using a formula

* bpu: add error checking for ghist ptr, suppor

parameters: reduce ghr length and make it calculated using a formula (#1442)

* parameters: reduce ghr length and make it calculated using a formula

* bpu: add error checking for ghist ptr, support hist lengths that are not power of 2

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bpu: handle fall through error at stage 3

bpu,ftq: remove oversize logic

bpu: add more detailed s3 redirect perf counters

bpu: read oldest bits one stage ahead

ftq: cut redirect path from toIfuReq.valid

bpu: add one cycle on direct

ras: should not push or pop when s3_redirect

ittage: use result in stage3

* remove base table and use ftb results as base pred
* add corrsponding redirect logic in bpu

tage: improve performance and reduce area

* split entries into by numBr and use bits in pc to hash between them
* use shorter tags for each table
* make perfEvents a general interface for branch pre

tage: improve performance and reduce area

* split entries into by numBr and use bits in pc to hash between them
* use shorter tags for each table
* make perfEvents a general interface for branch predictor components
in order to remove casting operation in composer

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bpu: timing optimizations

* move statisical corrector to stage 3
* add recover path in stage 3 for ras in case stage 2 falsely push or pop
* let stage 2 has the highest physical priority in bpu
* le

bpu: timing optimizations

* move statisical corrector to stage 3
* add recover path in stage 3 for ras in case stage 2 falsely push or pop
* let stage 2 has the highest physical priority in bpu
* left ras broken for the next commit to fix

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ubtb: timing and performance optimizations

* timing: use single ported SRAMs, invalidating read responses on write
* performance:
-- shortening history length to accelerate training
-- use a predict

ubtb: timing and performance optimizations

* timing: use single ported SRAMs, invalidating read responses on write
* performance:
-- shortening history length to accelerate training
-- use a predictor to reduce s2_redirects on FTB not hit

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bpu: fix an error when two stages has different 'oversize' bit

bpu: fix fallThruAddr on fallThruError, implement ghist diff mechanism

ubtb: use folded history class instead of seperately managing a ghr

ubtb: refactor prediction mechanism(temp commit)

Merge remote-tracking branch 'origin/change-fallThrough' into ubtb-refactor

bpu: timing optimizations

* use parallel mux to select provider and altprovider for TAGE and ITTAGE
* reduce logics on SC prediction
* calculate higher bits of targets at stage 1 for ftb
* reduce lo

bpu: timing optimizations

* use parallel mux to select provider and altprovider for TAGE and ITTAGE
* reduce logics on SC prediction
* calculate higher bits of targets at stage 1 for ftb
* reduce logics for RAS and ITTAGE prediction assignment

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Optimize IFU and PreDecode timing (#1347)

* ICache: add ReplacePipe for Probe & Release

* remove ProbeUnit

* Probe & Release enter ReplacePipe

* fix bugs when running Linux on MinimalConfi

Optimize IFU and PreDecode timing (#1347)

* ICache: add ReplacePipe for Probe & Release

* remove ProbeUnit

* Probe & Release enter ReplacePipe

* fix bugs when running Linux on MinimalConfig

* TODO: set conflict for ReplacePipe

* ICache: fix ReplacePipe invalid write bug

* chores: code clean up

* IFU: optimize timing

* PreDecode: separate into 2 module for timing optimization

* IBuffer: add enqEnable to replace valid for timing

* IFU/ITLB: optimize timing

* IFU: calculate cut_ptr in f1

* TLB: send req in f1 and wait resp in f2

* ICacheMainPipe: add tlb miss logic in s0

* Optimize IFU timing

* IFU: fix lastHalfRVI bug

* IFU: fix performance bug

* IFU: optimize MMIO commit timing

* IFU: optmize trigger timing and add frontendTrigger

* fix compile error

* IFU: fix mmio stuck bug

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core: refactor hardware performance counters (#1335)

This commit optimizes the coding style and timing for hardware
performance counters.

By default, performance counters are RegNext(RegNext(_)).

bpu: remove stage 3

bpu: remove unuseful 'pred_cycle' signal in meta SRAM

bpu: timing optimizations

* let the hit signal of each stage be used at last

bpu: timing optimizations

* use one hot muxes for ftb read resp
* generate branch history shift one hot vec for history update src sel
and update for all possible shift values