History log of /XiangShan/src/main/scala/xiangshan/backend/trace/Trace.scala (Results 1 – 6 of 6)
Revision Date Author Comments
# fd448a9d 16-Dec-2024 chengguanghui <[email protected]>

area(trace, pcMem): Trace only get `startAddr` from pcmem


# 3ad9f3dd 05-Dec-2024 chengguanghui <[email protected]>

fix(trace): add pipe for traceCoreInterface in memblock and l2top


# c308d936 21-Nov-2024 chengguanghui <[email protected]>

fix(trace): remove traceTrap & tracePriv from trace pipeline


# 551cc696 24-Oct-2024 chengguanghui <[email protected]>

fix(trace): fix width of iaddr


# 725e8ddc 19-Sep-2024 chengguanghui <[email protected]>

feat(trace): add TraceCoreInterface in top.


# 4907ec88 19-Sep-2024 chengguanghui <[email protected]>

feat(trace): add trace buffer.