1package xiangshan.backend.trace 2 3import chisel3._ 4import chisel3.util.{RegEnable, ValidIO, log2Up} 5import org.chipsalliance.cde.config.Parameters 6import xiangshan.HasXSParameter 7 8class TraceParams( 9 val TraceGroupNum : Int, 10 val HasEncoder : Boolean, 11 val TraceEnable : Boolean, 12) 13 14class TraceIO(implicit val p: Parameters) extends Bundle with HasXSParameter { 15 val fromEncoder = Input(new FromEncoder) 16 val fromRob = Flipped(new TraceBundle(hasIaddr = false, CommitWidth, IretireWidthInPipe)) 17 val blockRobCommit = Output(Bool()) 18 val toPcMem = Vec(TraceGroupNum, ValidIO(new TraceBlock(false, IretireWidthCompressed))) 19 val fromPcMem = Input(Vec(TraceGroupNum, UInt(IaddrWidth.W))) 20 val toEncoder = new TraceBundle(hasIaddr = true, TraceGroupNum, IretireWidthCompressed) 21} 22 23class Trace(implicit val p: Parameters) extends Module with HasXSParameter { 24 val io = IO(new TraceIO) 25 val (fromEncoder, fromRob, toPcMem, fromPcMem, toEncoder) = (io.fromEncoder, io.fromRob, io.toPcMem, io.fromPcMem, io.toEncoder) 26 27 /** 28 * stage 0: CommitInfo from rob 29 */ 30 val blockCommit = Wire(Bool()) 31 io.blockRobCommit := blockCommit 32 33 /** 34 * stage 1: regNext(robCommitInfo) 35 */ 36 val s1_in = fromRob 37 val s1_out = WireInit(0.U.asTypeOf(s1_in)) 38 39 for(i <- 0 until CommitWidth) { 40 if(i == 0){ 41 s1_out.trap := RegEnable(s1_in.trap, s1_in.blocks(i).valid) 42 } 43 s1_out.blocks(i).valid := RegEnable(s1_in.blocks(i).valid, !blockCommit) 44 s1_out.blocks(i).bits := RegEnable(s1_in.blocks(i).bits, s1_in.blocks(i).valid) 45 } 46 47 /** 48 * stage 2: compress, s2_out(deq from traceBuffer) -> pcMem 49 */ 50 val s2_in = s1_out 51 val traceBuffer = Module(new TraceBuffer) 52 traceBuffer.io.in.fromEncoder := fromEncoder 53 traceBuffer.io.in.fromRob := s2_in 54 val s2_out_trap = traceBuffer.io.out.groups.trap 55 val s2_out_block = traceBuffer.io.out.groups.blocks 56 blockCommit := traceBuffer.io.out.blockCommit 57 58 /** 59 * stage 3: groups with iaddr from pcMem(ftqidx & ftqOffset -> iaddr) -> encoder 60 */ 61 val s3_in_trap = s2_out_trap 62 val s3_in_block = s2_out_block 63 64 val s3_out_trap = RegNext(s3_in_trap) 65 val s3_out_block = RegNext(s3_in_block) 66 67 toPcMem := s3_in_block 68 69 io.toEncoder := DontCare 70 for(i <- 0 until TraceGroupNum) { 71 toEncoder.trap := s3_out_trap 72 toEncoder.blocks(i).bits.iaddr.foreach(_ := fromPcMem(i)) 73 toEncoder.blocks(i).valid := s3_out_block(i).valid 74 toEncoder.blocks(i).bits.tracePipe := s3_out_block(i).bits.tracePipe 75 } 76 if(backendParams.debugEn){ 77 dontTouch(io.toEncoder) 78 } 79} 80 81 82 83 84 85 86