1package xiangshan.backend.trace 2 3import chisel3._ 4import chisel3.util.{RegEnable, ValidIO, log2Up} 5import org.chipsalliance.cde.config.Parameters 6import xiangshan.HasXSParameter 7 8class TraceParams( 9 val HasEncoder : Boolean, 10 val TraceEnable : Boolean, 11 val TraceGroupNum : Int, 12 val PrivWidth : Int, 13 val ItypeWidth : Int, 14 val IlastsizeWidth : Int, 15) 16 17class TraceIO(implicit val p: Parameters) extends Bundle with HasXSParameter { 18 val fromEncoder = Input(new FromEncoder) 19 val fromRob = Flipped(new TraceBundle(hasIaddr = false, CommitWidth, IretireWidthInPipe)) 20 val blockRobCommit = Output(Bool()) 21 val toPcMem = Vec(TraceGroupNum, ValidIO(new TraceBlock(false, IretireWidthCompressed))) 22 val fromPcMem = Input(Vec(TraceGroupNum, UInt(IaddrWidth.W))) 23 val toEncoder = new TraceBundle(hasIaddr = true, TraceGroupNum, IretireWidthCompressed) 24} 25 26class Trace(implicit val p: Parameters) extends Module with HasXSParameter { 27 val io = IO(new TraceIO) 28 val (fromEncoder, fromRob, toPcMem, fromPcMem, toEncoder) = (io.fromEncoder, io.fromRob, io.toPcMem, io.fromPcMem, io.toEncoder) 29 30 /** 31 * stage 0: CommitInfo from rob 32 */ 33 val blockCommit = Wire(Bool()) 34 io.blockRobCommit := blockCommit 35 36 /** 37 * stage 1: regNext(robCommitInfo) 38 */ 39 val s1_in = fromRob 40 val s1_out = WireInit(0.U.asTypeOf(s1_in)) 41 42 for(i <- 0 until CommitWidth) { 43 // Trap only occor in block(0). 44 s1_out.trap := RegEnable(s1_in.trap, 0.U.asTypeOf(s1_in.trap), s1_in.blocks(0).valid && Itype.isTrap(s1_in.blocks(0).bits.tracePipe.itype)) 45 s1_out.blocks(i).valid := RegEnable(s1_in.blocks(i).valid, 0.U.asTypeOf(s1_in.blocks(i).valid), !blockCommit) 46 s1_out.blocks(i).bits := RegEnable(s1_in.blocks(i).bits, 0.U.asTypeOf(s1_in.blocks(i).bits), s1_in.blocks(i).valid) 47 } 48 49 /** 50 * stage 2: compress, s2_out(deq from traceBuffer) -> pcMem 51 */ 52 val s2_in = s1_out 53 val traceBuffer = Module(new TraceBuffer) 54 traceBuffer.io.in.fromEncoder := fromEncoder 55 traceBuffer.io.in.fromRob := s2_in 56 val s2_out_trap = traceBuffer.io.out.groups.trap 57 val s2_out_block = traceBuffer.io.out.groups.blocks 58 blockCommit := traceBuffer.io.out.blockCommit 59 60 /** 61 * stage 3: groups with iaddr from pcMem(ftqidx & ftqOffset -> iaddr) -> encoder 62 */ 63 val s3_in_trap = s2_out_trap 64 val s3_in_block = s2_out_block 65 66 val s3_out_trap = RegNext(s3_in_trap) 67 val s3_out_block = RegNext(s3_in_block) 68 69 toPcMem := s3_in_block 70 71 for(i <- 0 until TraceGroupNum) { 72 toEncoder.trap := s3_out_trap 73 toEncoder.blocks(i).valid := s3_out_block(i).valid 74 toEncoder.blocks(i).bits.iaddr.foreach(_ := Mux(s3_out_block(i).valid, fromPcMem(i), 0.U)) 75 toEncoder.blocks(i).bits.tracePipe := s3_out_block(i).bits.tracePipe 76 } 77 if(backendParams.debugEn){ 78 dontTouch(io.toEncoder) 79 } 80} 81 82 83 84 85 86 87