1package xiangshan.backend.trace 2 3import chisel3._ 4import chisel3.util.{RegEnable, ValidIO, log2Up} 5import org.chipsalliance.cde.config.Parameters 6import xiangshan.HasXSParameter 7 8class TraceParams( 9 val HasEncoder : Boolean, 10 val TraceEnable : Boolean, 11 val TraceGroupNum : Int, 12 val IaddrWidth : Int, 13 val PrivWidth : Int, 14 val ItypeWidth : Int, 15 val IlastsizeWidth : Int, 16) 17 18class TraceIO(implicit val p: Parameters) extends Bundle with HasXSParameter { 19 val fromEncoder = Input(new FromEncoder) 20 val fromRob = Flipped(new TraceBundle(hasIaddr = false, CommitWidth, IretireWidthInPipe)) 21 val blockRobCommit = Output(Bool()) 22 val toPcMem = Vec(TraceGroupNum, ValidIO(new TraceBlock(false, IretireWidthCompressed))) 23 val fromPcMem = Input(Vec(TraceGroupNum, UInt(IaddrWidth.W))) 24 val toEncoder = new TraceBundle(hasIaddr = true, TraceGroupNum, IretireWidthCompressed) 25} 26 27class Trace(implicit val p: Parameters) extends Module with HasXSParameter { 28 val io = IO(new TraceIO) 29 val (fromEncoder, fromRob, toPcMem, fromPcMem, toEncoder) = (io.fromEncoder, io.fromRob, io.toPcMem, io.fromPcMem, io.toEncoder) 30 31 /** 32 * stage 0: CommitInfo from rob 33 */ 34 val blockCommit = Wire(Bool()) 35 io.blockRobCommit := blockCommit 36 37 /** 38 * stage 1: regNext(robCommitInfo) 39 */ 40 val s1_in = fromRob 41 val s1_out = WireInit(0.U.asTypeOf(s1_in)) 42 43 for(i <- 0 until CommitWidth) { 44 // Trap only occor in block(0). 45 s1_out.trap := RegEnable(s1_in.trap, 0.U.asTypeOf(s1_in.trap), s1_in.blocks(0).valid && Itype.isTrap(s1_in.blocks(0).bits.tracePipe.itype)) 46 s1_out.blocks(i).valid := RegEnable(s1_in.blocks(i).valid, 0.U.asTypeOf(s1_in.blocks(i).valid), !blockCommit) 47 s1_out.blocks(i).bits := RegEnable(s1_in.blocks(i).bits, 0.U.asTypeOf(s1_in.blocks(i).bits), s1_in.blocks(i).valid) 48 } 49 50 /** 51 * stage 2: compress, s2_out(deq from traceBuffer) -> pcMem 52 */ 53 val s2_in = s1_out 54 val traceBuffer = Module(new TraceBuffer) 55 traceBuffer.io.in.fromEncoder := fromEncoder 56 traceBuffer.io.in.fromRob := s2_in 57 val s2_out_trap = traceBuffer.io.out.groups.trap 58 val s2_out_block = traceBuffer.io.out.groups.blocks 59 blockCommit := traceBuffer.io.out.blockCommit 60 61 /** 62 * stage 3: groups with iaddr from pcMem(ftqidx & ftqOffset -> iaddr) -> encoder 63 */ 64 val s3_in_trap = s2_out_trap 65 val s3_in_block = s2_out_block 66 67 val s3_out_trap = RegNext(s3_in_trap) 68 val s3_out_block = RegNext(s3_in_block) 69 70 toPcMem := s3_in_block 71 72 for(i <- 0 until TraceGroupNum) { 73 toEncoder.trap := s3_out_trap 74 toEncoder.blocks(i).valid := s3_out_block(i).valid 75 toEncoder.blocks(i).bits.iaddr.foreach(_ := Mux(s3_out_block(i).valid, fromPcMem(i), 0.U)) 76 toEncoder.blocks(i).bits.tracePipe := s3_out_block(i).bits.tracePipe 77 } 78 if(backendParams.debugEn){ 79 dontTouch(io.toEncoder) 80 } 81} 82 83 84 85 86 87 88