History log of /XiangShan/src/main/scala/xiangshan/backend/fu/ (Results 251 – 275 of 1283)
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89bb253528-Jun-2024 Xuan Hu <[email protected]>

NewCSR,AIA: connect external interrupt pending to xip CSR

* Connect meip produced by imsic to `mip.regOut.MEIP`.
* Connect seip produced by imsic to `mip.rdata.SEIP`.
* Connect vseip produced by ims

NewCSR,AIA: connect external interrupt pending to xip CSR

* Connect meip produced by imsic to `mip.regOut.MEIP`.
* Connect seip produced by imsic to `mip.rdata.SEIP`.
* Connect vseip produced by imsic to `hgeip.regOut[63:1]`

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cc1eb70d28-Jun-2024 Xuan Hu <[email protected]>

Decode: let CSRR vl executed in Vsetu

a023188927-Jun-2024 Xuan Hu <[email protected]>

NewCSR: separate csr modified FS/VS dirty from robCommit.FS/VS dirty

c715e8fe27-Jun-2024 Xuan Hu <[email protected]>

NewCSR: set vstart to zero when setting VS dirty

7d3fb55927-Jun-2024 Xuan Hu <[email protected]>

NewCSR,AIA: fix connection of xtopei

26033c5226-Jun-2024 chengguanghui <[email protected]>

Support smstateen/ssstateen extension, add stateen0 CSRs

cdf05a9c24-Jun-2024 sinceforYy <[email protected]>

NewCSR: fix miselect module name

d60bfe5a18-Jun-2024 sinceforYy <[email protected]>

NewCSR: decode all vecfp inst will raise EX_II when FS=Off

a9c95a2117-Jun-2024 sinceforYy <[email protected]>

NewCSR: fix hfence exception io

be37cd3a17-Jun-2024 sinceforYy <[email protected]>

NewCSR: executing dret outside of Debug Mode causes EX_II

0f9a14c614-Jun-2024 chengguanghui <[email protected]>

NewCSR: fixed dpc

5cfbb49613-Jun-2024 sinceforYy <[email protected]>

NewCSR: fix illegal check

* when write Read-Only CSR will raise EX_II
* Access M mode CSR in VS/VU mode will raise EX_II

7842010113-Jun-2024 chengguanghui <[email protected]>

NewCSR: correct typos about xcounteren

53e1a9f526-Jun-2024 Xuan Hu <[email protected]>

NewCSR: delay 1 cycle for vl and vtype passed to difftest

70cd397b24-Jun-2024 Xuan Hu <[email protected]>

bump AIA

f7c21cb524-Jun-2024 Xuan Hu <[email protected]>

NewCSR: fix connection of IMSIC

d23963a824-Jun-2024 Xuan Hu <[email protected]>

tmp-NewCSR: fix connection of CSR vector bundles

9c0fd28f18-Jun-2024 Xuan Hu <[email protected]>

NewCSR: fix atp CSRs PPN mask

* The writable length of satp is `PAddrBits - PageOffsetWidth`.
* The writable length of vsatp varies with hgatp.MODE.
* When hgatp.MODE is `Bare`, it's `PAddrBits -

NewCSR: fix atp CSRs PPN mask

* The writable length of satp is `PAddrBits - PageOffsetWidth`.
* The writable length of vsatp varies with hgatp.MODE.
* When hgatp.MODE is `Bare`, it's `PAddrBits - PageOffsetWidth`.
* When hgatp.MODE is `Sv39x4`, it's `41 - PageOffsetWidth`.
* The writable length of hgatp is `PAddrBits - PageOffsetWidth`. Since the root page table is 16 KiB and must be aligned to a 16-KiB boundary, the lowest two bits of the physical page number (PPN) in hgatp always read as zeros.
* A write to hgatp with an unsupported MODE value is not ignored as it is for satp.
* Instead, the fields of hgatp are WARL in the normal way, when so indicated.

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0bc47d4c13-Jun-2024 Xuan Hu <[email protected]>

NewCSR: delay one cycle for ASID/VMIDChanged

* Make ASID/VMIDChanged asserts at the same time of satp/vsatp/hgatp updated.

82f438ed13-Jun-2024 Xuan Hu <[email protected]>

NewCSR: update vsstatus.FS/VS only in VirtMode

bae2282113-Jun-2024 Xuan Hu <[email protected]>

NewCSR: use already existing fields bundle to avoid warnings

8885788913-Jun-2024 Xuan Hu <[email protected]>

NewCSR: fix illegal check when FS/VS is off and fix dirty set of FS/VS

69de61be12-Jun-2024 Xuan Hu <[email protected]>

NewCSR: fix highest EX/IR produce

c5996da912-Jun-2024 chengguanghui <[email protected]>

NewCSR: fixed read access to scountovf in Mmode

4d2be3d205-Jun-2024 sinceforYy <[email protected]>

NewCSR: add FS, VS check

* Execute fp/vec inst will modify sstatus.FS/VS to Dirty in HS/HU mode
* Execute fp/vec inst will modify sstatus.FS/VS and vsstatus.FS/VS to Dirty in VS/VU mode
* when sstat

NewCSR: add FS, VS check

* Execute fp/vec inst will modify sstatus.FS/VS to Dirty in HS/HU mode
* Execute fp/vec inst will modify sstatus.FS/VS and vsstatus.FS/VS to Dirty in VS/VU mode
* when sstatus.FS/VS is Off, execute fp/vec inst will raise EX_II in HS/HU mode
* when sstatus.FS/VS or vsstatus.FS/VS is Off, execute fp/vec inst will raise EX_II in VS/VU mode
* when sstatus.FS/VS or vsstatus.FS/VS is Off, access fp/vec CSR will raise EX_II

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