Backend: fix lat>0 cancel error

backend: change vfSchdParams, add PipelineConnect name

Backend: BusyTable supports load fastwakeup

Backend: reduce imm width and move imm generating of instr fusion to enq

Backend: remove unused signals in (BusyTable -> IQ)

IssueQueue: optimize timing
- parameterize deq imms for instruction fusion
- refactor deq entry selection

Decode: fix vset's vtype

rv64v: add f2v to remove all fs1 duplicate logic (#2613)

* rv64v: add f2v to remove all fs1 duplicate logic

* rv64v: use IntFPToVec module for i2v and f2v

mdp: enable LFST by default

mdp: connect missing wires

Fix bugs in exceptional stores (#2600)

* VPPU: fix timing mismatch between isMvnr and data

* STU,HYU,VSFlowQueue: add exceptionVec in store pipeline feedbacks

* VSFlowQueue: add exception buff

Fix bugs in exceptional stores (#2600)

* VPPU: fix timing mismatch between isMvnr and data

* STU,HYU,VSFlowQueue: add exceptionVec in store pipeline feedbacks

* VSFlowQueue: add exception buffer to record exceptional vaddr

* MemBlock: modify signal naming

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Backend: add predecode info in load pipeline

Add vector MMIO access path

Debug Module: cherry-pick debug module from nanhu

Bundles: fix width of uopIdx

VldMergeUnit: use vdIdx inside a field to generate mask

rv64v: add write back num for indexed load/store (#2469)

* rv64v: add write back num for indexed load/store

* rv64v: fix write back num for vset

Mgu: use sew as element width instead of eew for indexed loads/stores

UopQueue: pass on mask and vdIdx to Backend

backend: fix VldMergeUnit

IssueQueue: add vector load/store IssueQueue

rv64v: add veew in VPUCtrlSignals (#2434)

Add VLSU

* miscs: optimize code style

* vector: add VLSU param system and redefine vector lq io

* VLUopQueue: add flow split and address generation logic

* VLUopQueue: add flow issue and writebac

Add VLSU

* miscs: optimize code style

* vector: add VLSU param system and redefine vector lq io

* VLUopQueue: add flow split and address generation logic

* VLUopQueue: add flow issue and writeback logic

* VLUopQueue: set vstart for elements with exception

* VLUopQueue: handle unit-stride fof loads

* VLUopQueue: implement vector masking according to vm

* vector: rewrite vector store io

* VlFlowQueue: add enqueue and dequeue logic

* VLFlowQueue: fix some coding problem

* VlFlowQueue: add issue, replay and result logic

* VLFlowQueue: add redirect logic

* Rob: fix compilation error

* vector: remove stale codes

* vector: add VSUopQueue and fix bugs for vector load

* backbone: add vector load/store execution paths

* VSFlowQueue: Basic function

* VLUopQueue: add redirect logic for load-load violation

* VSFlowQueue: fix some compile problems

* VSUopQueue: add signal to indicate whether a flow is the last one

* VSFlowQueue: inform scala sq when vector store finished

* StoreQueue: maintain sequential retirement between scalar & vector stores

* LoadQueueRAW: handle violation between vector stores & scalar loads

* LDU: add vector store to scalar load forwarding

* XSCore: fix writeback width of MemBlock

* vector: fix load/store whole register and masked unit-stride load/store emul, evl, flownum (#2383)

* VSFlowQueue: Support STLF

* VLFlowQueue: fix compile bug

* VSFlowQueue: fix compile problem

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Co-authored-by: xuzefan <[email protected]>
Co-authored-by: good-circle <[email protected]>
Co-authored-by: weidingliu <[email protected]>

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backend: fix load cancel bundle

backend,mem: support HybridUnit