1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.BundleUtils.makeValid 8import utils.OptionWrapper 9import xiangshan._ 10import xiangshan.backend.datapath.DataConfig._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.datapath.WbConfig.PregWB 13import xiangshan.backend.decode.{ImmUnion, XDecode} 14import xiangshan.backend.exu.ExeUnitParams 15import xiangshan.backend.fu.FuType 16import xiangshan.backend.fu.fpu.Bundles.Frm 17import xiangshan.backend.fu.vector.Bundles._ 18import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, IssueQueueJumpBundle, SchedulerType, EntryDeqRespBundle} 19import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 20import xiangshan.backend.rob.RobPtr 21import xiangshan.frontend._ 22import xiangshan.mem.{LqPtr, SqPtr} 23 24object Bundles { 25 26 // frontend -> backend 27 class StaticInst(implicit p: Parameters) extends XSBundle { 28 val instr = UInt(32.W) 29 val pc = UInt(VAddrBits.W) 30 val foldpc = UInt(MemPredPCWidth.W) 31 val exceptionVec = ExceptionVec() 32 val trigger = new TriggerCf 33 val preDecodeInfo = new PreDecodeInfo 34 val pred_taken = Bool() 35 val crossPageIPFFix = Bool() 36 val ftqPtr = new FtqPtr 37 val ftqOffset = UInt(log2Up(PredictWidth).W) 38 39 def connectCtrlFlow(source: CtrlFlow): Unit = { 40 this.instr := source.instr 41 this.pc := source.pc 42 this.foldpc := source.foldpc 43 this.exceptionVec := source.exceptionVec 44 this.trigger := source.trigger 45 this.preDecodeInfo := source.pd 46 this.pred_taken := source.pred_taken 47 this.crossPageIPFFix := source.crossPageIPFFix 48 this.ftqPtr := source.ftqPtr 49 this.ftqOffset := source.ftqOffset 50 } 51 } 52 53 // StaticInst --[Decode]--> DecodedInst 54 class DecodedInst(implicit p: Parameters) extends XSBundle { 55 def numSrc = backendParams.numSrc 56 // passed from StaticInst 57 val instr = UInt(32.W) 58 val pc = UInt(VAddrBits.W) 59 val foldpc = UInt(MemPredPCWidth.W) 60 val exceptionVec = ExceptionVec() 61 val trigger = new TriggerCf 62 val preDecodeInfo = new PreDecodeInfo 63 val pred_taken = Bool() 64 val crossPageIPFFix = Bool() 65 val ftqPtr = new FtqPtr 66 val ftqOffset = UInt(log2Up(PredictWidth).W) 67 // decoded 68 val srcType = Vec(numSrc, SrcType()) 69 val lsrc = Vec(numSrc, UInt(6.W)) 70 val ldest = UInt(6.W) 71 val fuType = FuType() 72 val fuOpType = FuOpType() 73 val rfWen = Bool() 74 val fpWen = Bool() 75 val vecWen = Bool() 76 val isXSTrap = Bool() 77 val waitForward = Bool() // no speculate execution 78 val blockBackward = Bool() 79 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 80 val canRobCompress = Bool() 81 val selImm = SelImm() 82 val imm = UInt(ImmUnion.maxLen.W) 83 val fpu = new FPUCtrlSignals 84 val vpu = new VPUCtrlSignals 85 val wfflags = Bool() 86 val isMove = Bool() 87 val uopIdx = UInt(5.W) 88 val uopSplitType = UopSplitType() 89 val isVset = Bool() 90 val firstUop = Bool() 91 val lastUop = Bool() 92 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 93 val commitType = CommitType() // Todo: remove it 94 95 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 96 isXSTrap, waitForward, blockBackward, flushPipe, canRobCompress, uopSplitType, selImm) 97 98 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 99 val decoder: Seq[UInt] = ListLookup( 100 inst, XDecode.decodeDefault.map(bitPatToUInt), 101 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 102 ) 103 allSignals zip decoder foreach { case (s, d) => s := d } 104 this 105 } 106 107 def isSoftPrefetch: Bool = { 108 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 109 } 110 111 def connectStaticInst(source: StaticInst): Unit = { 112 for ((name, data) <- this.elements) { 113 if (source.elements.contains(name)) { 114 data := source.elements(name) 115 } 116 } 117 } 118 } 119 120 // DecodedInst --[Rename]--> DynInst 121 class DynInst(implicit p: Parameters) extends XSBundle { 122 def numSrc = backendParams.numSrc 123 // passed from StaticInst 124 val instr = UInt(32.W) 125 val pc = UInt(VAddrBits.W) 126 val foldpc = UInt(MemPredPCWidth.W) 127 val exceptionVec = ExceptionVec() 128 val trigger = new TriggerCf 129 val preDecodeInfo = new PreDecodeInfo 130 val pred_taken = Bool() 131 val crossPageIPFFix = Bool() 132 val ftqPtr = new FtqPtr 133 val ftqOffset = UInt(log2Up(PredictWidth).W) 134 // passed from DecodedInst 135 val srcType = Vec(numSrc, SrcType()) 136 val lsrc = Vec(numSrc, UInt(6.W)) 137 val ldest = UInt(6.W) 138 val fuType = FuType() 139 val fuOpType = FuOpType() 140 val rfWen = Bool() 141 val fpWen = Bool() 142 val vecWen = Bool() 143 val isXSTrap = Bool() 144 val waitForward = Bool() // no speculate execution 145 val blockBackward = Bool() 146 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 147 val canRobCompress = Bool() 148 val selImm = SelImm() 149 val imm = UInt(XLEN.W) // Todo: check if it need minimized 150 val fpu = new FPUCtrlSignals 151 val vpu = new VPUCtrlSignals 152 val wfflags = Bool() 153 val isMove = Bool() 154 val uopIdx = UInt(5.W) 155 val isVset = Bool() 156 val firstUop = Bool() 157 val lastUop = Bool() 158 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 159 val commitType = CommitType() 160 // rename 161 val srcState = Vec(numSrc, SrcState()) 162 val dataSource = Vec(numSrc, DataSource()) 163 val l1ExuOH = Vec(numSrc, ExuOH()) 164 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 165 val pdest = UInt(PhyRegIdxWidth.W) 166 val robIdx = new RobPtr 167 val instrSize = UInt(log2Ceil(RenameWidth + 1).W) 168 val dirtyFs = Bool() 169 170 val eliminatedMove = Bool() 171 // Take snapshot at this CFI inst 172 val snapshot = Bool() 173 val debugInfo = new PerfDebugInfo 174 val storeSetHit = Bool() // inst has been allocated an store set 175 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 176 // Load wait is needed 177 // load inst will not be executed until former store (predicted by mdp) addr calcuated 178 val loadWaitBit = Bool() 179 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 180 // load inst will not be executed until ALL former store addr calcuated 181 val loadWaitStrict = Bool() 182 val ssid = UInt(SSIDWidth.W) 183 // Todo 184 val lqIdx = new LqPtr 185 val sqIdx = new SqPtr 186 // debug module 187 val singleStep = Bool() 188 // schedule 189 val replayInst = Bool() 190 191 def isLUI: Bool = this.fuType === FuType.alu.U && (this.selImm === SelImm.IMM_U || this.selImm === SelImm.IMM_LUI32) 192 def isLUI32: Bool = this.fuType === FuType.alu.U && this.selImm === SelImm.IMM_LUI32 193 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 194 195 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 196 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 197 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 198 199 def srcIsReady: Vec[Bool] = { 200 VecInit(this.srcType.zip(this.srcState).map { 201 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 202 }) 203 } 204 205 def clearExceptions( 206 exceptionBits: Seq[Int] = Seq(), 207 flushPipe : Boolean = false, 208 replayInst : Boolean = false 209 ): DynInst = { 210 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 211 if (!flushPipe) { this.flushPipe := false.B } 212 if (!replayInst) { this.replayInst := false.B } 213 this 214 } 215 216 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen 217 } 218 219 trait BundleSource { 220 var wakeupSource = "undefined" 221 var idx = 0 222 } 223 224 /** 225 * 226 * @param pregIdxWidth index width of preg 227 * @param exuIndices exu indices of wakeup bundle 228 */ 229 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int]) extends Bundle { 230 val rfWen = Bool() 231 val fpWen = Bool() 232 val vecWen = Bool() 233 val pdest = UInt(pregIdxWidth.W) 234 235 /** 236 * @param successor Seq[(psrc, srcType)] 237 * @return Seq[if wakeup psrc] 238 */ 239 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 240 successor.map { case (thatPsrc, srcType) => 241 val pdestMatch = pdest === thatPsrc 242 pdestMatch && ( 243 SrcType.isFp(srcType) && this.fpWen || 244 SrcType.isXp(srcType) && this.rfWen || 245 SrcType.isVp(srcType) && this.vecWen 246 ) && valid 247 } 248 } 249 250 def hasOnlyOneSource: Boolean = exuIndices.size == 1 251 252 def hasMultiSources: Boolean = exuIndices.size > 1 253 254 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 255 256 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 257 258 def exuIdx: Int = { 259 require(hasOnlyOneSource) 260 this.exuIndices.head 261 } 262 } 263 264 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 265 266 } 267 268 class IssueQueueIQWakeUpBundle(exuIdx: Int, backendParams: BackendParams) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 269 val loadDependency = Vec(backendParams.LduCnt + backendParams.HyuCnt, UInt(3.W)) 270 def fromExuInput(exuInput: ExuInput, l2ExuVecs: Vec[UInt]): Unit = { 271 this.rfWen := exuInput.rfWen.getOrElse(false.B) 272 this.fpWen := exuInput.fpWen.getOrElse(false.B) 273 this.vecWen := exuInput.vecWen.getOrElse(false.B) 274 this.pdest := exuInput.pdest 275 } 276 277 def fromExuInput(exuInput: ExuInput): Unit = { 278 this.rfWen := exuInput.rfWen.getOrElse(false.B) 279 this.fpWen := exuInput.fpWen.getOrElse(false.B) 280 this.vecWen := exuInput.vecWen.getOrElse(false.B) 281 this.pdest := exuInput.pdest 282 } 283 } 284 285 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 286 // vtype 287 val vill = Bool() 288 val vma = Bool() // 1: agnostic, 0: undisturbed 289 val vta = Bool() // 1: agnostic, 0: undisturbed 290 val vsew = VSew() 291 val vlmul = VLmul() // 1/8~8 --> -3~3 292 293 val vm = Bool() // 0: need v0.t 294 val vstart = Vl() 295 296 // float rounding mode 297 val frm = Frm() 298 // scalar float instr and vector float reduction 299 val fpu = Fpu() 300 // vector fix int rounding mode 301 val vxrm = Vxrm() 302 // vector uop index, exclude other non-vector uop 303 val vuopIdx = UopIdx() 304 val lastUop = Bool() 305 // maybe used if data dependancy 306 val vmask = UInt(MaskSrcData().dataWidth.W) 307 val vl = Vl() 308 309 // vector load/store 310 val nf = Nf() 311 val veew = VEew() 312 313 val needScalaSrc = Bool() 314 315 val isReverse = Bool() // vrsub, vrdiv 316 val isExt = Bool() 317 val isNarrow = Bool() 318 val isDstMask = Bool() // vvm, vvvm, mmm 319 val isOpMask = Bool() // vmand, vmnand 320 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 321 322 def vtype: VType = { 323 val res = Wire(VType()) 324 res.illegal := this.vill 325 res.vma := this.vma 326 res.vta := this.vta 327 res.vsew := this.vsew 328 res.vlmul := this.vlmul 329 res 330 } 331 332 def vconfig: VConfig = { 333 val res = Wire(VConfig()) 334 res.vtype := this.vtype 335 res.vl := this.vl 336 res 337 } 338 } 339 340 // DynInst --[IssueQueue]--> DataPath 341 class IssueQueueIssueBundle( 342 iqParams: IssueBlockParams, 343 val exuParams: ExeUnitParams, 344 )(implicit 345 p: Parameters 346 ) extends Bundle { 347 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 348 // check which set both have fp and vec and remove fp 349 private val rfReadDataCfgSetFilterFp = rfReadDataCfgSet.map((set: Set[DataConfig]) => 350 if (set.contains(FpData()) && set.contains(VecData())) set.filter(_ != FpData()) 351 else set 352 ) 353 354 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 355 rfReadDataCfgSetFilterFp.map((set: Set[DataConfig]) => 356 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq) 357 ) 358 )) 359 360 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 361 val immType = SelImm() // used to select imm extractor 362 val common = new ExuInput(exuParams) 363 val addrOH = UInt(iqParams.numEntries.W) 364 365 def exuIdx = exuParams.exuIdx 366 def getSource: SchedulerType = exuParams.getWBSource 367 def getIntWbBusyBundle = common.rfWen.toSeq 368 def getVfWbBusyBundle = common.getVfWen.toSeq 369 def getIntRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readInt).toSeq 370 def getVfRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readVf).toSeq 371 372 def getIntRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 373 getIntRfReadBundle.zip(srcType).map { 374 case (rfRd: RfReadPortWithConfig, t: UInt) => 375 makeValid(issueValid && SrcType.isXp(t), rfRd) 376 } 377 } 378 379 def getVfRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 380 getVfRfReadBundle.zip(srcType).map { 381 case (rfRd: RfReadPortWithConfig, t: UInt) => 382 makeValid(issueValid && SrcType.isVfp(t), rfRd) 383 } 384 } 385 386 def getIntRfWriteValidBundle(issueValid: Bool) = { 387 388 } 389 } 390 391 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 392 val issueQueueParams = this.params 393 val og0resp = Valid(new EntryDeqRespBundle) 394 val og1resp = Valid(new EntryDeqRespBundle) 395 } 396 397 class fuBusyRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 398 val respType = RSFeedbackType() // update credit if needs replay 399 val rfWen = Bool() // TODO: use params to identify IntWB/VfWB 400 val fuType = FuType() 401 } 402 403 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 404 private val intCertainLat = params.intLatencyCertain 405 private val vfCertainLat = params.vfLatencyCertain 406 private val intLat = params.intLatencyValMax 407 private val vfLat = params.vfLatencyValMax 408 409 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 410 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 411 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 412 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 413 } 414 415 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 416 private val intCertainLat = params.intLatencyCertain 417 private val vfCertainLat = params.vfLatencyCertain 418 private val intLat = params.intLatencyValMax 419 private val vfLat = params.vfLatencyValMax 420 421 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 422 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 423 } 424 425 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 426 private val intCertainLat = params.intLatencyCertain 427 private val vfCertainLat = params.vfLatencyCertain 428 429 val intConflict = OptionWrapper(intCertainLat, Bool()) 430 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 431 } 432 433 // DataPath --[ExuInput]--> Exu 434 class ExuInput(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 435 val fuType = FuType() 436 val fuOpType = FuOpType() 437 val src = Vec(params.numRegSrc, UInt(params.dataBitsMax.W)) 438 val imm = UInt(XLEN.W) 439 val robIdx = new RobPtr 440 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 441 val isFirstIssue = Bool() // Only used by store yet 442 val pdest = UInt(params.wbPregIdxWidth.W) 443 val rfWen = if (params.writeIntRf) Some(Bool()) else None 444 val fpWen = if (params.writeFpRf) Some(Bool()) else None 445 val vecWen = if (params.writeVecRf) Some(Bool()) else None 446 val fpu = if (params.writeFflags) Some(new FPUCtrlSignals) else None 447 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 448 val flushPipe = if (params.flushPipe) Some(Bool()) else None 449 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 450 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 451 val ftqIdx = if (params.needPc || params.replayInst || params.hasStoreAddrFu) 452 Some(new FtqPtr) else None 453 val ftqOffset = if (params.needPc || params.replayInst || params.hasStoreAddrFu) 454 Some(UInt(log2Up(PredictWidth).W)) else None 455 val predictInfo = if (params.hasPredecode) Some(new Bundle { 456 val target = UInt(VAddrData().dataWidth.W) 457 val taken = Bool() 458 }) else None 459 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 460 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 461 val dataSources = Vec(params.numRegSrc, DataSource()) 462 val l1ExuOH = Vec(params.numRegSrc, ExuOH()) 463 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 464 val loadDependency = OptionWrapper(params.isIQWakeUpSink, Vec(LoadPipelineWidth, UInt(3.W))) 465 val deqLdExuIdx = OptionWrapper(params.hasLoadFu || params.hasHyldaFu, UInt(log2Ceil(LoadPipelineWidth).W)) 466 467 val perfDebugInfo = new PerfDebugInfo() 468 469 def exuIdx = this.params.exuIdx 470 471 def needCancel(og0CancelOH: UInt, og1CancelOH: UInt) : Bool = { 472 if (params.isIQWakeUpSink) { 473 require( 474 og0CancelOH.getWidth == l1ExuOH.head.getWidth, 475 s"cancelVecSize: {og0: ${og0CancelOH.getWidth}, og1: ${og1CancelOH.getWidth}}" 476 ) 477 val l1Cancel: Bool = l1ExuOH.zip(srcTimer.get).map { 478 case(exuOH: UInt, srcTimer: UInt) => 479 (exuOH & og0CancelOH).orR && srcTimer === 1.U 480 }.reduce(_ | _) 481 l1Cancel 482 } else { 483 false.B 484 } 485 } 486 487 def getVfWen = { 488 if (params.writeFpRf) this.fpWen 489 else if(params.writeVecRf) this.vecWen 490 else None 491 } 492 493 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 494 // src is assigned to rfReadData 495 this.fuType := source.common.fuType 496 this.fuOpType := source.common.fuOpType 497 this.imm := source.common.imm 498 this.robIdx := source.common.robIdx 499 this.pdest := source.common.pdest 500 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 501 this.iqIdx := source.common.iqIdx // Only used by mem feedback 502 this.dataSources := source.common.dataSources 503 this.l1ExuOH := source.common.l1ExuOH 504 this.rfWen .foreach(_ := source.common.rfWen.get) 505 this.fpWen .foreach(_ := source.common.fpWen.get) 506 this.vecWen .foreach(_ := source.common.vecWen.get) 507 this.fpu .foreach(_ := source.common.fpu.get) 508 this.vpu .foreach(_ := source.common.vpu.get) 509 this.flushPipe .foreach(_ := source.common.flushPipe.get) 510 this.pc .foreach(_ := source.common.pc.get) 511 this.preDecode .foreach(_ := source.common.preDecode.get) 512 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 513 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 514 this.predictInfo .foreach(_ := source.common.predictInfo.get) 515 this.lqIdx .foreach(_ := source.common.lqIdx.get) 516 this.sqIdx .foreach(_ := source.common.sqIdx.get) 517 this.srcTimer .foreach(_ := source.common.srcTimer.get) 518 this.loadDependency.foreach(_ := source.common.loadDependency.get.map(_ << 1)) 519 this.deqLdExuIdx .foreach(_ := source.common.deqLdExuIdx.get) 520 } 521 } 522 523 // ExuInput --[FuncUnit]--> ExuOutput 524 class ExuOutput( 525 val params: ExeUnitParams, 526 )(implicit 527 val p: Parameters 528 ) extends Bundle with BundleSource with HasXSParameter { 529 val data = UInt(params.dataBitsMax.W) 530 val pdest = UInt(params.wbPregIdxWidth.W) 531 val robIdx = new RobPtr 532 val intWen = if (params.writeIntRf) Some(Bool()) else None 533 val fpWen = if (params.writeFpRf) Some(Bool()) else None 534 val vecWen = if (params.writeVecRf) Some(Bool()) else None 535 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 536 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 537 val wflags = if (params.writeFflags) Some(Bool()) else None 538 val vxsat = if (params.writeVxsat) Some(Bool()) else None 539 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 540 val flushPipe = if (params.flushPipe) Some(Bool()) else None 541 val replay = if (params.replayInst) Some(Bool()) else None 542 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 543 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 544 Some(new SqPtr()) else None 545 // uop info 546 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 547 // vldu used only 548 val vls = OptionWrapper(params.hasVLoadFu, new Bundle { 549 val vpu = new VPUCtrlSignals 550 val oldVdPsrc = UInt(PhyRegIdxWidth.W) 551 val vdIdx = UInt(3.W) 552 val isIndexed = Bool() 553 }) 554 val debug = new DebugBundle 555 val debugInfo = new PerfDebugInfo 556 } 557 558 // ExuOutput + DynInst --> WriteBackBundle 559 class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource { 560 val rfWen = Bool() 561 val fpWen = Bool() 562 val vecWen = Bool() 563 val pdest = UInt(params.pregIdxWidth(backendParams).W) 564 val data = UInt(params.dataWidth.W) 565 val robIdx = new RobPtr()(p) 566 val flushPipe = Bool() 567 val replayInst = Bool() 568 val redirect = ValidIO(new Redirect) 569 val fflags = UInt(5.W) 570 val vxsat = Bool() 571 val exceptionVec = ExceptionVec() 572 val debug = new DebugBundle 573 val debugInfo = new PerfDebugInfo 574 575 this.wakeupSource = s"WB(${params.toString})" 576 577 def fromExuOutput(source: ExuOutput) = { 578 this.rfWen := source.intWen.getOrElse(false.B) 579 this.fpWen := source.fpWen.getOrElse(false.B) 580 this.vecWen := source.vecWen.getOrElse(false.B) 581 this.pdest := source.pdest 582 this.data := source.data 583 this.robIdx := source.robIdx 584 this.flushPipe := source.flushPipe.getOrElse(false.B) 585 this.replayInst := source.replay.getOrElse(false.B) 586 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 587 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 588 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 589 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 590 this.debug := source.debug 591 this.debugInfo := source.debugInfo 592 } 593 594 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 595 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth))) 596 rfWrite.wen := this.rfWen && fire 597 rfWrite.addr := this.pdest 598 rfWrite.data := this.data 599 rfWrite.intWen := this.rfWen 600 rfWrite.fpWen := false.B 601 rfWrite.vecWen := false.B 602 rfWrite 603 } 604 605 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 606 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth))) 607 rfWrite.wen := (this.fpWen || this.vecWen) && fire 608 rfWrite.addr := this.pdest 609 rfWrite.data := this.data 610 rfWrite.intWen := false.B 611 rfWrite.fpWen := this.fpWen 612 rfWrite.vecWen := this.vecWen 613 rfWrite 614 } 615 } 616 617 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 618 // / 619 // [IssueQueue]--> ExuInput -- 620 class ExuBypassBundle( 621 val params: ExeUnitParams, 622 )(implicit 623 val p: Parameters 624 ) extends Bundle { 625 val data = UInt(params.dataBitsMax.W) 626 val pdest = UInt(params.wbPregIdxWidth.W) 627 } 628 629 class ExceptionInfo extends Bundle { 630 val pc = UInt(VAddrData().dataWidth.W) 631 val instr = UInt(32.W) 632 val commitType = CommitType() 633 val exceptionVec = ExceptionVec() 634 val singleStep = Bool() 635 val crossPageIPFFix = Bool() 636 val isInterrupt = Bool() 637 } 638 639 object UopIdx { 640 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 641 } 642 643 object FuLatency { 644 def apply(): UInt = UInt(width.W) 645 646 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 647 } 648 649 object ExuOH { 650 def apply(exuNum: Int): UInt = UInt(exuNum.W) 651 652 def apply()(implicit p: Parameters): UInt = UInt(width.W) 653 654 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 655 } 656 657 class CancelSignal(implicit p: Parameters) extends XSBundle { 658 val rfWen = Bool() 659 val fpWen = Bool() 660 val vecWen = Bool() 661 val pdest = UInt(PhyRegIdxWidth.W) 662 663 def needCancel(srcType: UInt, psrc: UInt, valid: Bool): Bool = { 664 val pdestMatch = pdest === psrc 665 pdestMatch && ( 666 SrcType.isFp(srcType) && !this.rfWen || 667 SrcType.isXp(srcType) && this.rfWen || 668 SrcType.isVp(srcType) && !this.rfWen 669 ) && valid 670 } 671 } 672 673 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 674 val uop = new DynInst 675 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 676 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 677 val isFirstIssue = Bool() 678 val deqPortIdx = UInt(log2Ceil(LoadPipelineWidth).W) 679 680 def src_rs1 = src(0) 681 def src_stride = src(1) 682 def src_vs3 = src(2) 683 def src_mask = if (isVector) src(3) else 0.U 684 def src_vl = if (isVector) src(4) else 0.U 685 } 686 687 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 688 val uop = new DynInst 689 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 690 val mask = if (isVector) Some(UInt(VLEN.W)) else None 691 val vdIdx = if (isVector) Some(UInt(3.W)) else None // TODO: parameterize width 692 val debug = new DebugBundle 693 } 694 695 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 696 val uop = new DynInst 697 val flag = UInt(1.W) 698 } 699 700 object LoadShouldCancel { 701 def apply(loadDependency: Option[Seq[UInt]], ldCancel: Seq[LoadCancelIO]): Bool = { 702 val ld1Cancel = loadDependency.map(deps => 703 deps.zipWithIndex.map { case (dep, ldPortIdx) => 704 ldCancel.map(_.ld1Cancel).map(cancel => cancel.fire && dep(1) && cancel.bits === ldPortIdx.U).reduce(_ || _) 705 }.reduce(_ || _) 706 ) 707 val ld2Cancel = loadDependency.map(deps => 708 deps.zipWithIndex.map { case (dep, ldPortIdx) => 709 ldCancel.map(_.ld2Cancel).map(cancel => cancel.fire && dep(2) && cancel.bits === ldPortIdx.U).reduce(_ || _) 710 }.reduce(_ || _) 711 ) 712 ld1Cancel.map(_ || ld2Cancel.get).getOrElse(false.B) 713 } 714 } 715} 716