1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.BundleUtils.makeValid 8import utils.OptionWrapper 9import xiangshan._ 10import xiangshan.backend.datapath.DataConfig._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.datapath.WbConfig.PregWB 13import xiangshan.backend.decode.{ImmUnion, XDecode} 14import xiangshan.backend.exu.ExeUnitParams 15import xiangshan.backend.fu.FuType 16import xiangshan.backend.fu.fpu.Bundles.Frm 17import xiangshan.backend.fu.vector.Bundles._ 18import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, IssueQueueJumpBundle, SchedulerType, EntryDeqRespBundle} 19import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 20import xiangshan.backend.rob.RobPtr 21import xiangshan.frontend._ 22import xiangshan.mem.{LqPtr, SqPtr} 23 24object Bundles { 25 26 // frontend -> backend 27 class StaticInst(implicit p: Parameters) extends XSBundle { 28 val instr = UInt(32.W) 29 val pc = UInt(VAddrBits.W) 30 val foldpc = UInt(MemPredPCWidth.W) 31 val exceptionVec = ExceptionVec() 32 val trigger = new TriggerCf 33 val preDecodeInfo = new PreDecodeInfo 34 val pred_taken = Bool() 35 val crossPageIPFFix = Bool() 36 val ftqPtr = new FtqPtr 37 val ftqOffset = UInt(log2Up(PredictWidth).W) 38 39 def connectCtrlFlow(source: CtrlFlow): Unit = { 40 this.instr := source.instr 41 this.pc := source.pc 42 this.foldpc := source.foldpc 43 this.exceptionVec := source.exceptionVec 44 this.trigger := source.trigger 45 this.preDecodeInfo := source.pd 46 this.pred_taken := source.pred_taken 47 this.crossPageIPFFix := source.crossPageIPFFix 48 this.ftqPtr := source.ftqPtr 49 this.ftqOffset := source.ftqOffset 50 } 51 } 52 53 // StaticInst --[Decode]--> DecodedInst 54 class DecodedInst(implicit p: Parameters) extends XSBundle { 55 def numSrc = backendParams.numSrc 56 // passed from StaticInst 57 val instr = UInt(32.W) 58 val pc = UInt(VAddrBits.W) 59 val foldpc = UInt(MemPredPCWidth.W) 60 val exceptionVec = ExceptionVec() 61 val trigger = new TriggerCf 62 val preDecodeInfo = new PreDecodeInfo 63 val pred_taken = Bool() 64 val crossPageIPFFix = Bool() 65 val ftqPtr = new FtqPtr 66 val ftqOffset = UInt(log2Up(PredictWidth).W) 67 // decoded 68 val srcType = Vec(numSrc, SrcType()) 69 val lsrc = Vec(numSrc, UInt(6.W)) 70 val ldest = UInt(6.W) 71 val fuType = FuType() 72 val fuOpType = FuOpType() 73 val rfWen = Bool() 74 val fpWen = Bool() 75 val vecWen = Bool() 76 val isXSTrap = Bool() 77 val waitForward = Bool() // no speculate execution 78 val blockBackward = Bool() 79 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 80 val canRobCompress = Bool() 81 val selImm = SelImm() 82 val imm = UInt(ImmUnion.maxLen.W) 83 val fpu = new FPUCtrlSignals 84 val vpu = new VPUCtrlSignals 85 val vlsInstr = Bool() 86 val wfflags = Bool() 87 val isMove = Bool() 88 val uopIdx = UopIdx() 89 val uopSplitType = UopSplitType() 90 val isVset = Bool() 91 val firstUop = Bool() 92 val lastUop = Bool() 93 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 94 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 95 val commitType = CommitType() // Todo: remove it 96 97 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 98 isXSTrap, waitForward, blockBackward, flushPipe, canRobCompress, uopSplitType, selImm) 99 100 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 101 val decoder: Seq[UInt] = ListLookup( 102 inst, XDecode.decodeDefault.map(bitPatToUInt), 103 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 104 ) 105 allSignals zip decoder foreach { case (s, d) => s := d } 106 this 107 } 108 109 def isSoftPrefetch: Bool = { 110 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 111 } 112 113 def connectStaticInst(source: StaticInst): Unit = { 114 for ((name, data) <- this.elements) { 115 if (source.elements.contains(name)) { 116 data := source.elements(name) 117 } 118 } 119 } 120 } 121 122 // DecodedInst --[Rename]--> DynInst 123 class DynInst(implicit p: Parameters) extends XSBundle { 124 def numSrc = backendParams.numSrc 125 // passed from StaticInst 126 val instr = UInt(32.W) 127 val pc = UInt(VAddrBits.W) 128 val foldpc = UInt(MemPredPCWidth.W) 129 val exceptionVec = ExceptionVec() 130 val trigger = new TriggerCf 131 val preDecodeInfo = new PreDecodeInfo 132 val pred_taken = Bool() 133 val crossPageIPFFix = Bool() 134 val ftqPtr = new FtqPtr 135 val ftqOffset = UInt(log2Up(PredictWidth).W) 136 // passed from DecodedInst 137 val srcType = Vec(numSrc, SrcType()) 138 val lsrc = Vec(numSrc, UInt(6.W)) 139 val ldest = UInt(6.W) 140 val fuType = FuType() 141 val fuOpType = FuOpType() 142 val rfWen = Bool() 143 val fpWen = Bool() 144 val vecWen = Bool() 145 val isXSTrap = Bool() 146 val waitForward = Bool() // no speculate execution 147 val blockBackward = Bool() 148 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 149 val canRobCompress = Bool() 150 val selImm = SelImm() 151 val imm = UInt(32.W) 152 val fpu = new FPUCtrlSignals 153 val vpu = new VPUCtrlSignals 154 val vlsInstr = Bool() 155 val wfflags = Bool() 156 val isMove = Bool() 157 val uopIdx = UopIdx() 158 val isVset = Bool() 159 val firstUop = Bool() 160 val lastUop = Bool() 161 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 162 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 163 val commitType = CommitType() 164 // rename 165 val srcState = Vec(numSrc, SrcState()) 166 val srcLoadDependency = Vec(numSrc, Vec(LoadPipelineWidth, UInt(3.W))) 167 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 168 val pdest = UInt(PhyRegIdxWidth.W) 169 val robIdx = new RobPtr 170 val instrSize = UInt(log2Ceil(RenameWidth + 1).W) 171 val dirtyFs = Bool() 172 173 val eliminatedMove = Bool() 174 // Take snapshot at this CFI inst 175 val snapshot = Bool() 176 val debugInfo = new PerfDebugInfo 177 val storeSetHit = Bool() // inst has been allocated an store set 178 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 179 // Load wait is needed 180 // load inst will not be executed until former store (predicted by mdp) addr calcuated 181 val loadWaitBit = Bool() 182 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 183 // load inst will not be executed until ALL former store addr calcuated 184 val loadWaitStrict = Bool() 185 val ssid = UInt(SSIDWidth.W) 186 // Todo 187 val lqIdx = new LqPtr 188 val sqIdx = new SqPtr 189 // debug module 190 val singleStep = Bool() 191 // schedule 192 val replayInst = Bool() 193 194 def isLUI: Bool = this.fuType === FuType.alu.U && (this.selImm === SelImm.IMM_U || this.selImm === SelImm.IMM_LUI32) 195 def isLUI32: Bool = this.selImm === SelImm.IMM_LUI32 196 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 197 198 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 199 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 200 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 201 202 def srcIsReady: Vec[Bool] = { 203 VecInit(this.srcType.zip(this.srcState).map { 204 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 205 }) 206 } 207 208 def clearExceptions( 209 exceptionBits: Seq[Int] = Seq(), 210 flushPipe : Boolean = false, 211 replayInst : Boolean = false 212 ): DynInst = { 213 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 214 if (!flushPipe) { this.flushPipe := false.B } 215 if (!replayInst) { this.replayInst := false.B } 216 this 217 } 218 219 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen 220 } 221 222 trait BundleSource { 223 var wakeupSource = "undefined" 224 var idx = 0 225 } 226 227 /** 228 * 229 * @param pregIdxWidth index width of preg 230 * @param exuIndices exu indices of wakeup bundle 231 */ 232 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int]) extends Bundle { 233 val rfWen = Bool() 234 val fpWen = Bool() 235 val vecWen = Bool() 236 val pdest = UInt(pregIdxWidth.W) 237 238 /** 239 * @param successor Seq[(psrc, srcType)] 240 * @return Seq[if wakeup psrc] 241 */ 242 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 243 successor.map { case (thatPsrc, srcType) => 244 val pdestMatch = pdest === thatPsrc 245 pdestMatch && ( 246 SrcType.isFp(srcType) && this.fpWen || 247 SrcType.isXp(srcType) && this.rfWen || 248 SrcType.isVp(srcType) && this.vecWen 249 ) && valid 250 } 251 } 252 253 def hasOnlyOneSource: Boolean = exuIndices.size == 1 254 255 def hasMultiSources: Boolean = exuIndices.size > 1 256 257 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 258 259 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 260 261 def exuIdx: Int = { 262 require(hasOnlyOneSource) 263 this.exuIndices.head 264 } 265 } 266 267 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 268 269 } 270 271 class IssueQueueIQWakeUpBundle(exuIdx: Int, backendParams: BackendParams) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 272 val loadDependency = Vec(backendParams.LduCnt + backendParams.HyuCnt, UInt(3.W)) 273 def fromExuInput(exuInput: ExuInput, l2ExuVecs: Vec[UInt]): Unit = { 274 this.rfWen := exuInput.rfWen.getOrElse(false.B) 275 this.fpWen := exuInput.fpWen.getOrElse(false.B) 276 this.vecWen := exuInput.vecWen.getOrElse(false.B) 277 this.pdest := exuInput.pdest 278 } 279 280 def fromExuInput(exuInput: ExuInput): Unit = { 281 this.rfWen := exuInput.rfWen.getOrElse(false.B) 282 this.fpWen := exuInput.fpWen.getOrElse(false.B) 283 this.vecWen := exuInput.vecWen.getOrElse(false.B) 284 this.pdest := exuInput.pdest 285 } 286 } 287 288 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 289 // vtype 290 val vill = Bool() 291 val vma = Bool() // 1: agnostic, 0: undisturbed 292 val vta = Bool() // 1: agnostic, 0: undisturbed 293 val vsew = VSew() 294 val vlmul = VLmul() // 1/8~8 --> -3~3 295 296 val vm = Bool() // 0: need v0.t 297 val vstart = Vl() 298 299 // float rounding mode 300 val frm = Frm() 301 // scalar float instr and vector float reduction 302 val fpu = Fpu() 303 // vector fix int rounding mode 304 val vxrm = Vxrm() 305 // vector uop index, exclude other non-vector uop 306 val vuopIdx = UopIdx() 307 val lastUop = Bool() 308 // maybe used if data dependancy 309 val vmask = UInt(MaskSrcData().dataWidth.W) 310 val vl = Vl() 311 312 // vector load/store 313 val nf = Nf() 314 val veew = VEew() 315 316 val isReverse = Bool() // vrsub, vrdiv 317 val isExt = Bool() 318 val isNarrow = Bool() 319 val isDstMask = Bool() // vvm, vvvm, mmm 320 val isOpMask = Bool() // vmand, vmnand 321 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 322 323 def vtype: VType = { 324 val res = Wire(VType()) 325 res.illegal := this.vill 326 res.vma := this.vma 327 res.vta := this.vta 328 res.vsew := this.vsew 329 res.vlmul := this.vlmul 330 res 331 } 332 333 def vconfig: VConfig = { 334 val res = Wire(VConfig()) 335 res.vtype := this.vtype 336 res.vl := this.vl 337 res 338 } 339 340 def connectVType(source: VType): Unit = { 341 this.vill := source.illegal 342 this.vma := source.vma 343 this.vta := source.vta 344 this.vsew := source.vsew 345 this.vlmul := source.vlmul 346 } 347 } 348 349 // DynInst --[IssueQueue]--> DataPath 350 class IssueQueueIssueBundle( 351 iqParams: IssueBlockParams, 352 val exuParams: ExeUnitParams, 353 )(implicit 354 p: Parameters 355 ) extends Bundle { 356 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 357 // check which set both have fp and vec and remove fp 358 private val rfReadDataCfgSetFilterFp = rfReadDataCfgSet.map((set: Set[DataConfig]) => 359 if (set.contains(FpData()) && set.contains(VecData())) set.filter(_ != FpData()) 360 else set 361 ) 362 363 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 364 rfReadDataCfgSetFilterFp.map((set: Set[DataConfig]) => 365 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq) 366 ) 367 )) 368 369 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 370 val immType = SelImm() // used to select imm extractor 371 val common = new ExuInput(exuParams) 372 val addrOH = UInt(iqParams.numEntries.W) 373 374 def exuIdx = exuParams.exuIdx 375 def getSource: SchedulerType = exuParams.getWBSource 376 def getIntWbBusyBundle = common.rfWen.toSeq 377 def getVfWbBusyBundle = common.getVfWen.toSeq 378 def getIntRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readInt).toSeq 379 def getVfRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readVf).toSeq 380 381 def getIntRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 382 getIntRfReadBundle.zip(srcType).map { 383 case (rfRd: RfReadPortWithConfig, t: UInt) => 384 makeValid(issueValid && SrcType.isXp(t), rfRd) 385 } 386 } 387 388 def getVfRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 389 getVfRfReadBundle.zip(srcType).map { 390 case (rfRd: RfReadPortWithConfig, t: UInt) => 391 makeValid(issueValid && SrcType.isVfp(t), rfRd) 392 } 393 } 394 395 def getIntRfWriteValidBundle(issueValid: Bool) = { 396 397 } 398 } 399 400 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 401 val issueQueueParams = this.params 402 val og0resp = Valid(new EntryDeqRespBundle) 403 val og1resp = Valid(new EntryDeqRespBundle) 404 } 405 406 class fuBusyRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 407 val respType = RSFeedbackType() // update credit if needs replay 408 val rfWen = Bool() // TODO: use params to identify IntWB/VfWB 409 val fuType = FuType() 410 } 411 412 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 413 private val intCertainLat = params.intLatencyCertain 414 private val vfCertainLat = params.vfLatencyCertain 415 private val intLat = params.intLatencyValMax 416 private val vfLat = params.vfLatencyValMax 417 418 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 419 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 420 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 421 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 422 } 423 424 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 425 private val intCertainLat = params.intLatencyCertain 426 private val vfCertainLat = params.vfLatencyCertain 427 private val intLat = params.intLatencyValMax 428 private val vfLat = params.vfLatencyValMax 429 430 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 431 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 432 } 433 434 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 435 private val intCertainLat = params.intLatencyCertain 436 private val vfCertainLat = params.vfLatencyCertain 437 438 val intConflict = OptionWrapper(intCertainLat, Bool()) 439 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 440 } 441 442 // DataPath --[ExuInput]--> Exu 443 class ExuInput(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 444 val fuType = FuType() 445 val fuOpType = FuOpType() 446 val src = Vec(params.numRegSrc, UInt(params.dataBitsMax.W)) 447 val imm = UInt(32.W) 448 val robIdx = new RobPtr 449 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 450 val isFirstIssue = Bool() // Only used by store yet 451 val pdest = UInt(params.wbPregIdxWidth.W) 452 val rfWen = if (params.writeIntRf) Some(Bool()) else None 453 val fpWen = if (params.writeFpRf) Some(Bool()) else None 454 val vecWen = if (params.writeVecRf) Some(Bool()) else None 455 val fpu = if (params.writeFflags) Some(new FPUCtrlSignals) else None 456 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 457 val flushPipe = if (params.flushPipe) Some(Bool()) else None 458 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 459 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 460 val ftqIdx = if (params.needPc || params.replayInst || params.hasStoreAddrFu) 461 Some(new FtqPtr) else None 462 val ftqOffset = if (params.needPc || params.replayInst || params.hasStoreAddrFu) 463 Some(UInt(log2Up(PredictWidth).W)) else None 464 val predictInfo = if (params.needPdInfo) Some(new Bundle { 465 val target = UInt(VAddrData().dataWidth.W) 466 val taken = Bool() 467 }) else None 468 val loadWaitBit = OptionWrapper(params.hasLoadExu, Bool()) 469 val waitForRobIdx = OptionWrapper(params.hasLoadExu, new RobPtr) // store set predicted previous store robIdx 470 val storeSetHit = OptionWrapper(params.hasLoadExu, Bool()) // inst has been allocated an store set 471 val loadWaitStrict = OptionWrapper(params.hasLoadExu, Bool()) // load inst will not be executed until ALL former store addr calcuated 472 val ssid = OptionWrapper(params.hasLoadExu, UInt(SSIDWidth.W)) 473 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 474 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 475 val dataSources = Vec(params.numRegSrc, DataSource()) 476 val l1ExuOH = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, ExuOH())) 477 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 478 val loadDependency = OptionWrapper(params.isIQWakeUpSink, Vec(LoadPipelineWidth, UInt(3.W))) 479 val deqLdExuIdx = OptionWrapper(params.hasLoadFu || params.hasHyldaFu, UInt(log2Ceil(LoadPipelineWidth).W)) 480 481 val perfDebugInfo = new PerfDebugInfo() 482 483 def exuIdx = this.params.exuIdx 484 485 def needCancel(og0CancelOH: UInt, og1CancelOH: UInt) : Bool = { 486 if (params.isIQWakeUpSink) { 487 require( 488 og0CancelOH.getWidth == l1ExuOH.get.head.getWidth, 489 s"cancelVecSize: {og0: ${og0CancelOH.getWidth}, og1: ${og1CancelOH.getWidth}}" 490 ) 491 val l1Cancel: Bool = l1ExuOH.get.zip(srcTimer.get).map { 492 case(exuOH: UInt, srcTimer: UInt) => 493 (exuOH & og0CancelOH).orR && srcTimer === 1.U 494 }.reduce(_ | _) 495 l1Cancel 496 } else { 497 false.B 498 } 499 } 500 501 def getVfWen = { 502 if (params.writeFpRf) this.fpWen 503 else if(params.writeVecRf) this.vecWen 504 else None 505 } 506 507 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 508 // src is assigned to rfReadData 509 this.fuType := source.common.fuType 510 this.fuOpType := source.common.fuOpType 511 this.imm := source.common.imm 512 this.robIdx := source.common.robIdx 513 this.pdest := source.common.pdest 514 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 515 this.iqIdx := source.common.iqIdx // Only used by mem feedback 516 this.dataSources := source.common.dataSources 517 this.l1ExuOH .foreach(_ := source.common.l1ExuOH.get) 518 this.rfWen .foreach(_ := source.common.rfWen.get) 519 this.fpWen .foreach(_ := source.common.fpWen.get) 520 this.vecWen .foreach(_ := source.common.vecWen.get) 521 this.fpu .foreach(_ := source.common.fpu.get) 522 this.vpu .foreach(_ := source.common.vpu.get) 523 this.flushPipe .foreach(_ := source.common.flushPipe.get) 524 this.pc .foreach(_ := source.common.pc.get) 525 this.preDecode .foreach(_ := source.common.preDecode.get) 526 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 527 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 528 this.predictInfo .foreach(_ := source.common.predictInfo.get) 529 this.loadWaitBit .foreach(_ := source.common.loadWaitBit.get) 530 this.waitForRobIdx .foreach(_ := source.common.waitForRobIdx.get) 531 this.storeSetHit .foreach(_ := source.common.storeSetHit.get) 532 this.loadWaitStrict.foreach(_ := source.common.loadWaitStrict.get) 533 this.ssid .foreach(_ := source.common.ssid.get) 534 this.lqIdx .foreach(_ := source.common.lqIdx.get) 535 this.sqIdx .foreach(_ := source.common.sqIdx.get) 536 this.srcTimer .foreach(_ := source.common.srcTimer.get) 537 this.loadDependency.foreach(_ := source.common.loadDependency.get.map(_ << 1)) 538 this.deqLdExuIdx .foreach(_ := source.common.deqLdExuIdx.get) 539 } 540 } 541 542 // ExuInput --[FuncUnit]--> ExuOutput 543 class ExuOutput( 544 val params: ExeUnitParams, 545 )(implicit 546 val p: Parameters 547 ) extends Bundle with BundleSource with HasXSParameter { 548 val data = UInt(params.dataBitsMax.W) 549 val pdest = UInt(params.wbPregIdxWidth.W) 550 val robIdx = new RobPtr 551 val intWen = if (params.writeIntRf) Some(Bool()) else None 552 val fpWen = if (params.writeFpRf) Some(Bool()) else None 553 val vecWen = if (params.writeVecRf) Some(Bool()) else None 554 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 555 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 556 val wflags = if (params.writeFflags) Some(Bool()) else None 557 val vxsat = if (params.writeVxsat) Some(Bool()) else None 558 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 559 val flushPipe = if (params.flushPipe) Some(Bool()) else None 560 val replay = if (params.replayInst) Some(Bool()) else None 561 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 562 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 563 Some(new SqPtr()) else None 564 val trigger = if (params.trigger) Some(new TriggerCf) else None 565 // uop info 566 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 567 // vldu used only 568 val vls = OptionWrapper(params.hasVLoadFu, new Bundle { 569 val vpu = new VPUCtrlSignals 570 val oldVdPsrc = UInt(PhyRegIdxWidth.W) 571 val vdIdx = UInt(3.W) 572 val vdIdxInField = UInt(3.W) 573 val isIndexed = Bool() 574 }) 575 val debug = new DebugBundle 576 val debugInfo = new PerfDebugInfo 577 } 578 579 // ExuOutput + DynInst --> WriteBackBundle 580 class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource { 581 val rfWen = Bool() 582 val fpWen = Bool() 583 val vecWen = Bool() 584 val pdest = UInt(params.pregIdxWidth(backendParams).W) 585 val data = UInt(params.dataWidth.W) 586 val robIdx = new RobPtr()(p) 587 val flushPipe = Bool() 588 val replayInst = Bool() 589 val redirect = ValidIO(new Redirect) 590 val fflags = UInt(5.W) 591 val vxsat = Bool() 592 val exceptionVec = ExceptionVec() 593 val debug = new DebugBundle 594 val debugInfo = new PerfDebugInfo 595 596 this.wakeupSource = s"WB(${params.toString})" 597 598 def fromExuOutput(source: ExuOutput) = { 599 this.rfWen := source.intWen.getOrElse(false.B) 600 this.fpWen := source.fpWen.getOrElse(false.B) 601 this.vecWen := source.vecWen.getOrElse(false.B) 602 this.pdest := source.pdest 603 this.data := source.data 604 this.robIdx := source.robIdx 605 this.flushPipe := source.flushPipe.getOrElse(false.B) 606 this.replayInst := source.replay.getOrElse(false.B) 607 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 608 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 609 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 610 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 611 this.debug := source.debug 612 this.debugInfo := source.debugInfo 613 } 614 615 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 616 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth))) 617 rfWrite.wen := this.rfWen && fire 618 rfWrite.addr := this.pdest 619 rfWrite.data := this.data 620 rfWrite.intWen := this.rfWen 621 rfWrite.fpWen := false.B 622 rfWrite.vecWen := false.B 623 rfWrite 624 } 625 626 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 627 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth))) 628 rfWrite.wen := (this.fpWen || this.vecWen) && fire 629 rfWrite.addr := this.pdest 630 rfWrite.data := this.data 631 rfWrite.intWen := false.B 632 rfWrite.fpWen := this.fpWen 633 rfWrite.vecWen := this.vecWen 634 rfWrite 635 } 636 } 637 638 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 639 // / 640 // [IssueQueue]--> ExuInput -- 641 class ExuBypassBundle( 642 val params: ExeUnitParams, 643 )(implicit 644 val p: Parameters 645 ) extends Bundle { 646 val data = UInt(params.dataBitsMax.W) 647 val pdest = UInt(params.wbPregIdxWidth.W) 648 } 649 650 class ExceptionInfo(implicit p: Parameters) extends Bundle { 651 val pc = UInt(VAddrData().dataWidth.W) 652 val instr = UInt(32.W) 653 val commitType = CommitType() 654 val exceptionVec = ExceptionVec() 655 val singleStep = Bool() 656 val crossPageIPFFix = Bool() 657 val isInterrupt = Bool() 658 val vls = Bool() 659 val trigger = new TriggerCf 660 } 661 662 object UopIdx { 663 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 664 } 665 666 object FuLatency { 667 def apply(): UInt = UInt(width.W) 668 669 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 670 } 671 672 object ExuOH { 673 def apply(exuNum: Int): UInt = UInt(exuNum.W) 674 675 def apply()(implicit p: Parameters): UInt = UInt(width.W) 676 677 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 678 } 679 680 class CancelSignal(implicit p: Parameters) extends XSBundle { 681 val rfWen = Bool() 682 val fpWen = Bool() 683 val vecWen = Bool() 684 val pdest = UInt(PhyRegIdxWidth.W) 685 686 def needCancel(srcType: UInt, psrc: UInt, valid: Bool): Bool = { 687 val pdestMatch = pdest === psrc 688 pdestMatch && ( 689 SrcType.isFp(srcType) && !this.rfWen || 690 SrcType.isXp(srcType) && this.rfWen || 691 SrcType.isVp(srcType) && !this.rfWen 692 ) && valid 693 } 694 } 695 696 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 697 val uop = new DynInst 698 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 699 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 700 val isFirstIssue = Bool() 701 val deqPortIdx = UInt(log2Ceil(LoadPipelineWidth).W) 702 703 def src_rs1 = src(0) 704 def src_stride = src(1) 705 def src_vs3 = src(2) 706 def src_mask = if (isVector) src(3) else 0.U 707 def src_vl = if (isVector) src(4) else 0.U 708 } 709 710 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 711 val uop = new DynInst 712 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 713 val mask = if (isVector) Some(UInt(VLEN.W)) else None 714 val vdIdx = if (isVector) Some(UInt(3.W)) else None // TODO: parameterize width 715 val vdIdxInField = if (isVector) Some(UInt(3.W)) else None 716 val debug = new DebugBundle 717 718 def isVls = FuType.isVls(uop.fuType) 719 } 720 721 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 722 val uop = new DynInst 723 val flag = UInt(1.W) 724 } 725 726 object LoadShouldCancel { 727 def apply(loadDependency: Option[Seq[UInt]], ldCancel: Seq[LoadCancelIO]): Bool = { 728 val ld1Cancel = loadDependency.map(deps => 729 deps.zipWithIndex.map { case (dep, ldPortIdx) => 730 ldCancel.map(_.ld1Cancel).map(cancel => cancel.fire && dep(1) && cancel.bits === ldPortIdx.U).reduce(_ || _) 731 }.reduce(_ || _) 732 ) 733 val ld2Cancel = loadDependency.map(deps => 734 deps.zipWithIndex.map { case (dep, ldPortIdx) => 735 ldCancel.map(_.ld2Cancel).map(cancel => cancel.fire && dep(2) && cancel.bits === ldPortIdx.U).reduce(_ || _) 736 }.reduce(_ || _) 737 ) 738 ld1Cancel.map(_ || ld2Cancel.get).getOrElse(false.B) 739 } 740 } 741} 742